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// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP4CGX15BF14C6 Package FBGA169
//
//
// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6,
// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
//
//
// This SDF file should be used for ModelSim-Altera (VHDL) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "full_adder")
(DATE "02/17/2016 22:15:19")
(VENDOR "Altera")
(PROGRAM "Quartus II 64-Bit")
(VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cycloneiv_io_obuf")
(INSTANCE \\SUM\~output\\)
(DELAY
(ABSOLUTE
(PORT i (814:814:814) (741:741:741))
(IOPATH i o (2324:2324:2324) (2217:2217:2217))
)
)
)
(CELL
(CELLTYPE "cycloneiv_io_obuf")
(INSTANCE \\Cout\~output\\)
(DELAY
(ABSOLUTE
(PORT i (1434:1434:1434) (1335:1335:1335))
(IOPATH i o (2211:2211:2211) (2140:2140:2140))
)
)
)
(CELL
(CELLTYPE "cycloneiv_io_ibuf")
(INSTANCE \\X\~input\\)
(DELAY
(ABSOLUTE
(IOPATH i o (498:498:498) (654:654:654))
)
)
)
(CELL
(CELLTYPE "cycloneiv_io_ibuf")
(INSTANCE \\Cin\~input\\)
(DELAY
(ABSOLUTE
(IOPATH i o (498:498:498) (654:654:654))
)
)
)
(CELL
(CELLTYPE "cycloneiv_io_ibuf")
(INSTANCE \\Y\~input\\)
(DELAY
(ABSOLUTE
(IOPATH i o (488:488:488) (644:644:644))
)
)
)
(CELL
(CELLTYPE "cycloneiv_lcell_comb")
(INSTANCE \\inst2\~0\\)
(DELAY
(ABSOLUTE
(PORT dataa (2684:2684:2684) (2884:2884:2884))
(PORT datac (3102:3102:3102) (3326:3326:3326))
(PORT datad (2629:2629:2629) (2825:2825:2825))
(IOPATH dataa combout (318:318:318) (327:327:327))
(IOPATH datac combout (220:220:220) (216:216:216))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneiv_lcell_comb")
(INSTANCE \\inst3\~0\\)
(DELAY
(ABSOLUTE
(PORT dataa (2689:2689:2689) (2890:2890:2890))
(PORT datac (3097:3097:3097) (3321:3321:3321))
(PORT datad (2633:2633:2633) (2830:2830:2830))
(IOPATH dataa combout (307:307:307) (306:306:306))
(IOPATH datac combout (220:220:220) (216:216:216))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
)
|
