diff options
Diffstat (limited to 'ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.rpt')
| -rw-r--r-- | ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.rpt | 1153 |
1 files changed, 1153 insertions, 0 deletions
diff --git a/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.rpt b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.rpt new file mode 100644 index 0000000..5baa30d --- /dev/null +++ b/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.rpt @@ -0,0 +1,1153 @@ +Fitter report for ten_bit_adder_NO_BUS +Thu Feb 18 22:56:43 2016 +Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. I/O Assignment Warnings + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Non-Global High Fan-Out Signals + 21. Routing Usage Summary + 22. LAB Logic Elements + 23. LAB Signals Sourced + 24. LAB Signals Sourced Out + 25. LAB Distinct Inputs + 26. I/O Rules Summary + 27. I/O Rules Details + 28. I/O Rules Matrix + 29. Fitter Device Options + 30. Operating Settings and Conditions + 31. Fitter Messages + 32. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+--------------------------------------------+ +; Fitter Status ; Successful - Thu Feb 18 22:56:43 2016 ; +; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; +; Revision Name ; ten_bit_adder_NO_BUS ; +; Top-level Entity Name ; ten_bit_adder_NO_BUS ; +; Family ; Cyclone IV GX ; +; Device ; EP4CGX15BF14C6 ; +; Timing Models ; Final ; +; Total logic elements ; 21 / 14,400 ( < 1 % ) ; +; Total combinational functions ; 21 / 14,400 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 14,400 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 32 / 81 ( 40 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 552,960 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total GXB Receiver Channel PCS ; 0 / 2 ( 0 % ) ; +; Total GXB Receiver Channel PMA ; 0 / 2 ( 0 % ) ; +; Total GXB Transmitter Channel PCS ; 0 / 2 ( 0 % ) ; +; Total GXB Transmitter Channel PMA ; 0 / 2 ( 0 % ) ; +; Total PLLs ; 0 / 3 ( 0 % ) ; ++------------------------------------+--------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; auto ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Generate GXB Reconfig MIF ; Off ; Off ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Off ; Off ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Active Serial clock source ; FREQ_40MHz ; FREQ_40MHz ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; Cout ; Incomplete set of assignments ; +; S0 ; Incomplete set of assignments ; +; S1 ; Incomplete set of assignments ; +; S2 ; Incomplete set of assignments ; +; S3 ; Incomplete set of assignments ; +; S4 ; Incomplete set of assignments ; +; S5 ; Incomplete set of assignments ; +; S6 ; Incomplete set of assignments ; +; S7 ; Incomplete set of assignments ; +; S8 ; Incomplete set of assignments ; +; S9 ; Incomplete set of assignments ; +; Y9 ; Incomplete set of assignments ; +; ENY ; Incomplete set of assignments ; +; Y8 ; Incomplete set of assignments ; +; Y7 ; Incomplete set of assignments ; +; Y6 ; Incomplete set of assignments ; +; Y5 ; Incomplete set of assignments ; +; Y4 ; Incomplete set of assignments ; +; Y3 ; Incomplete set of assignments ; +; Y2 ; Incomplete set of assignments ; +; Y0 ; Incomplete set of assignments ; +; X0 ; Incomplete set of assignments ; +; Y1 ; Incomplete set of assignments ; +; X1 ; Incomplete set of assignments ; +; X2 ; Incomplete set of assignments ; +; X3 ; Incomplete set of assignments ; +; X4 ; Incomplete set of assignments ; +; X5 ; Incomplete set of assignments ; +; X6 ; Incomplete set of assignments ; +; X7 ; Incomplete set of assignments ; +; X8 ; Incomplete set of assignments ; +; X9 ; Incomplete set of assignments ; ++----------+-------------------------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 96 ) ; 0.00 % ( 0 / 96 ) ; 0.00 % ( 0 / 96 ) ; +; -- Achieved ; 0.00 % ( 0 / 96 ) ; 0.00 % ( 0 / 96 ) ; 0.00 % ( 0 / 96 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 86 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 21 / 14,400 ( < 1 % ) ; +; -- Combinational with no register ; 21 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 18 ; +; -- 3 input functions ; 1 ; +; -- <=2 input functions ; 2 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 21 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 14,733 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 14,400 ( 0 % ) ; +; -- I/O registers ; 0 / 333 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 2 / 900 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 32 / 81 ( 40 % ) ; +; -- Clock pins ; 2 / 6 ( 33 % ) ; +; -- Dedicated input pins ; 0 / 12 ( 0 % ) ; +; ; ; +; Global signals ; 0 ; +; M9Ks ; 0 / 60 ( 0 % ) ; +; Total block memory bits ; 0 / 552,960 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 552,960 ( 0 % ) ; +; PLLs ; 0 / 3 ( 0 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; GXB Receiver channel PCSs ; 0 / 2 ( 0 % ) ; +; GXB Receiver channel PMAs ; 0 / 2 ( 0 % ) ; +; GXB Transmitter channel PCSs ; 0 / 2 ( 0 % ) ; +; GXB Transmitter channel PMAs ; 0 / 2 ( 0 % ) ; +; Impedance control blocks ; 0 / 3 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 1% ; +; Maximum fan-out ; 19 ; +; Highest non-global fan-out ; 19 ; +; Total fan-out ; 127 ; +; Average fan-out ; 1.34 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 21 / 14400 ( < 1 % ) ; 0 / 14400 ( 0 % ) ; +; -- Combinational with no register ; 21 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 18 ; 0 ; +; -- 3 input functions ; 1 ; 0 ; +; -- <=2 input functions ; 2 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 21 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 14400 ( 0 % ) ; 0 / 14400 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 2 / 900 ( < 1 % ) ; 0 / 900 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 32 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; 0 ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 122 ; 5 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 21 ; 0 ; +; -- Output Ports ; 11 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+ +; ENY ; N7 ; 4 ; 16 ; 0 ; 0 ; 19 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; X0 ; L13 ; 5 ; 33 ; 12 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; X1 ; K13 ; 5 ; 33 ; 15 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; X2 ; F13 ; 6 ; 33 ; 16 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; X3 ; F12 ; 6 ; 33 ; 16 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; X4 ; K12 ; 5 ; 33 ; 11 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; X5 ; L9 ; 4 ; 24 ; 0 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; X6 ; K9 ; 4 ; 22 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; X7 ; M6 ; 3 ; 12 ; 0 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; X8 ; N4 ; 3 ; 10 ; 0 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; X9 ; L4 ; 3 ; 8 ; 0 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; Y0 ; A13 ; 7 ; 26 ; 31 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; Y1 ; K10 ; 4 ; 31 ; 0 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; Y2 ; L12 ; 5 ; 33 ; 12 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; Y3 ; N10 ; 4 ; 26 ; 0 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; Y4 ; N12 ; 4 ; 29 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; Y5 ; M13 ; 5 ; 33 ; 10 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; Y6 ; M9 ; 4 ; 24 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; Y7 ; N8 ; 4 ; 20 ; 0 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; Y8 ; N6 ; 3 ; 12 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; +; Y9 ; M7 ; 4 ; 16 ; 0 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Cout ; N9 ; 4 ; 20 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S0 ; J13 ; 5 ; 33 ; 15 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S1 ; H10 ; 5 ; 33 ; 14 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S2 ; N11 ; 4 ; 26 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S3 ; F11 ; 6 ; 33 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S4 ; K11 ; 5 ; 33 ; 11 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S5 ; M11 ; 4 ; 29 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S6 ; N13 ; 5 ; 33 ; 10 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S7 ; L5 ; 3 ; 14 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S8 ; K8 ; 4 ; 22 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; S9 ; L7 ; 3 ; 14 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------+--------------------------+------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------+--------------------------+------------------+---------------------------+ +; L3 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; N3 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; K5 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; J5 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; K6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; N4 ; DIFFIO_B1p, CRC_ERROR ; Use as regular IO ; X8 ; Dual Purpose Pin ; +; N5 ; DIFFIO_B1n, NCEO ; Use as programming pin ; ~ALTERA_NCEO~ ; Dual Purpose Pin ; +; M6 ; DIFFIO_B2p, INIT_DONE ; Use as regular IO ; X7 ; Dual Purpose Pin ; +; A5 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; B5 ; ASDO ; As input tri-stated ; ~ALTERA_ASDO~ ; Dual Purpose Pin ; +; C5 ; NCSO ; As input tri-stated ; ~ALTERA_NCSO~ ; Dual Purpose Pin ; +; A4 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; D5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; C4 ; nCE ; - ; - ; Dedicated Programming Pin ; ++----------+-----------------------+--------------------------+------------------+---------------------------+ + + ++-------------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+------------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCCLKIN Voltage ; ++----------+------------------+---------------+--------------+------------------+ +; QL0 ; 0 / 8 ( 0 % ) ; -- ; -- ; -- ; +; 3 ; 7 / 8 ( 88 % ) ; 2.5V ; -- ; -- ; +; 3A ; 0 / 2 ( 0 % ) ; -- ; -- ; 2.5V ; +; 4 ; 13 / 14 ( 93 % ) ; 2.5V ; -- ; -- ; +; 5 ; 9 / 12 ( 75 % ) ; 2.5V ; -- ; -- ; +; 6 ; 3 / 12 ( 25 % ) ; 2.5V ; -- ; -- ; +; 7 ; 1 / 14 ( 7 % ) ; 2.5V ; -- ; -- ; +; 8A ; 0 / 2 ( 0 % ) ; -- ; -- ; 2.5V ; +; 8 ; 0 / 5 ( 0 % ) ; 2.5V ; -- ; -- ; +; 9 ; 4 / 4 ( 100 % ) ; 2.5V ; -- ; -- ; ++----------+------------------+---------------+--------------+------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; 99 ; 9 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; A2 ; 98 ; 9 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; A3 ; 96 ; 9 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; A4 ; 93 ; 9 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Column I/O ; N ; no ; On ; +; A5 ; 90 ; 9 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Column I/O ; N ; no ; On ; +; A6 ; 89 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 87 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 88 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 81 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A10 ; 82 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A11 ; 79 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 80 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 73 ; 7 ; Y0 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 97 ; 9 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; B4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B5 ; 91 ; 9 ; ~ALTERA_ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Column I/O ; N ; no ; On ; +; B6 ; 86 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B8 ; 77 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 76 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; B11 ; 75 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B13 ; 74 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C1 ; 9 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; C2 ; 8 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; C3 ; ; 9 ; VCCIO9 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C4 ; 95 ; 9 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; C5 ; 92 ; 9 ; ~ALTERA_NCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Column I/O ; N ; no ; On ; +; C6 ; 85 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C7 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C8 ; 78 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C10 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C11 ; 69 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C12 ; 70 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 71 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D3 ; ; ; VCCD_PLL ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; D4 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D5 ; 94 ; 9 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; D6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D7 ; ; 8A ; VCC_CLKIN8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D9 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D10 ; 65 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D11 ; 68 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D12 ; 67 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D13 ; 72 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E1 ; 11 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; +; E2 ; 10 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; +; E3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E4 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E6 ; 83 ; 8A ; GXB_GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; E7 ; 84 ; 8A ; GXB_GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; E8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E10 ; 66 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E11 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E13 ; 63 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; F1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F3 ; ; -- ; VCCL_GXB ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F9 ; 64 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F10 ; 62 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F11 ; 61 ; 6 ; S3 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F12 ; 58 ; 6 ; X3 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F13 ; 57 ; 6 ; X2 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G1 ; 13 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; G2 ; 12 ; QL0 ; GXB_NC ; ; ; ; -- ; ; -- ; -- ; +; G3 ; ; -- ; VCCH_GXB ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G4 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G9 ; 60 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G10 ; 59 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G11 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G13 ; 55 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H3 ; ; -- ; VCCL_GXB ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H10 ; 52 ; 5 ; S1 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H11 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H12 ; 51 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; H13 ; 56 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; J1 ; 15 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; +; J2 ; 14 ; QL0 ; GXB_GND* ; ; ; ; -- ; ; -- ; -- ; +; J3 ; ; -- ; VCCA_GXB ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J4 ; ; ; VCCD_PLL ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J5 ; 19 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; J6 ; 29 ; 3A ; GXB_GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; J7 ; 30 ; 3A ; GXB_GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; J8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCD_PLL ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J13 ; 53 ; 5 ; S0 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; ; -- ; VCCA ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K5 ; 18 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; K6 ; 20 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; K7 ; ; 3A ; VCC_CLKIN3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; 35 ; 4 ; S8 ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; K9 ; 36 ; 4 ; X6 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; K10 ; 43 ; 4 ; Y1 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; K11 ; 48 ; 5 ; S4 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; K12 ; 47 ; 5 ; X4 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; K13 ; 54 ; 5 ; X1 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L1 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ; +; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L3 ; 16 ; 3 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 21 ; 3 ; X9 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; L5 ; 27 ; 3 ; S7 ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; L6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L7 ; 28 ; 3 ; S9 ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; L8 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L9 ; 37 ; 4 ; X5 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; L10 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L11 ; 44 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L12 ; 50 ; 5 ; Y2 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L13 ; 49 ; 5 ; X0 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M2 ; ; -- ; VCCA_GXB ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M4 ; 22 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; 25 ; 3 ; X7 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; M7 ; 31 ; 4 ; Y9 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M9 ; 38 ; 4 ; Y6 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; 41 ; 4 ; S5 ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; 46 ; 5 ; Y5 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N1 ; ; -- ; VCCL_GXB ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N3 ; 17 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; N4 ; 23 ; 3 ; X8 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N5 ; 24 ; 3 ; ~ALTERA_NCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N6 ; 26 ; 3 ; Y8 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N7 ; 32 ; 4 ; ENY ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N8 ; 33 ; 4 ; Y7 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N9 ; 34 ; 4 ; Cout ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N10 ; 39 ; 4 ; Y3 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N11 ; 40 ; 4 ; S2 ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N12 ; 42 ; 4 ; Y4 ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N13 ; 45 ; 5 ; S6 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; ++----------+------------+----------+--------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------+--------------+ +; |ten_bit_adder_NO_BUS ; 21 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 ; 0 ; 21 (2) ; 0 (0) ; 0 (0) ; |ten_bit_adder_NO_BUS ; work ; +; |full_adder:inst10| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |ten_bit_adder_NO_BUS|full_adder:inst10 ; work ; +; |full_adder:inst11| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |ten_bit_adder_NO_BUS|full_adder:inst11 ; work ; +; |full_adder:inst12| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |ten_bit_adder_NO_BUS|full_adder:inst12 ; work ; +; |full_adder:inst13| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |ten_bit_adder_NO_BUS|full_adder:inst13 ; work ; +; |full_adder:inst14| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |ten_bit_adder_NO_BUS|full_adder:inst14 ; work ; +; |full_adder:inst15| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |ten_bit_adder_NO_BUS|full_adder:inst15 ; work ; +; |full_adder:inst16| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |ten_bit_adder_NO_BUS|full_adder:inst16 ; work ; +; |full_adder:inst17| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |ten_bit_adder_NO_BUS|full_adder:inst17 ; work ; +; |full_adder:inst8| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |ten_bit_adder_NO_BUS|full_adder:inst8 ; work ; +; |full_adder:inst9| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |ten_bit_adder_NO_BUS|full_adder:inst9 ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; Cout ; Output ; -- ; -- ; -- ; -- ; -- ; +; S0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S2 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S3 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S4 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S5 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S6 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S7 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S8 ; Output ; -- ; -- ; -- ; -- ; -- ; +; S9 ; Output ; -- ; -- ; -- ; -- ; -- ; +; Y9 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; ENY ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; Y8 ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ; +; Y7 ; Input ; -- ; (6) 1313 ps ; -- ; -- ; -- ; +; Y6 ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ; +; Y5 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Y4 ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ; +; Y3 ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ; +; Y2 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Y0 ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ; +; X0 ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Y1 ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ; +; X1 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; X2 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; X3 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; X4 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; X5 ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ; +; X6 ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ; +; X7 ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ; +; X8 ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ; +; X9 ; Input ; (6) 1313 ps ; -- ; -- ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+------+ + + ++----------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++----------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++----------------------------------+-------------------+---------+ +; Y9 ; ; ; +; ENY ; ; ; +; Y8 ; ; ; +; - full_adder:inst16|inst3~0 ; 0 ; 6 ; +; - full_adder:inst16|inst2~0 ; 0 ; 6 ; +; Y7 ; ; ; +; - full_adder:inst15|inst3~0 ; 1 ; 6 ; +; - full_adder:inst15|inst2~0 ; 1 ; 6 ; +; Y6 ; ; ; +; - full_adder:inst14|inst3~0 ; 0 ; 6 ; +; - full_adder:inst14|inst2~0 ; 0 ; 6 ; +; Y5 ; ; ; +; - full_adder:inst13|inst3~0 ; 0 ; 6 ; +; - full_adder:inst13|inst2~0 ; 0 ; 6 ; +; Y4 ; ; ; +; - full_adder:inst12|inst3~0 ; 0 ; 6 ; +; - full_adder:inst12|inst2~0 ; 0 ; 6 ; +; Y3 ; ; ; +; - full_adder:inst11|inst3~0 ; 0 ; 6 ; +; - full_adder:inst11|inst2~0 ; 0 ; 6 ; +; Y2 ; ; ; +; - full_adder:inst10|inst3~0 ; 0 ; 6 ; +; - full_adder:inst10|inst2~0 ; 0 ; 6 ; +; Y0 ; ; ; +; - inst6 ; 0 ; 6 ; +; - full_adder:inst8|inst ; 0 ; 6 ; +; X0 ; ; ; +; - full_adder:inst9|inst3~0 ; 1 ; 6 ; +; - full_adder:inst8|inst ; 1 ; 6 ; +; - full_adder:inst9|inst2 ; 1 ; 6 ; +; Y1 ; ; ; +; - inst7 ; 0 ; 6 ; +; X1 ; ; ; +; - full_adder:inst9|inst3~0 ; 0 ; 6 ; +; - full_adder:inst9|inst2 ; 0 ; 6 ; +; X2 ; ; ; +; X3 ; ; ; +; X4 ; ; ; +; - full_adder:inst12|inst3~0 ; 0 ; 6 ; +; - full_adder:inst12|inst2~0 ; 0 ; 6 ; +; X5 ; ; ; +; - full_adder:inst13|inst3~0 ; 0 ; 6 ; +; - full_adder:inst13|inst2~0 ; 0 ; 6 ; +; X6 ; ; ; +; - full_adder:inst14|inst3~0 ; 0 ; 6 ; +; - full_adder:inst14|inst2~0 ; 0 ; 6 ; +; X7 ; ; ; +; - full_adder:inst15|inst3~0 ; 0 ; 6 ; +; - full_adder:inst15|inst2~0 ; 0 ; 6 ; +; X8 ; ; ; +; - full_adder:inst16|inst3~0 ; 0 ; 6 ; +; - full_adder:inst16|inst2~0 ; 0 ; 6 ; +; X9 ; ; ; +; - full_adder:inst17|inst3~0 ; 0 ; 6 ; +; - full_adder:inst17|inst2~0 ; 0 ; 6 ; ++----------------------------------+-------------------+---------+ + + ++-------------------------------------+ +; Non-Global High Fan-Out Signals ; ++---------------------------+---------+ +; Name ; Fan-Out ; ++---------------------------+---------+ +; ENY~input ; 19 ; +; X0~input ; 3 ; +; X9~input ; 2 ; +; X8~input ; 2 ; +; X7~input ; 2 ; +; X6~input ; 2 ; +; X5~input ; 2 ; +; X4~input ; 2 ; +; X3~input ; 2 ; +; X2~input ; 2 ; +; X1~input ; 2 ; +; Y0~input ; 2 ; +; Y2~input ; 2 ; +; Y3~input ; 2 ; +; Y4~input ; 2 ; +; Y5~input ; 2 ; +; Y6~input ; 2 ; +; Y7~input ; 2 ; +; Y8~input ; 2 ; +; Y9~input ; 2 ; +; full_adder:inst16|inst3~0 ; 2 ; +; full_adder:inst15|inst3~0 ; 2 ; +; full_adder:inst14|inst3~0 ; 2 ; +; full_adder:inst13|inst3~0 ; 2 ; +; full_adder:inst12|inst3~0 ; 2 ; +; full_adder:inst11|inst3~0 ; 2 ; +; full_adder:inst10|inst3~0 ; 2 ; +; full_adder:inst9|inst3~0 ; 2 ; +; inst7 ; 2 ; +; inst6 ; 2 ; +; Y1~input ; 1 ; +; full_adder:inst17|inst2~0 ; 1 ; +; full_adder:inst16|inst2~0 ; 1 ; +; full_adder:inst15|inst2~0 ; 1 ; +; full_adder:inst14|inst2~0 ; 1 ; +; full_adder:inst13|inst2~0 ; 1 ; +; full_adder:inst12|inst2~0 ; 1 ; +; full_adder:inst11|inst2~0 ; 1 ; +; full_adder:inst10|inst2~0 ; 1 ; +; full_adder:inst9|inst2 ; 1 ; +; full_adder:inst8|inst ; 1 ; +; full_adder:inst17|inst3~0 ; 1 ; ++---------------------------+---------+ + + ++-----------------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------------------+-----------------------+ +; Routing Resource Type ; Usage ; ++-----------------------------------+-----------------------+ +; Block interconnects ; 34 / 42,960 ( < 1 % ) ; +; C16 interconnects ; 11 / 1,518 ( < 1 % ) ; +; C4 interconnects ; 44 / 26,928 ( < 1 % ) ; +; Direct links ; 0 / 42,960 ( 0 % ) ; +; GXB block output buffers ; 0 / 1,200 ( 0 % ) ; +; Global clocks ; 0 / 20 ( 0 % ) ; +; Interquad Reference Clock Outputs ; 0 / 1 ( 0 % ) ; +; Interquad TXRX Clocks ; 0 / 8 ( 0 % ) ; +; Interquad TXRX PCSRX outputs ; 0 / 4 ( 0 % ) ; +; Interquad TXRX PCSTX outputs ; 0 / 4 ( 0 % ) ; +; Local interconnects ; 9 / 14,400 ( < 1 % ) ; +; R24 interconnects ; 8 / 1,710 ( < 1 % ) ; +; R4 interconnects ; 31 / 37,740 ( < 1 % ) ; ++-----------------------------------+-----------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 10.50) ; Number of LABs (Total = 2) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 1 ; +; 16 ; 0 ; ++---------------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 10.50) ; Number of LABs (Total = 2) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 6.00) ; Number of LABs (Total = 2) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 11.50) ; Number of LABs (Total = 2) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 21 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 32 ; 32 ; 0 ; 11 ; 0 ; 0 ; 21 ; 0 ; 11 ; 21 ; 0 ; 0 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 32 ; 32 ; 32 ; 32 ; 32 ; 0 ; 32 ; 32 ; 0 ; 0 ; 32 ; 21 ; 32 ; 32 ; 11 ; 32 ; 21 ; 11 ; 32 ; 32 ; 32 ; 21 ; 32 ; 32 ; 32 ; 32 ; 32 ; 0 ; 32 ; 32 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Cout ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S2 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S3 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S4 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S5 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S6 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S7 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S8 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; S9 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Y9 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ENY ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Y8 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Y7 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Y6 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Y5 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Y4 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Y3 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Y2 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Y0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; X0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Y1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; X1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; X2 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; X3 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; X4 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; X5 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; X6 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; X7 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; X8 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; X9 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++-----------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+----------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+----------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Active Serial clock source ; 40 MHz Internal Oscillator ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; DCLK ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+----------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119004): Automatically selected device EP4CGX15BF14C6 for design ten_bit_adder_NO_BUS +Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'. +Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CGX30BF14C6 is compatible + Info (176445): Device EP4CGX22BF14C6 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_NCEO~ is reserved at location N5 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location A5 + Info (169125): Pin ~ALTERA_ASDO~ is reserved at location B5 + Info (169125): Pin ~ALTERA_NCSO~ is reserved at location C5 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location A4 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 32 pins of 32 total pins + Info (169086): Pin Cout not assigned to an exact location on the device + Info (169086): Pin S0 not assigned to an exact location on the device + Info (169086): Pin S1 not assigned to an exact location on the device + Info (169086): Pin S2 not assigned to an exact location on the device + Info (169086): Pin S3 not assigned to an exact location on the device + Info (169086): Pin S4 not assigned to an exact location on the device + Info (169086): Pin S5 not assigned to an exact location on the device + Info (169086): Pin S6 not assigned to an exact location on the device + Info (169086): Pin S7 not assigned to an exact location on the device + Info (169086): Pin S8 not assigned to an exact location on the device + Info (169086): Pin S9 not assigned to an exact location on the device + Info (169086): Pin Y9 not assigned to an exact location on the device + Info (169086): Pin ENY not assigned to an exact location on the device + Info (169086): Pin Y8 not assigned to an exact location on the device + Info (169086): Pin Y7 not assigned to an exact location on the device + Info (169086): Pin Y6 not assigned to an exact location on the device + Info (169086): Pin Y5 not assigned to an exact location on the device + Info (169086): Pin Y4 not assigned to an exact location on the device + Info (169086): Pin Y3 not assigned to an exact location on the device + Info (169086): Pin Y2 not assigned to an exact location on the device + Info (169086): Pin Y0 not assigned to an exact location on the device + Info (169086): Pin X0 not assigned to an exact location on the device + Info (169086): Pin Y1 not assigned to an exact location on the device + Info (169086): Pin X1 not assigned to an exact location on the device + Info (169086): Pin X2 not assigned to an exact location on the device + Info (169086): Pin X3 not assigned to an exact location on the device + Info (169086): Pin X4 not assigned to an exact location on the device + Info (169086): Pin X5 not assigned to an exact location on the device + Info (169086): Pin X6 not assigned to an exact location on the device + Info (169086): Pin X7 not assigned to an exact location on the device + Info (169086): Pin X8 not assigned to an exact location on the device + Info (169086): Pin X9 not assigned to an exact location on the device +Critical Warning (332012): Synopsys Design Constraints File file not found: 'ten_bit_adder_NO_BUS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 32 (unused VREF, 2.5V VCCIO, 21 input, 11 output, 0 bidirectional) + Info (176212): I/O standards used: 2.5 V. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 0 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 7 pins available + Info (176213): I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 2 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available + Info (176213): I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 2 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 5 pins available + Info (176213): I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 0 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y0 to location X33_Y9 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.13 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (144001): Generated suppressed messages file C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 911 megabytes + Info: Processing ended: Thu Feb 18 22:56:44 2016 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:06 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/Asus/Documents/GitHub/ten_bit_adder_NO_BUS/output_files/ten_bit_adder_NO_BUS.fit.smsg. + + |