diff options
Diffstat (limited to 'ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo')
| -rw-r--r-- | ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo | 437 |
1 files changed, 437 insertions, 0 deletions
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo new file mode 100644 index 0000000..f1b4d56 --- /dev/null +++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_85c_vhd_slow.sdo @@ -0,0 +1,437 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CGX15BF14C6 Package FBGA169 +// + +// +// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6, +// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "ten_d_flip_flop") + (DATE "02/19/2016 16:48:21") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[9\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1037:1037:1037) (1073:1073:1073)) + (IOPATH i o (2534:2534:2534) (2436:2436:2436)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[8\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (345:345:345) (382:382:382)) + (IOPATH i o (2745:2745:2745) (2674:2674:2674)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[7\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (527:527:527) (546:546:546)) + (IOPATH i o (2659:2659:2659) (2557:2557:2557)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[6\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (616:616:616) (662:662:662)) + (IOPATH i o (2745:2745:2745) (2674:2674:2674)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[5\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1265:1265:1265) (1369:1369:1369)) + (IOPATH i o (2544:2544:2544) (2446:2446:2446)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[4\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (615:615:615) (645:645:645)) + (IOPATH i o (2745:2745:2745) (2674:2674:2674)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[3\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (877:877:877) (925:925:925)) + (IOPATH i o (2649:2649:2649) (2547:2547:2547)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[2\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1023:1023:1023) (1071:1071:1071)) + (IOPATH i o (2534:2534:2534) (2436:2436:2436)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[1\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (345:345:345) (382:382:382)) + (IOPATH i o (2589:2589:2589) (2486:2486:2486)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[0\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (611:611:611) (651:651:651)) + (IOPATH i o (3425:3425:3425) (3387:3387:3387)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\CLK\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (527:527:527) (701:701:701)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_clkctrl") + (INSTANCE \\CLK\~inputclkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (390:390:390) (378:378:378)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[9\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (525:525:525) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst9) + (DELAY + (ABSOLUTE + (PORT clk (1430:1430:1430) (1401:1401:1401)) + (PORT asdata (1778:1778:1778) (1758:1758:1758)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[8\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (515:515:515) (688:688:688)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst8) + (DELAY + (ABSOLUTE + (PORT clk (1422:1422:1422) (1399:1399:1399)) + (PORT asdata (1458:1458:1458) (1444:1444:1444)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[7\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (537:537:537) (711:711:711)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst7) + (DELAY + (ABSOLUTE + (PORT clk (1449:1449:1449) (1425:1425:1425)) + (PORT asdata (3750:3750:3750) (4006:4006:4006)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[6\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (525:525:525) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_lcell_comb") + (INSTANCE \\inst6\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (3385:3385:3385) (3658:3658:3658)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst6) + (DELAY + (ABSOLUTE + (PORT clk (1428:1428:1428) (1403:1403:1403)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[5\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (537:537:537) (711:711:711)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst5) + (DELAY + (ABSOLUTE + (PORT clk (1450:1450:1450) (1425:1425:1425)) + (PORT asdata (3393:3393:3393) (3633:3633:3633)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[4\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (525:525:525) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_lcell_comb") + (INSTANCE \\inst4\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (3079:3079:3079) (3352:3352:3352)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst4) + (DELAY + (ABSOLUTE + (PORT clk (1431:1431:1431) (1402:1402:1402)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[3\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (535:535:535) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_lcell_comb") + (INSTANCE \\inst3\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (3011:3011:3011) (3264:3264:3264)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst3) + (DELAY + (ABSOLUTE + (PORT clk (1435:1435:1435) (1410:1410:1410)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[2\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (517:517:517) (691:691:691)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_lcell_comb") + (INSTANCE \\inst2\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (3064:3064:3064) (3315:3315:3315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst2) + (DELAY + (ABSOLUTE + (PORT clk (1456:1456:1456) (1430:1430:1430)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[1\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (525:525:525) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst1) + (DELAY + (ABSOLUTE + (PORT clk (1432:1432:1432) (1409:1409:1409)) + (PORT asdata (3461:3461:3461) (3731:3731:3731)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[0\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (535:535:535) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_lcell_comb") + (INSTANCE \\inst\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (3078:3078:3078) (3341:3341:3341)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst) + (DELAY + (ABSOLUTE + (PORT clk (1434:1434:1434) (1409:1409:1409)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) +) |