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Diffstat (limited to 'ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_slow.vho')
| -rw-r--r-- | ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_slow.vho | 621 |
1 files changed, 621 insertions, 0 deletions
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_slow.vho b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_slow.vho new file mode 100644 index 0000000..5ebc801 --- /dev/null +++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_slow.vho @@ -0,0 +1,621 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +-- DATE "02/19/2016 16:48:20" + +-- +-- Device: Altera EP4CGX15BF14C6 Package FBGA169 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY ALTERA; +LIBRARY CYCLONEIV; +LIBRARY IEEE; +USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL; +USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY ten_d_flip_flop IS + PORT ( + Q : OUT std_logic_vector(9 DOWNTO 0); + CLK : IN std_logic; + D : IN std_logic_vector(9 DOWNTO 0) + ); +END ten_d_flip_flop; + +-- Design Ports Information +-- Q[9] => Location: PIN_M11, I/O Standard: 2.5 V, Current Strength: Default +-- Q[8] => Location: PIN_G9, I/O Standard: 2.5 V, Current Strength: Default +-- Q[7] => Location: PIN_C13, I/O Standard: 2.5 V, Current Strength: Default +-- Q[6] => Location: PIN_J13, I/O Standard: 2.5 V, Current Strength: Default +-- Q[5] => Location: PIN_N12, I/O Standard: 2.5 V, Current Strength: Default +-- Q[4] => Location: PIN_L13, I/O Standard: 2.5 V, Current Strength: Default +-- Q[3] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default +-- Q[2] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +-- Q[1] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default +-- Q[0] => Location: PIN_E13, I/O Standard: 2.5 V, Current Strength: Default +-- D[9] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default +-- CLK => Location: PIN_J7, I/O Standard: 2.5 V, Current Strength: Default +-- D[8] => Location: PIN_F12, I/O Standard: 2.5 V, Current Strength: Default +-- D[7] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default +-- D[6] => Location: PIN_F11, I/O Standard: 2.5 V, Current Strength: Default +-- D[5] => Location: PIN_D13, I/O Standard: 2.5 V, Current Strength: Default +-- D[4] => Location: PIN_K12, I/O Standard: 2.5 V, Current Strength: Default +-- D[3] => Location: PIN_D10, I/O Standard: 2.5 V, Current Strength: Default +-- D[2] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default +-- D[1] => Location: PIN_F10, I/O Standard: 2.5 V, Current Strength: Default +-- D[0] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF ten_d_flip_flop IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_Q : std_logic_vector(9 DOWNTO 0); +SIGNAL ww_CLK : std_logic; +SIGNAL ww_D : std_logic_vector(9 DOWNTO 0); +SIGNAL \CLK~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \Q[9]~output_o\ : std_logic; +SIGNAL \Q[8]~output_o\ : std_logic; +SIGNAL \Q[7]~output_o\ : std_logic; +SIGNAL \Q[6]~output_o\ : std_logic; +SIGNAL \Q[5]~output_o\ : std_logic; +SIGNAL \Q[4]~output_o\ : std_logic; +SIGNAL \Q[3]~output_o\ : std_logic; +SIGNAL \Q[2]~output_o\ : std_logic; +SIGNAL \Q[1]~output_o\ : std_logic; +SIGNAL \Q[0]~output_o\ : std_logic; +SIGNAL \CLK~input_o\ : std_logic; +SIGNAL \CLK~inputclkctrl_outclk\ : std_logic; +SIGNAL \D[9]~input_o\ : std_logic; +SIGNAL \inst9~q\ : std_logic; +SIGNAL \D[8]~input_o\ : std_logic; +SIGNAL \inst8~q\ : std_logic; +SIGNAL \D[7]~input_o\ : std_logic; +SIGNAL \inst7~q\ : std_logic; +SIGNAL \D[6]~input_o\ : std_logic; +SIGNAL \inst6~feeder_combout\ : std_logic; +SIGNAL \inst6~q\ : std_logic; +SIGNAL \D[5]~input_o\ : std_logic; +SIGNAL \inst5~q\ : std_logic; +SIGNAL \D[4]~input_o\ : std_logic; +SIGNAL \inst4~feeder_combout\ : std_logic; +SIGNAL \inst4~q\ : std_logic; +SIGNAL \D[3]~input_o\ : std_logic; +SIGNAL \inst3~feeder_combout\ : std_logic; +SIGNAL \inst3~q\ : std_logic; +SIGNAL \D[2]~input_o\ : std_logic; +SIGNAL \inst2~feeder_combout\ : std_logic; +SIGNAL \inst2~q\ : std_logic; +SIGNAL \D[1]~input_o\ : std_logic; +SIGNAL \inst1~q\ : std_logic; +SIGNAL \D[0]~input_o\ : std_logic; +SIGNAL \inst~feeder_combout\ : std_logic; +SIGNAL \inst~q\ : std_logic; + +BEGIN + +Q <= ww_Q; +ww_CLK <= CLK; +ww_D <= D; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; + +\CLK~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \CLK~input_o\); + +-- Location: IOOBUF_X29_Y0_N9 +\Q[9]~output\ : cycloneiv_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst9~q\, + devoe => ww_devoe, + o => \Q[9]~output_o\); + +-- Location: IOOBUF_X33_Y22_N2 +\Q[8]~output\ : cycloneiv_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst8~q\, + devoe => ww_devoe, + o => \Q[8]~output_o\); + +-- Location: IOOBUF_X29_Y31_N2 +\Q[7]~output\ : cycloneiv_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst7~q\, + devoe => ww_devoe, + o => \Q[7]~output_o\); + +-- Location: IOOBUF_X33_Y15_N9 +\Q[6]~output\ : cycloneiv_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst6~q\, + devoe => ww_devoe, + o => \Q[6]~output_o\); + +-- Location: IOOBUF_X29_Y0_N2 +\Q[5]~output\ : cycloneiv_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst5~q\, + devoe => ww_devoe, + o => \Q[5]~output_o\); + +-- Location: IOOBUF_X33_Y12_N9 +\Q[4]~output\ : cycloneiv_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst4~q\, + devoe => ww_devoe, + o => \Q[4]~output_o\); + +-- Location: IOOBUF_X26_Y31_N2 +\Q[3]~output\ : cycloneiv_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3~q\, + devoe => ww_devoe, + o => \Q[3]~output_o\); + +-- Location: IOOBUF_X10_Y31_N2 +\Q[2]~output\ : cycloneiv_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2~q\, + devoe => ww_devoe, + o => \Q[2]~output_o\); + +-- Location: IOOBUF_X33_Y25_N2 +\Q[1]~output\ : cycloneiv_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1~q\, + devoe => ww_devoe, + o => \Q[1]~output_o\); + +-- Location: IOOBUF_X33_Y25_N9 +\Q[0]~output\ : cycloneiv_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst~q\, + devoe => ww_devoe, + o => \Q[0]~output_o\); + +-- Location: IOIBUF_X16_Y0_N15 +\CLK~input\ : cycloneiv_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_CLK, + o => \CLK~input_o\); + +-- Location: CLKCTRL_G17 +\CLK~inputclkctrl\ : cycloneiv_clkctrl +-- pragma translate_off +GENERIC MAP ( + clock_type => "global clock", + ena_register_mode => "none") +-- pragma translate_on +PORT MAP ( + inclk => \CLK~inputclkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \CLK~inputclkctrl_outclk\); + +-- Location: IOIBUF_X33_Y16_N8 +\D[9]~input\ : cycloneiv_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_D(9), + o => \D[9]~input_o\); + +-- Location: FF_X32_Y7_N1 +inst9 : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLK~inputclkctrl_outclk\, + asdata => \D[9]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst9~q\); + +-- Location: IOIBUF_X33_Y16_N1 +\D[8]~input\ : cycloneiv_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_D(8), + o => \D[8]~input_o\); + +-- Location: FF_X32_Y22_N9 +inst8 : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLK~inputclkctrl_outclk\, + asdata => \D[8]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst8~q\); + +-- Location: IOIBUF_X26_Y31_N8 +\D[7]~input\ : cycloneiv_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_D(7), + o => \D[7]~input_o\); + +-- Location: FF_X29_Y30_N1 +inst7 : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLK~inputclkctrl_outclk\, + asdata => \D[7]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst7~q\); + +-- Location: IOIBUF_X33_Y24_N8 +\D[6]~input\ : cycloneiv_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_D(6), + o => \D[6]~input_o\); + +-- Location: LCCOMB_X32_Y19_N8 +\inst6~feeder\ : cycloneiv_lcell_comb +-- Equation(s): +-- \inst6~feeder_combout\ = \D[6]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \D[6]~input_o\, + combout => \inst6~feeder_combout\); + +-- Location: FF_X32_Y19_N9 +inst6 : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLK~inputclkctrl_outclk\, + d => \inst6~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst6~q\); + +-- Location: IOIBUF_X29_Y31_N8 +\D[5]~input\ : cycloneiv_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_D(5), + o => \D[5]~input_o\); + +-- Location: FF_X30_Y30_N17 +inst5 : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLK~inputclkctrl_outclk\, + asdata => \D[5]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst5~q\); + +-- Location: IOIBUF_X33_Y11_N8 +\D[4]~input\ : cycloneiv_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_D(4), + o => \D[4]~input_o\); + +-- Location: LCCOMB_X32_Y10_N16 +\inst4~feeder\ : cycloneiv_lcell_comb +-- Equation(s): +-- \inst4~feeder_combout\ = \D[4]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \D[4]~input_o\, + combout => \inst4~feeder_combout\); + +-- Location: FF_X32_Y10_N17 +inst4 : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLK~inputclkctrl_outclk\, + d => \inst4~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst4~q\); + +-- Location: IOIBUF_X33_Y27_N8 +\D[3]~input\ : cycloneiv_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_D(3), + o => \D[3]~input_o\); + +-- Location: LCCOMB_X30_Y27_N0 +\inst3~feeder\ : cycloneiv_lcell_comb +-- Equation(s): +-- \inst3~feeder_combout\ = \D[3]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \D[3]~input_o\, + combout => \inst3~feeder_combout\); + +-- Location: FF_X30_Y27_N1 +inst3 : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLK~inputclkctrl_outclk\, + d => \inst3~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst3~q\); + +-- Location: IOIBUF_X24_Y31_N1 +\D[2]~input\ : cycloneiv_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_D(2), + o => \D[2]~input_o\); + +-- Location: LCCOMB_X23_Y30_N16 +\inst2~feeder\ : cycloneiv_lcell_comb +-- Equation(s): +-- \inst2~feeder_combout\ = \D[2]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \D[2]~input_o\, + combout => \inst2~feeder_combout\); + +-- Location: FF_X23_Y30_N17 +inst2 : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLK~inputclkctrl_outclk\, + d => \inst2~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2~q\); + +-- Location: IOIBUF_X33_Y24_N1 +\D[1]~input\ : cycloneiv_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_D(1), + o => \D[1]~input_o\); + +-- Location: FF_X32_Y25_N9 +inst1 : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLK~inputclkctrl_outclk\, + asdata => \D[1]~input_o\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst1~q\); + +-- Location: IOIBUF_X33_Y27_N1 +\D[0]~input\ : cycloneiv_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_D(0), + o => \D[0]~input_o\); + +-- Location: LCCOMB_X32_Y26_N8 +\inst~feeder\ : cycloneiv_lcell_comb +-- Equation(s): +-- \inst~feeder_combout\ = \D[0]~input_o\ + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datad => \D[0]~input_o\, + combout => \inst~feeder_combout\); + +-- Location: FF_X32_Y26_N9 +inst : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLK~inputclkctrl_outclk\, + d => \inst~feeder_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst~q\); + +ww_Q(9) <= \Q[9]~output_o\; + +ww_Q(8) <= \Q[8]~output_o\; + +ww_Q(7) <= \Q[7]~output_o\; + +ww_Q(6) <= \Q[6]~output_o\; + +ww_Q(5) <= \Q[5]~output_o\; + +ww_Q(4) <= \Q[4]~output_o\; + +ww_Q(3) <= \Q[3]~output_o\; + +ww_Q(2) <= \Q[2]~output_o\; + +ww_Q(1) <= \Q[1]~output_o\; + +ww_Q(0) <= \Q[0]~output_o\; +END structure; + + |