1 files changed, 8 insertions, 0 deletions
diff --git a/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/_primary.vhd b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/_primary.vhd
new file mode 100644
index 0000000..61a9062
--- /dev/null
+++ b/bcd_to_display/simulation/qsim/work/bcd_to_display_vlg_sample_tst/_primary.vhd
@@ -0,0 +1,8 @@
+library verilog;
+use verilog.vl_types.all;
+entity bcd_to_display_vlg_sample_tst is
+    port(
+        BCDin           : in     vl_logic_vector(3 downto 0);
+        sampler_tx      : out    vl_logic
+    );
+end bcd_to_display_vlg_sample_tst;