diff options
Diffstat (limited to 'ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo')
| -rw-r--r-- | ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo | 437 |
1 files changed, 437 insertions, 0 deletions
diff --git a/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo new file mode 100644 index 0000000..e134099 --- /dev/null +++ b/ten_d_flip_flop/simulation/modelsim/ten_d_flip_flop_6_1200mv_0c_vhd_slow.sdo @@ -0,0 +1,437 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CGX15BF14C6 Package FBGA169 +// + +// +// This file contains Slow Corner delays for the design using part EP4CGX15BF14C6, +// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "ten_d_flip_flop") + (DATE "02/19/2016 16:48:21") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[9\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (962:962:962) (959:959:959)) + (IOPATH i o (2211:2211:2211) (2140:2140:2140)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[8\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (317:317:317) (339:339:339)) + (IOPATH i o (2429:2429:2429) (2341:2341:2341)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[7\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (490:490:490) (486:486:486)) + (IOPATH i o (2354:2354:2354) (2247:2247:2247)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[6\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (569:569:569) (593:593:593)) + (IOPATH i o (2429:2429:2429) (2341:2341:2341)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[5\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1172:1172:1172) (1225:1225:1225)) + (IOPATH i o (2221:2221:2221) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[4\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (567:567:567) (577:577:577)) + (IOPATH i o (2429:2429:2429) (2341:2341:2341)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[3\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (816:816:816) (830:830:830)) + (IOPATH i o (2344:2344:2344) (2237:2237:2237)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[2\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (950:950:950) (951:951:951)) + (IOPATH i o (2211:2211:2211) (2140:2140:2140)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[1\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (317:317:317) (339:339:339)) + (IOPATH i o (2261:2261:2261) (2188:2188:2188)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Q\[0\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (562:562:562) (580:580:580)) + (IOPATH i o (2993:2993:2993) (2959:2959:2959)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\CLK\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (508:508:508) (664:664:664)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_clkctrl") + (INSTANCE \\CLK\~inputclkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (342:342:342) (340:340:340)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[9\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (505:505:505) (659:659:659)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst9) + (DELAY + (ABSOLUTE + (PORT clk (1266:1266:1266) (1246:1246:1246)) + (PORT asdata (1596:1596:1596) (1595:1595:1595)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[8\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (495:495:495) (649:649:649)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst8) + (DELAY + (ABSOLUTE + (PORT clk (1259:1259:1259) (1242:1242:1242)) + (PORT asdata (1307:1307:1307) (1312:1312:1312)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[7\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (518:518:518) (674:674:674)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst7) + (DELAY + (ABSOLUTE + (PORT clk (1280:1280:1280) (1271:1271:1271)) + (PORT asdata (3261:3261:3261) (3456:3456:3456)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[6\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (505:505:505) (659:659:659)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_lcell_comb") + (INSTANCE \\inst6\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (2937:2937:2937) (3148:3148:3148)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst6) + (DELAY + (ABSOLUTE + (PORT clk (1263:1263:1263) (1248:1248:1248)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[5\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (518:518:518) (674:674:674)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst5) + (DELAY + (ABSOLUTE + (PORT clk (1280:1280:1280) (1271:1271:1271)) + (PORT asdata (2931:2931:2931) (3119:3119:3119)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[4\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (505:505:505) (659:659:659)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_lcell_comb") + (INSTANCE \\inst4\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (2665:2665:2665) (2867:2867:2867)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst4) + (DELAY + (ABSOLUTE + (PORT clk (1266:1266:1266) (1247:1247:1247)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[3\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (515:515:515) (669:669:669)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_lcell_comb") + (INSTANCE \\inst3\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (2606:2606:2606) (2789:2789:2789)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst3) + (DELAY + (ABSOLUTE + (PORT clk (1270:1270:1270) (1255:1255:1255)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[2\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (498:498:498) (654:654:654)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_lcell_comb") + (INSTANCE \\inst2\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (2637:2637:2637) (2834:2834:2834)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst2) + (DELAY + (ABSOLUTE + (PORT clk (1286:1286:1286) (1276:1276:1276)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[1\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (505:505:505) (659:659:659)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst1) + (DELAY + (ABSOLUTE + (PORT clk (1267:1267:1267) (1252:1252:1252)) + (PORT asdata (3004:3004:3004) (3208:3208:3208)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_ibuf") + (INSTANCE \\D\[0\]\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (515:515:515) (669:669:669)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_lcell_comb") + (INSTANCE \\inst\~feeder\\) + (DELAY + (ABSOLUTE + (PORT datad (2658:2658:2658) (2860:2860:2860)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE inst) + (DELAY + (ABSOLUTE + (PORT clk (1269:1269:1269) (1254:1254:1254)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) +) |