diff options
Diffstat (limited to 'ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_vhd_fast.sdo')
| -rw-r--r-- | ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_vhd_fast.sdo | 676 |
1 files changed, 676 insertions, 0 deletions
diff --git a/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_vhd_fast.sdo b/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_vhd_fast.sdo new file mode 100644 index 0000000..43549a6 --- /dev/null +++ b/ten_bit_adder/simulation/modelsim/ten_bit_adder_min_1200mv_0c_vhd_fast.sdo @@ -0,0 +1,676 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CGX15BF14C6 Package FBGA169 +// + +// +// This file contains Fast Corner delays for the design using part EP4CGX15BF14C6, +// with speed grade M, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "ten_bit_adder") + (DATE "02/18/2016 22:20:18") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\Cout\~output\\) + (DELAY + (ABSOLUTE + (PORT i (544:544:544) (598:598:598)) + (IOPATH i o (1723:1723:1723) (1675:1675:1675)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\S\[9\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (553:553:553) (617:617:617)) + (IOPATH i o (1733:1733:1733) (1685:1685:1685)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\S\[8\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (532:532:532) (589:589:589)) + (IOPATH i o (1630:1630:1630) (1619:1619:1619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\S\[7\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (696:696:696) (763:763:763)) + (IOPATH i o (1723:1723:1723) (1675:1675:1675)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\S\[6\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1248:1248:1248) (1414:1414:1414)) + (IOPATH i o (1545:1545:1545) (1518:1518:1518)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\S\[5\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (580:580:580) (647:647:647)) + (IOPATH i o (1733:1733:1733) (1685:1685:1685)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_io_obuf") + (INSTANCE \\S\[4\]\~output\\) + (DELAY + (ABSOLUTE + (PORT i (874:874:874) (981:981:981)) + (IOPATH i o (1555:1555:1555) (1528:1528:1528)) + ) + ) + ) + (CELL + (CELLTYPE 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(IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_lcell_comb") + (INSTANCE inst7) + (DELAY + (ABSOLUTE + (PORT datab (2208:2208:2208) (2471:2471:2471)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneiv_lcell_comb") + (INSTANCE inst6) + (DELAY + (ABSOLUTE + (PORT datab (2094:2094:2094) (2342:2342:2342)) + (PORT datac (2163:2163:2163) (2430:2430:2430)) + (PORT datad (2194:2194:2194) (2449:2449:2449)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) +) |