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|
TimeQuest Timing Analyzer report for full_adder
Wed Feb 17 22:15:16 2016
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1200mV 85C Model Fmax Summary
6. Timing Closure Recommendations
7. Slow 1200mV 85C Model Setup Summary
8. Slow 1200mV 85C Model Hold Summary
9. Slow 1200mV 85C Model Recovery Summary
10. Slow 1200mV 85C Model Removal Summary
11. Slow 1200mV 85C Model Minimum Pulse Width Summary
12. Propagation Delay
13. Minimum Propagation Delay
14. Slow 1200mV 85C Model Metastability Report
15. Slow 1200mV 0C Model Fmax Summary
16. Slow 1200mV 0C Model Setup Summary
17. Slow 1200mV 0C Model Hold Summary
18. Slow 1200mV 0C Model Recovery Summary
19. Slow 1200mV 0C Model Removal Summary
20. Slow 1200mV 0C Model Minimum Pulse Width Summary
21. Propagation Delay
22. Minimum Propagation Delay
23. Slow 1200mV 0C Model Metastability Report
24. Fast 1200mV 0C Model Setup Summary
25. Fast 1200mV 0C Model Hold Summary
26. Fast 1200mV 0C Model Recovery Summary
27. Fast 1200mV 0C Model Removal Summary
28. Fast 1200mV 0C Model Minimum Pulse Width Summary
29. Propagation Delay
30. Minimum Propagation Delay
31. Fast 1200mV 0C Model Metastability Report
32. Multicorner Timing Analysis Summary
33. Propagation Delay
34. Minimum Propagation Delay
35. Board Trace Model Assignments
36. Input Transition Times
37. Signal Integrity Metrics (Slow 1200mv 0c Model)
38. Signal Integrity Metrics (Slow 1200mv 85c Model)
39. Signal Integrity Metrics (Fast 1200mv 0c Model)
40. Clock Transfers
41. Report TCCS
42. Report RSKM
43. Unconstrained Paths
44. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; full_adder ;
; Device Family ; Cyclone IV GX ;
; Device Name ; EP4CGX15BF14C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+--------------------+----------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
----------
; Clocks ;
----------
No clocks to report.
--------------------------------------
; Slow 1200mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
---------------------------------------
; Slow 1200mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.
--------------------------------------
; Slow 1200mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.
------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
-----------------------------------------------------
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
No paths to report.
+----------------------------------------------------------+
; Propagation Delay ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+-------+-------+-------+-------+
; Cin ; Cout ; 8.391 ; ; ; 8.732 ;
; Cin ; SUM ; 7.822 ; 7.666 ; 8.288 ; 8.164 ;
; X ; Cout ; 8.048 ; ; ; 8.353 ;
; X ; SUM ; 7.483 ; 7.353 ; 7.927 ; 7.794 ;
; Y ; Cout ; 7.770 ; ; ; 8.036 ;
; Y ; SUM ; 7.192 ; 7.038 ; 7.621 ; 7.458 ;
+------------+-------------+-------+-------+-------+-------+
+----------------------------------------------------------+
; Minimum Propagation Delay ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+-------+-------+-------+-------+
; Cin ; Cout ; 8.099 ; ; ; 8.430 ;
; Cin ; SUM ; 7.557 ; 7.403 ; 8.012 ; 7.889 ;
; X ; Cout ; 7.721 ; ; ; 8.010 ;
; X ; SUM ; 7.171 ; 7.046 ; 7.614 ; 7.452 ;
; Y ; Cout ; 7.505 ; ; ; 7.763 ;
; Y ; SUM ; 6.955 ; 6.803 ; 7.373 ; 7.212 ;
+------------+-------------+-------+-------+-------+-------+
----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.
-------------------------------------
; Slow 1200mV 0C Model Fmax Summary ;
-------------------------------------
No paths to report.
--------------------------------------
; Slow 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Slow 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
+----------------------------------------------------------+
; Propagation Delay ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+-------+-------+-------+-------+
; Cin ; Cout ; 7.460 ; ; ; 7.666 ;
; Cin ; SUM ; 6.958 ; 6.763 ; 7.320 ; 7.154 ;
; X ; Cout ; 7.139 ; ; ; 7.325 ;
; X ; SUM ; 6.638 ; 6.467 ; 6.994 ; 6.819 ;
; Y ; Cout ; 6.885 ; ; ; 7.044 ;
; Y ; SUM ; 6.374 ; 6.181 ; 6.723 ; 6.522 ;
+------------+-------------+-------+-------+-------+-------+
+----------------------------------------------------------+
; Minimum Propagation Delay ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+-------+-------+-------+-------+
; Cin ; Cout ; 7.198 ; ; ; 7.401 ;
; Cin ; SUM ; 6.721 ; 6.530 ; 7.076 ; 6.913 ;
; X ; Cout ; 6.844 ; ; ; 7.021 ;
; X ; SUM ; 6.358 ; 6.197 ; 6.713 ; 6.517 ;
; Y ; Cout ; 6.648 ; ; ; 6.805 ;
; Y ; SUM ; 6.162 ; 5.973 ; 6.502 ; 6.307 ;
+------------+-------------+-------+-------+-------+-------+
---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
--------------------------------------
; Fast 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Fast 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
+----------------------------------------------------------+
; Propagation Delay ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+-------+-------+-------+-------+
; Cin ; Cout ; 4.812 ; ; ; 5.483 ;
; Cin ; SUM ; 4.496 ; 4.512 ; 5.107 ; 5.141 ;
; X ; Cout ; 4.631 ; ; ; 5.247 ;
; X ; SUM ; 4.312 ; 4.341 ; 4.886 ; 4.906 ;
; Y ; Cout ; 4.475 ; ; ; 5.067 ;
; Y ; SUM ; 4.150 ; 4.169 ; 4.703 ; 4.715 ;
+------------+-------------+-------+-------+-------+-------+
+----------------------------------------------------------+
; Minimum Propagation Delay ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+-------+-------+-------+-------+
; Cin ; Cout ; 4.643 ; ; ; 5.302 ;
; Cin ; SUM ; 4.342 ; 4.356 ; 4.943 ; 4.977 ;
; X ; Cout ; 4.441 ; ; ; 5.043 ;
; X ; SUM ; 4.131 ; 4.157 ; 4.698 ; 4.706 ;
; Y ; Cout ; 4.319 ; ; ; 4.902 ;
; Y ; SUM ; 4.009 ; 4.028 ; 4.556 ; 4.568 ;
+------------+-------------+-------+-------+-------+-------+
---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+-------+------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
+------------------+-------+------+----------+---------+---------------------+
+----------------------------------------------------------+
; Propagation Delay ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+-------+-------+-------+-------+
; Cin ; Cout ; 8.391 ; ; ; 8.732 ;
; Cin ; SUM ; 7.822 ; 7.666 ; 8.288 ; 8.164 ;
; X ; Cout ; 8.048 ; ; ; 8.353 ;
; X ; SUM ; 7.483 ; 7.353 ; 7.927 ; 7.794 ;
; Y ; Cout ; 7.770 ; ; ; 8.036 ;
; Y ; SUM ; 7.192 ; 7.038 ; 7.621 ; 7.458 ;
+------------+-------------+-------+-------+-------+-------+
+----------------------------------------------------------+
; Minimum Propagation Delay ;
+------------+-------------+-------+-------+-------+-------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+-------+-------+-------+-------+
; Cin ; Cout ; 4.643 ; ; ; 5.302 ;
; Cin ; SUM ; 4.342 ; 4.356 ; 4.943 ; 4.977 ;
; X ; Cout ; 4.441 ; ; ; 5.043 ;
; X ; SUM ; 4.131 ; 4.157 ; 4.698 ; 4.706 ;
; Y ; Cout ; 4.319 ; ; ; 4.902 ;
; Y ; SUM ; 4.009 ; 4.028 ; 4.556 ; 4.568 ;
+------------+-------------+-------+-------+-------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; SUM ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; Cout ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; ~ALTERA_NCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+-------------------------------------------------------------------+
; Input Transition Times ;
+----------------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+----------------+--------------+-----------------+-----------------+
; X ; 2.5 V ; 2000 ps ; 2000 ps ;
; Y ; 2.5 V ; 2000 ps ; 2000 ps ;
; Cin ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_ASDO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_NCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
+----------------+--------------+-----------------+-----------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; SUM ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.29e-09 V ; 2.39 V ; -0.00317 V ; 0.179 V ; 0.007 V ; 4.7e-10 s ; 4.72e-10 s ; No ; Yes ; 2.32 V ; 7.29e-09 V ; 2.39 V ; -0.00317 V ; 0.179 V ; 0.007 V ; 4.7e-10 s ; 4.72e-10 s ; No ; Yes ;
; Cout ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.29e-09 V ; 2.39 V ; -0.00339 V ; 0.206 V ; 0.007 V ; 2.77e-10 s ; 3.24e-10 s ; Yes ; Yes ; 2.32 V ; 7.29e-09 V ; 2.39 V ; -0.00339 V ; 0.206 V ; 0.007 V ; 2.77e-10 s ; 3.24e-10 s ; Yes ; Yes ;
; ~ALTERA_NCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.76e-09 V ; 2.4 V ; -0.034 V ; 0.102 V ; 0.065 V ; 2.49e-10 s ; 3.49e-10 s ; Yes ; Yes ; 2.32 V ; 4.76e-09 V ; 2.4 V ; -0.034 V ; 0.102 V ; 0.065 V ; 2.49e-10 s ; 3.49e-10 s ; Yes ; Yes ;
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.94e-09 V ; 2.39 V ; -0.0344 V ; 0.156 V ; 0.089 V ; 2.68e-10 s ; 2.6e-10 s ; Yes ; Yes ; 2.32 V ; 5.94e-09 V ; 2.39 V ; -0.0344 V ; 0.156 V ; 0.089 V ; 2.68e-10 s ; 2.6e-10 s ; Yes ; Yes ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; SUM ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.21e-06 V ; 2.36 V ; -0.00833 V ; 0.113 V ; 0.035 V ; 6.32e-10 s ; 5.89e-10 s ; No ; Yes ; 2.32 V ; 1.21e-06 V ; 2.36 V ; -0.00833 V ; 0.113 V ; 0.035 V ; 6.32e-10 s ; 5.89e-10 s ; No ; Yes ;
; Cout ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.21e-06 V ; 2.37 V ; -0.00606 V ; 0.107 V ; 0.021 V ; 4.26e-10 s ; 4.03e-10 s ; Yes ; Yes ; 2.32 V ; 1.21e-06 V ; 2.37 V ; -0.00606 V ; 0.107 V ; 0.021 V ; 4.26e-10 s ; 4.03e-10 s ; Yes ; Yes ;
; ~ALTERA_NCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.93e-07 V ; 2.37 V ; -0.0278 V ; 0.106 V ; 0.115 V ; 2.69e-10 s ; 4.05e-10 s ; Yes ; Yes ; 2.32 V ; 7.93e-07 V ; 2.37 V ; -0.0278 V ; 0.106 V ; 0.115 V ; 2.69e-10 s ; 4.05e-10 s ; Yes ; Yes ;
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.76e-07 V ; 2.36 V ; -0.00439 V ; 0.088 V ; 0.007 V ; 4.05e-10 s ; 3.35e-10 s ; Yes ; Yes ; 2.32 V ; 9.76e-07 V ; 2.36 V ; -0.00439 V ; 0.088 V ; 0.007 V ; 4.05e-10 s ; 3.35e-10 s ; Yes ; Yes ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; SUM ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.66e-08 V ; 2.72 V ; -0.0215 V ; 0.161 V ; 0.061 V ; 4.44e-10 s ; 4.06e-10 s ; No ; Yes ; 2.62 V ; 4.66e-08 V ; 2.72 V ; -0.0215 V ; 0.161 V ; 0.061 V ; 4.44e-10 s ; 4.06e-10 s ; No ; Yes ;
; Cout ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.66e-08 V ; 2.73 V ; -0.0205 V ; 0.17 V ; 0.027 V ; 2.58e-10 s ; 2.57e-10 s ; Yes ; Yes ; 2.62 V ; 4.66e-08 V ; 2.73 V ; -0.0205 V ; 0.17 V ; 0.027 V ; 2.58e-10 s ; 2.57e-10 s ; Yes ; Yes ;
; ~ALTERA_NCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.06e-08 V ; 2.86 V ; -0.0341 V ; 0.364 V ; 0.046 V ; 1.17e-10 s ; 2.6e-10 s ; No ; Yes ; 2.62 V ; 3.06e-08 V ; 2.86 V ; -0.0341 V ; 0.364 V ; 0.046 V ; 1.17e-10 s ; 2.6e-10 s ; No ; Yes ;
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.81e-08 V ; 2.72 V ; -0.0542 V ; 0.144 V ; 0.087 V ; 2.55e-10 s ; 2.14e-10 s ; Yes ; Yes ; 2.62 V ; 3.81e-08 V ; 2.72 V ; -0.0542 V ; 0.144 V ; 0.087 V ; 2.55e-10 s ; 2.14e-10 s ; Yes ; Yes ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-------------------
; Clock Transfers ;
-------------------
Nothing to report.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 3 ; 3 ;
; Unconstrained Input Port Paths ; 6 ; 6 ;
; Unconstrained Output Ports ; 2 ; 2 ;
; Unconstrained Output Port Paths ; 6 ; 6 ;
+---------------------------------+-------+------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Feb 17 22:15:12 2016
Info: Command: quartus_sta full_adder -c full_adder
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'full_adder.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (332159): No clocks to report
Info: Analyzing Slow 1200mV 85C Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1200mV 0C Model
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 519 megabytes
Info: Processing ended: Wed Feb 17 22:15:16 2016
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:03
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