adding verilog stop clock made purely in verilog

117 files changed, 32205 insertions, 0 deletions

diff --git a/stopClockVerilog/counter.bsf b/stopClockVerilog/counter.bsf
new file mode 100644
index 0000000..8046255
--- /dev/null
+++ b/stopClockVerilog/counter.bsf
@@ -0,0 +1,78 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 168 128)
+	(text "counter" (rect 5 0 34 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 20 12)(font "Arial" ))
+		(text "clock" (rect 21 27 41 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "b0" (rect 0 0 9 12)(font "Arial" ))
+		(text "b0" (rect 21 43 30 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "b1" (rect 0 0 8 12)(font "Arial" ))
+		(text "b1" (rect 21 59 29 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 152 32)
+		(output)
+		(text "c0[3..0]" (rect 0 0 29 12)(font "Arial" ))
+		(text "c0[3..0]" (rect 102 27 131 39)(font "Arial" ))
+		(line (pt 152 32)(pt 136 32)(line_width 3))
+	)
+	(port
+		(pt 152 48)
+		(output)
+		(text "c1[3..0]" (rect 0 0 28 12)(font "Arial" ))
+		(text "c1[3..0]" (rect 103 43 131 55)(font "Arial" ))
+		(line (pt 152 48)(pt 136 48)(line_width 3))
+	)
+	(port
+		(pt 152 64)
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+		(text "c2[3..0]" (rect 0 0 29 12)(font "Arial" ))
+		(text "c2[3..0]" (rect 102 59 131 71)(font "Arial" ))
+		(line (pt 152 64)(pt 136 64)(line_width 3))
+	)
+	(port
+		(pt 152 80)
+		(output)
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+		(text "c3[3..0]" (rect 102 75 131 87)(font "Arial" ))
+		(line (pt 152 80)(pt 136 80)(line_width 3))
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+	(drawing
+		(rectangle (rect 16 16 136 96)(line_width 1))
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diff --git a/stopClockVerilog/db/.cmp.kpt b/stopClockVerilog/db/.cmp.kpt
new file mode 100644
index 0000000..bb6c787
--- /dev/null
+++ b/stopClockVerilog/db/.cmp.kpt
diff --git a/stopClockVerilog/db/logic_util_heursitic.dat b/stopClockVerilog/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..bb61f26
--- /dev/null
+++ b/stopClockVerilog/db/logic_util_heursitic.dat
diff --git a/stopClockVerilog/db/prev_cmp_stopclock.qmsg b/stopClockVerilog/db/prev_cmp_stopclock.qmsg
new file mode 100644
index 0000000..5d97003
--- /dev/null
+++ b/stopClockVerilog/db/prev_cmp_stopclock.qmsg
@@ -0,0 +1,146 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456932057549 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932057549 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:20:57 2016 " "Processing started: Wed Mar 02 15:20:57 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932057549 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456932057549 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off stopclock -c stopclock " "Command: quartus_map --read_settings_files=on --write_settings_files=off stopclock -c stopclock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456932057549 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1456932057960 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "stopclock.v(11) " "Verilog HDL information at stopclock.v(11): always construct contains both blocking and non-blocking assignments" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 11 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1456932058014 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "stopclock.v(40) " "Verilog HDL information at stopclock.v(40): always construct contains both blocking and non-blocking assignments" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 40 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1456932058015 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stopclock.v 4 4 " "Found 4 design units, including 4 entities, in source file stopclock.v" { { "Info" "ISGN_ENTITY_NAME" "1 hundred_hertz_clock " "Found entity 1: hundred_hertz_clock" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932058016 ""} { "Info" "ISGN_ENTITY_NAME" "2 counter " "Found entity 2: counter" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 31 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932058016 ""} { "Info" "ISGN_ENTITY_NAME" "3 dec_to_seven_segment " "Found entity 3: dec_to_seven_segment" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 80 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932058016 ""} { "Info" "ISGN_ENTITY_NAME" "4 stopclock " "Found entity 4: stopclock" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 122 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932058016 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456932058016 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "stopClock.bdf " "Can't analyze file -- file stopClock.bdf is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1456932058025 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stopclockblock.bdf 1 1 " "Found 1 design units, including 1 entities, in source file stopclockblock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 stopClockBlock " "Found entity 1: stopClockBlock" {  } { { "stopClockBlock.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopClockBlock.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932058028 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456932058028 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "stopclock " "Elaborating entity \"stopclock\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456932058073 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hundred_hertz_clock hundred_hertz_clock:clockConv " "Elaborating entity \"hundred_hertz_clock\" for hierarchy \"hundred_hertz_clock:clockConv\"" {  } { { "stopclock.v" "clockConv" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 133 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456932058076 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:timeCount " "Elaborating entity \"counter\" for hierarchy \"counter:timeCount\"" {  } { { "stopclock.v" "timeCount" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 134 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456932058078 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec_to_seven_segment dec_to_seven_segment:dss0 " "Elaborating entity \"dec_to_seven_segment\" for hierarchy \"dec_to_seven_segment:dss0\"" {  } { { "stopclock.v" "dss0" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 135 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456932058080 ""}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "out stopclock.v(87) " "Verilog HDL Always Construct warning at stopclock.v(87): inferring latch(es) for variable \"out\", which holds its previous value in one or more paths through the always construct" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 87 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[0\] stopclock.v(89) " "Inferred latch for \"out\[0\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[1\] stopclock.v(89) " "Inferred latch for \"out\[1\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[2\] stopclock.v(89) " "Inferred latch for \"out\[2\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[3\] stopclock.v(89) " "Inferred latch for \"out\[3\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[4\] stopclock.v(89) " "Inferred latch for \"out\[4\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[5\] stopclock.v(89) " "Inferred latch for \"out\[5\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[6\] stopclock.v(89) " "Inferred latch for \"out\[6\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "decimal_point GND " "Pin \"decimal_point\" is stuck at GND" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 124 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456932058587 "|stopclock|decimal_point"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1456932058587 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1456932058723 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.map.smsg " "Generated suppressed messages file C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1456932058926 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1456932059026 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456932059026 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "148 " "Implemented 148 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1456932059101 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1456932059101 ""} { "Info" "ICUT_CUT_TM_LCELLS" "115 " "Implemented 115 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1456932059101 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1456932059101 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "506 " "Peak virtual memory: 506 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932059125 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:20:59 2016 " "Processing ended: Wed Mar 02 15:20:59 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932059125 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932059125 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932059125 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456932059125 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456932061249 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932061251 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:21:00 2016 " "Processing started: Wed Mar 02 15:21:00 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932061251 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1456932061251 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off stopclock -c stopclock " "Command: quartus_fit --read_settings_files=off --write_settings_files=off stopclock -c stopclock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1456932061251 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1456932061367 ""}
+{ "Info" "0" "" "Project  = stopclock" {  } {  } 0 0 "Project  = stopclock" 0 0 "Fitter" 0 0 1456932061367 ""}
+{ "Info" "0" "" "Revision = stopclock" {  } {  } 0 0 "Revision = stopclock" 0 0 "Fitter" 0 0 1456932061368 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1456932061432 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "stopclock EP3C16U484C6 " "Selected device EP3C16U484C6 for design \"stopclock\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1456932061439 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456932061494 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456932061495 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456932061495 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1456932061585 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1456932061599 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40U484C6 " "Device EP3C40U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456932061894 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55U484C6 " "Device EP3C55U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456932061894 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80U484C6 " "Device EP3C80U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456932061894 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1456932061894 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 287 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932061896 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 289 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932061896 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 291 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932061896 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 293 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932061896 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 295 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932061896 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1456932061896 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1456932061897 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "33 33 " "No exact pin location assignment(s) for 33 pins of 33 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[0\] " "Pin hex0\[0\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[0] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 13 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[1\] " "Pin hex0\[1\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[1] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 14 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[2\] " "Pin hex0\[2\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[2] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 15 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[3\] " "Pin hex0\[3\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[3] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 16 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[4\] " "Pin hex0\[4\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[4] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 17 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[5\] " "Pin hex0\[5\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[5] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 18 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[6\] " "Pin hex0\[6\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[6] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 19 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[0\] " "Pin hex1\[0\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[0] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 20 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[1\] " "Pin hex1\[1\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[1] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 21 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[2\] " "Pin hex1\[2\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[2] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 22 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[3\] " "Pin hex1\[3\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[3] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 23 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[4\] " "Pin hex1\[4\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[4] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 24 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[5\] " "Pin hex1\[5\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[5] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 25 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[6\] " "Pin hex1\[6\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[6] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 26 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[0\] " "Pin hex2\[0\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[0] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 27 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[1\] " "Pin hex2\[1\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[1] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 28 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[2\] " "Pin hex2\[2\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[2] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 29 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[3\] " "Pin hex2\[3\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[3] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 30 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[4\] " "Pin hex2\[4\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[4] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 31 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[5\] " "Pin hex2\[5\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[5] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 32 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[6\] " "Pin hex2\[6\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[6] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 33 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[0\] " "Pin hex3\[0\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[0] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 34 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[1\] " "Pin hex3\[1\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[1] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 35 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[2\] " "Pin hex3\[2\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[2] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 36 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[3\] " "Pin hex3\[3\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[3] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 37 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[4\] " "Pin hex3\[4\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[4] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 38 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[5\] " "Pin hex3\[5\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[5] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 39 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[6\] " "Pin hex3\[6\] not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[6] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 40 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "decimal_point " "Pin decimal_point not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { decimal_point } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 124 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { decimal_point } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 45 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "button2 " "Pin button2 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { button2 } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { button2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 44 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "button0 " "Pin button0 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { button0 } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { button0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 42 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "button1 " "Pin button1 not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { button1 } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { button1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 43 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Pin clk not assigned to an exact location on the device" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { clk } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 41 9662 10382 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1456932062894 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "28 " "TimeQuest Timing Analyzer is analyzing 28 combinational loops as latches." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Fitter" 0 -1 1456932063063 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "stopclock.sdc " "Synopsys Design Constraints File file not found: 'stopclock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1456932063063 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1456932063064 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1456932063066 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1456932063067 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1456932063067 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "button2~input (placed in PIN G2 (CLK0, DIFFCLK_0p)) " "Automatically promoted node button2~input (placed in PIN G2 (CLK0, DIFFCLK_0p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456932063092 ""}  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { button2~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 279 9662 10382 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456932063092 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN G1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk~input (placed in PIN G1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456932063092 ""}  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 282 9662 10382 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456932063092 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "hundred_hertz_clock:clockConv\|clock_out  " "Automatically promoted node hundred_hertz_clock:clockConv\|clock_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456932063092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "hundred_hertz_clock:clockConv\|clock_out~0 " "Destination node hundred_hertz_clock:clockConv\|clock_out~0" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 5 -1 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hundred_hertz_clock:clockConv|clock_out~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 211 9662 10382 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456932063092 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1456932063092 ""}  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 5 -1 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hundred_hertz_clock:clockConv|clock_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 104 9662 10382 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456932063092 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1456932063273 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456932063274 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456932063274 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456932063275 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456932063275 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1456932063275 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1456932063276 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1456932063276 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1456932063276 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1456932063276 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1456932063276 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "31 unused 2.5V 2 29 0 " "Number of I/O pins in group: 31 (unused VREF, 2.5V VCCIO, 2 input, 29 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1456932063279 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1456932063279 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1456932063279 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 6 27 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 6 total pin(s) used --  27 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1456932063280 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1456932063280 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932063305 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1456932064388 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932064479 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1456932064486 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1456932065575 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932065575 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1456932065803 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X21_Y20 X30_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29" {  } { { "loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29"} 21 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1456932066472 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1456932066472 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932067565 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1456932067565 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1456932067565 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.33 " "Total time spent on timing analysis during the Fitter is 0.33 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1456932067575 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456932067612 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456932067940 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456932067972 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456932068134 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932068561 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.fit.smsg " "Generated suppressed messages file C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1456932069645 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "846 " "Peak virtual memory: 846 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932069911 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:21:09 2016 " "Processing ended: Wed Mar 02 15:21:09 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932069911 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932069911 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932069911 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1456932069911 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1456932071867 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932071867 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:21:11 2016 " "Processing started: Wed Mar 02 15:21:11 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932071867 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1456932071867 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off stopclock -c stopclock " "Command: quartus_asm --read_settings_files=off --write_settings_files=off stopclock -c stopclock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1456932071868 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1456932072765 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1456932072797 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "465 " "Peak virtual memory: 465 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932073227 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:21:13 2016 " "Processing ended: Wed Mar 02 15:21:13 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932073227 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932073227 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932073227 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1456932073227 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1456932073848 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1456932075398 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932075399 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:21:14 2016 " "Processing started: Wed Mar 02 15:21:14 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932075399 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456932075399 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta stopclock -c stopclock " "Command: quartus_sta stopclock -c stopclock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456932075399 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1456932075595 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1456932075922 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456932075922 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456932076029 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456932076029 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "28 " "TimeQuest Timing Analyzer is analyzing 28 combinational loops as latches." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Quartus II" 0 -1 1456932076264 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "stopclock.sdc " "Synopsys Design Constraints File file not found: 'stopclock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1456932076356 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456932076359 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076361 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name hundred_hertz_clock:clockConv\|clock_out hundred_hertz_clock:clockConv\|clock_out " "create_clock -period 1.000 -name hundred_hertz_clock:clockConv\|clock_out hundred_hertz_clock:clockConv\|clock_out" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076361 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name button2 button2 " "create_clock -period 1.000 -name button2 button2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076361 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076361 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1456932076529 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076530 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1456932076531 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1456932076548 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456932076567 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456932076567 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.274 " "Worst-case setup slack is -2.274" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076576 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076576 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.274             -38.401 clk  " "   -2.274             -38.401 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076576 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.840             -24.288 hundred_hertz_clock:clockConv\|clock_out  " "   -1.840             -24.288 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076576 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.700             -41.655 button2  " "   -1.700             -41.655 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076576 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932076576 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.515 " "Worst-case hold slack is -0.515" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076581 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076581 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.515              -0.515 clk  " "   -0.515              -0.515 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076581 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.359               0.000 hundred_hertz_clock:clockConv\|clock_out  " "    0.359               0.000 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076581 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.753               0.000 button2  " "    0.753               0.000 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076581 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932076581 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932076591 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932076595 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -23.000 clk  " "   -3.000             -23.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000              -3.000 button2  " "   -3.000              -3.000 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000             -17.000 hundred_hertz_clock:clockConv\|clock_out  " "   -1.000             -17.000 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076599 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932076599 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456932076759 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1456932076782 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1456932077260 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077314 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456932077328 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456932077328 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.965 " "Worst-case setup slack is -1.965" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077333 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077333 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.965             -33.022 clk  " "   -1.965             -33.022 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077333 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.582             -20.441 hundred_hertz_clock:clockConv\|clock_out  " "   -1.582             -20.441 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077333 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.392             -33.987 button2  " "   -1.392             -33.987 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077333 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932077333 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.478 " "Worst-case hold slack is -0.478" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.478              -0.478 clk  " "   -0.478              -0.478 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.313               0.000 hundred_hertz_clock:clockConv\|clock_out  " "    0.313               0.000 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.665               0.000 button2  " "    0.665               0.000 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077343 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932077343 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932077350 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932077356 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077362 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077362 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -23.000 clk  " "   -3.000             -23.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077362 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000              -3.000 button2  " "   -3.000              -3.000 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077362 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000             -17.000 hundred_hertz_clock:clockConv\|clock_out  " "   -1.000             -17.000 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077362 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932077362 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456932077489 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077683 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456932077684 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456932077684 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.818 " "Worst-case setup slack is -0.818" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077700 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077700 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.818             -12.743 clk  " "   -0.818             -12.743 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077700 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.554              -6.490 hundred_hertz_clock:clockConv\|clock_out  " "   -0.554              -6.490 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077700 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.441              -8.576 button2  " "   -0.441              -8.576 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077700 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932077700 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.331 " "Worst-case hold slack is -0.331" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.331              -0.331 clk  " "   -0.331              -0.331 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.188               0.000 hundred_hertz_clock:clockConv\|clock_out  " "    0.188               0.000 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.311               0.000 button2  " "    0.311               0.000 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077722 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932077722 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932077742 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932077759 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077769 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077769 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -24.282 clk  " "   -3.000             -24.282 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077769 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000              -3.000 button2  " "   -3.000              -3.000 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077769 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000             -17.000 hundred_hertz_clock:clockConv\|clock_out  " "   -1.000             -17.000 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077769 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932077769 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456932078126 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456932078127 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "505 " "Peak virtual memory: 505 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932078265 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:21:18 2016 " "Processing ended: Wed Mar 02 15:21:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932078265 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932078265 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932078265 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456932078265 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456932080290 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932080290 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:21:20 2016 " "Processing started: Wed Mar 02 15:21:20 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932080290 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456932080290 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off stopclock -c stopclock " "Command: quartus_eda --read_settings_files=off --write_settings_files=off stopclock -c stopclock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456932080291 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_6_1200mv_85c_slow.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_6_1200mv_85c_slow.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932080888 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_6_1200mv_0c_slow.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_6_1200mv_0c_slow.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932080948 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_min_1200mv_0c_fast.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_min_1200mv_0c_fast.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932080991 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932081043 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_6_1200mv_85c_vhd_slow.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_6_1200mv_85c_vhd_slow.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932081079 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_6_1200mv_0c_vhd_slow.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_6_1200mv_0c_vhd_slow.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932081124 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_min_1200mv_0c_vhd_fast.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_min_1200mv_0c_vhd_fast.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932081166 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_vhd.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_vhd.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932081204 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "431 " "Peak virtual memory: 431 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932081278 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:21:21 2016 " "Processing ended: Wed Mar 02 15:21:21 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932081278 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932081278 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932081278 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456932081278 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 17 s " "Quartus II Full Compilation was successful. 0 errors, 17 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456932081898 ""}
diff --git a/stopClockVerilog/db/stopclock.(0).cnf.cdb b/stopClockVerilog/db/stopclock.(0).cnf.cdb
new file mode 100644
index 0000000..39ed4ca
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.(0).cnf.cdb
diff --git a/stopClockVerilog/db/stopclock.(0).cnf.hdb b/stopClockVerilog/db/stopclock.(0).cnf.hdb
new file mode 100644
index 0000000..d7d286d
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.(0).cnf.hdb
diff --git a/stopClockVerilog/db/stopclock.(1).cnf.cdb b/stopClockVerilog/db/stopclock.(1).cnf.cdb
new file mode 100644
index 0000000..9c32e99
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.(1).cnf.cdb
diff --git a/stopClockVerilog/db/stopclock.(1).cnf.hdb b/stopClockVerilog/db/stopclock.(1).cnf.hdb
new file mode 100644
index 0000000..0c5c873
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.(1).cnf.hdb
diff --git a/stopClockVerilog/db/stopclock.(2).cnf.cdb b/stopClockVerilog/db/stopclock.(2).cnf.cdb
new file mode 100644
index 0000000..7cd70e0
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.(2).cnf.cdb
diff --git a/stopClockVerilog/db/stopclock.(2).cnf.hdb b/stopClockVerilog/db/stopclock.(2).cnf.hdb
new file mode 100644
index 0000000..6831d9a
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.(2).cnf.hdb
diff --git a/stopClockVerilog/db/stopclock.(3).cnf.cdb b/stopClockVerilog/db/stopclock.(3).cnf.cdb
new file mode 100644
index 0000000..f050635
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.(3).cnf.cdb
diff --git a/stopClockVerilog/db/stopclock.(3).cnf.hdb b/stopClockVerilog/db/stopclock.(3).cnf.hdb
new file mode 100644
index 0000000..d957fde
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.(3).cnf.hdb
diff --git a/stopClockVerilog/db/stopclock.asm.qmsg b/stopClockVerilog/db/stopclock.asm.qmsg
new file mode 100644
index 0000000..4bbee9a
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456932282045 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932282046 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:24:41 2016 " "Processing started: Wed Mar 02 15:24:41 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932282046 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1456932282046 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off stopclock -c stopclock " "Command: quartus_asm --read_settings_files=off --write_settings_files=off stopclock -c stopclock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1456932282046 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1456932283008 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1456932283043 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "465 " "Peak virtual memory: 465 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932283420 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:24:43 2016 " "Processing ended: Wed Mar 02 15:24:43 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932283420 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932283420 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932283420 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1456932283420 ""}
diff --git a/stopClockVerilog/db/stopclock.asm.rdb b/stopClockVerilog/db/stopclock.asm.rdb
new file mode 100644
index 0000000..9071933
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.asm.rdb
diff --git a/stopClockVerilog/db/stopclock.asm_labs.ddb b/stopClockVerilog/db/stopclock.asm_labs.ddb
new file mode 100644
index 0000000..5f6c550
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.asm_labs.ddb
diff --git a/stopClockVerilog/db/stopclock.cbx.xml b/stopClockVerilog/db/stopclock.cbx.xml
new file mode 100644
index 0000000..7a8d93d
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="stopclock">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/stopClockVerilog/db/stopclock.cmp.bpm b/stopClockVerilog/db/stopclock.cmp.bpm
new file mode 100644
index 0000000..481f31c
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.cmp.bpm
diff --git a/stopClockVerilog/db/stopclock.cmp.cdb b/stopClockVerilog/db/stopclock.cmp.cdb
new file mode 100644
index 0000000..b42863f
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.cmp.cdb
diff --git a/stopClockVerilog/db/stopclock.cmp.hdb b/stopClockVerilog/db/stopclock.cmp.hdb
new file mode 100644
index 0000000..adacc83
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.cmp.hdb
diff --git a/stopClockVerilog/db/stopclock.cmp.idb b/stopClockVerilog/db/stopclock.cmp.idb
new file mode 100644
index 0000000..23d9e26
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.cmp.idb
diff --git a/stopClockVerilog/db/stopclock.cmp.logdb b/stopClockVerilog/db/stopclock.cmp.logdb
new file mode 100644
index 0000000..fa5c3bf
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.cmp.logdb
@@ -0,0 +1,75 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,33;0;33;0;0;33;33;0;33;33;0;29;0;0;4;0;29;4;0;0;0;29;0;0;0;0;0;33;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;33;0;33;33;0;0;33;0;0;33;4;33;33;29;33;4;29;33;33;33;4;33;33;33;33;33;0;33;33,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,hex0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,hex3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,decimal_point,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,button2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,button0,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,button1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,clk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/stopClockVerilog/db/stopclock.cmp.rdb b/stopClockVerilog/db/stopclock.cmp.rdb
new file mode 100644
index 0000000..9489091
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.cmp.rdb
diff --git a/stopClockVerilog/db/stopclock.cmp_merge.kpt b/stopClockVerilog/db/stopclock.cmp_merge.kpt
new file mode 100644
index 0000000..b030592
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.cmp_merge.kpt
diff --git a/stopClockVerilog/db/stopclock.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/stopClockVerilog/db/stopclock.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..999f11c
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/stopClockVerilog/db/stopclock.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/stopClockVerilog/db/stopclock.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..4436436
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/stopClockVerilog/db/stopclock.db_info b/stopClockVerilog/db/stopclock.db_info
new file mode 100644
index 0000000..54b2311
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Wed Mar 02 15:17:02 2016
diff --git a/stopClockVerilog/db/stopclock.eda.qmsg b/stopClockVerilog/db/stopclock.eda.qmsg
new file mode 100644
index 0000000..0dc2618
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.eda.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456932289743 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932289744 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:24:49 2016 " "Processing started: Wed Mar 02 15:24:49 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932289744 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456932289744 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off stopclock -c stopclock " "Command: quartus_eda --read_settings_files=off --write_settings_files=off stopclock -c stopclock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456932289744 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_6_1200mv_85c_slow.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_6_1200mv_85c_slow.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932290341 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_6_1200mv_0c_slow.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_6_1200mv_0c_slow.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932290392 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_min_1200mv_0c_fast.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_min_1200mv_0c_fast.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932290433 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932290474 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_6_1200mv_85c_vhd_slow.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_6_1200mv_85c_vhd_slow.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932290505 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_6_1200mv_0c_vhd_slow.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_6_1200mv_0c_vhd_slow.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932290544 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_min_1200mv_0c_vhd_fast.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_min_1200mv_0c_vhd_fast.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932290592 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_vhd.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_vhd.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932290632 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "431 " "Peak virtual memory: 431 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932290696 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:24:50 2016 " "Processing ended: Wed Mar 02 15:24:50 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932290696 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932290696 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932290696 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456932290696 ""}
diff --git a/stopClockVerilog/db/stopclock.fit.qmsg b/stopClockVerilog/db/stopclock.fit.qmsg
new file mode 100644
index 0000000..bf78d60
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.fit.qmsg
@@ -0,0 +1,46 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1456932272010 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "stopclock EP3C16U484C6 " "Selected device EP3C16U484C6 for design \"stopclock\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1456932272017 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456932272073 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456932272074 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456932272074 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1456932272168 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1456932272181 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40U484C6 " "Device EP3C40U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456932272490 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55U484C6 " "Device EP3C55U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456932272490 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80U484C6 " "Device EP3C80U484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456932272490 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1456932272490 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 287 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932272492 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 289 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932272492 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 291 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932272492 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 293 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932272492 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" {  } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 295 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932272492 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1456932272492 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1456932272494 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "28 " "TimeQuest Timing Analyzer is analyzing 28 combinational loops as latches." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Fitter" 0 -1 1456932273746 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "stopclock.sdc " "Synopsys Design Constraints File file not found: 'stopclock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1456932273747 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1456932273748 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1456932273750 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1456932273751 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1456932273751 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN G21 (CLK4, DIFFCLK_2p)) " "Automatically promoted node clk~input (placed in PIN G21 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456932273766 ""}  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 282 9662 10382 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456932273766 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "hundred_hertz_clock:clockConv\|clock_out  " "Automatically promoted node hundred_hertz_clock:clockConv\|clock_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456932273766 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "hundred_hertz_clock:clockConv\|clock_out~0 " "Destination node hundred_hertz_clock:clockConv\|clock_out~0" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 5 -1 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hundred_hertz_clock:clockConv|clock_out~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 211 9662 10382 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456932273766 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1456932273766 ""}  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 5 -1 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hundred_hertz_clock:clockConv|clock_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 104 9662 10382 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456932273766 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1456932274000 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456932274000 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456932274001 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456932274002 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456932274002 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1456932274003 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1456932274003 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1456932274003 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1456932274004 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1456932274004 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1456932274004 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932274040 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1456932275024 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932275124 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1456932275134 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1456932275699 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932275699 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1456932275893 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X21_Y20 X30_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29" {  } { { "loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29"} 21 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1456932276581 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1456932276581 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932277710 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1456932277710 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1456932277710 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.28 " "Total time spent on timing analysis during the Fitter is 0.28 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1456932277721 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456932277769 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456932278077 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456932278119 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456932278245 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932278658 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.fit.smsg " "Generated suppressed messages file C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1456932279777 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "839 " "Peak virtual memory: 839 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932280048 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:24:40 2016 " "Processing ended: Wed Mar 02 15:24:40 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932280048 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932280048 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932280048 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1456932280048 ""}
diff --git a/stopClockVerilog/db/stopclock.hier_info b/stopClockVerilog/db/stopclock.hier_info
new file mode 100644
index 0000000..fe9b926
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.hier_info
@@ -0,0 +1,183 @@
+|stopclock
+clk => clk.IN1
+button0 => button0.IN1
+button1 => button1.IN2
+button2 => button2.IN4
+hex0[0] << dec_to_seven_segment:dss0.out
+hex0[1] << dec_to_seven_segment:dss0.out
+hex0[2] << dec_to_seven_segment:dss0.out
+hex0[3] << dec_to_seven_segment:dss0.out
+hex0[4] << dec_to_seven_segment:dss0.out
+hex0[5] << dec_to_seven_segment:dss0.out
+hex0[6] << dec_to_seven_segment:dss0.out
+hex1[0] << dec_to_seven_segment:dss1.out
+hex1[1] << dec_to_seven_segment:dss1.out
+hex1[2] << dec_to_seven_segment:dss1.out
+hex1[3] << dec_to_seven_segment:dss1.out
+hex1[4] << dec_to_seven_segment:dss1.out
+hex1[5] << dec_to_seven_segment:dss1.out
+hex1[6] << dec_to_seven_segment:dss1.out
+hex2[0] << dec_to_seven_segment:dss2.out
+hex2[1] << dec_to_seven_segment:dss2.out
+hex2[2] << dec_to_seven_segment:dss2.out
+hex2[3] << dec_to_seven_segment:dss2.out
+hex2[4] << dec_to_seven_segment:dss2.out
+hex2[5] << dec_to_seven_segment:dss2.out
+hex2[6] << dec_to_seven_segment:dss2.out
+hex3[0] << dec_to_seven_segment:dss3.out
+hex3[1] << dec_to_seven_segment:dss3.out
+hex3[2] << dec_to_seven_segment:dss3.out
+hex3[3] << dec_to_seven_segment:dss3.out
+hex3[4] << dec_to_seven_segment:dss3.out
+hex3[5] << dec_to_seven_segment:dss3.out
+hex3[6] << dec_to_seven_segment:dss3.out
+decimal_point << <GND>
+
+
+|stopclock|hundred_hertz_clock:clockConv
+clock_in => clock_out~reg0.CLK
+clock_in => ctr[0].CLK
+clock_in => ctr[1].CLK
+clock_in => ctr[2].CLK
+clock_in => ctr[3].CLK
+clock_in => ctr[4].CLK
+clock_in => ctr[5].CLK
+clock_in => ctr[6].CLK
+clock_in => ctr[7].CLK
+clock_in => ctr[8].CLK
+clock_in => ctr[9].CLK
+clock_in => ctr[10].CLK
+clock_in => ctr[11].CLK
+clock_in => ctr[12].CLK
+clock_in => ctr[13].CLK
+clock_in => ctr[14].CLK
+clock_in => ctr[15].CLK
+clock_in => ctr[16].CLK
+clock_in => ctr[17].CLK
+clock_in => start.CLK
+b1 => start.OUTPUTSELECT
+clock_out <= clock_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopclock|counter:timeCount
+clock => c3[0]~reg0.CLK
+clock => c3[1]~reg0.CLK
+clock => c3[2]~reg0.CLK
+clock => c3[3]~reg0.CLK
+clock => c2[0]~reg0.CLK
+clock => c2[1]~reg0.CLK
+clock => c2[2]~reg0.CLK
+clock => c2[3]~reg0.CLK
+clock => c1[0]~reg0.CLK
+clock => c1[1]~reg0.CLK
+clock => c1[2]~reg0.CLK
+clock => c1[3]~reg0.CLK
+clock => c0[0]~reg0.CLK
+clock => c0[1]~reg0.CLK
+clock => c0[2]~reg0.CLK
+clock => c0[3]~reg0.CLK
+clock => en.CLK
+b0 => always0.IN1
+b1 => en.OUTPUTSELECT
+c0[0] <= c0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c0[1] <= c0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c0[2] <= c0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c0[3] <= c0[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c1[0] <= c1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c1[1] <= c1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c1[2] <= c1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c1[3] <= c1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c2[0] <= c2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c2[1] <= c2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c2[2] <= c2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c2[3] <= c2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c3[0] <= c3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c3[1] <= c3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c3[2] <= c3[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+c3[3] <= c3[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopclock|dec_to_seven_segment:dss0
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+b2 => out[1]$latch.LATCH_ENABLE
+b2 => out[0]$latch.LATCH_ENABLE
+b2 => out[2]$latch.LATCH_ENABLE
+b2 => out[3]$latch.LATCH_ENABLE
+b2 => out[4]$latch.LATCH_ENABLE
+b2 => out[5]$latch.LATCH_ENABLE
+b2 => out[6]$latch.LATCH_ENABLE
+out[0] <= out[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= out[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= out[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= out[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= out[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopclock|dec_to_seven_segment:dss1
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+b2 => out[1]$latch.LATCH_ENABLE
+b2 => out[0]$latch.LATCH_ENABLE
+b2 => out[2]$latch.LATCH_ENABLE
+b2 => out[3]$latch.LATCH_ENABLE
+b2 => out[4]$latch.LATCH_ENABLE
+b2 => out[5]$latch.LATCH_ENABLE
+b2 => out[6]$latch.LATCH_ENABLE
+out[0] <= out[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= out[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= out[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= out[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= out[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopclock|dec_to_seven_segment:dss2
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+b2 => out[1]$latch.LATCH_ENABLE
+b2 => out[0]$latch.LATCH_ENABLE
+b2 => out[2]$latch.LATCH_ENABLE
+b2 => out[3]$latch.LATCH_ENABLE
+b2 => out[4]$latch.LATCH_ENABLE
+b2 => out[5]$latch.LATCH_ENABLE
+b2 => out[6]$latch.LATCH_ENABLE
+out[0] <= out[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= out[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= out[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= out[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= out[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|stopclock|dec_to_seven_segment:dss3
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+b2 => out[1]$latch.LATCH_ENABLE
+b2 => out[0]$latch.LATCH_ENABLE
+b2 => out[2]$latch.LATCH_ENABLE
+b2 => out[3]$latch.LATCH_ENABLE
+b2 => out[4]$latch.LATCH_ENABLE
+b2 => out[5]$latch.LATCH_ENABLE
+b2 => out[6]$latch.LATCH_ENABLE
+out[0] <= out[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= out[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= out[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= out[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= out[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= out[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= out[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/stopClockVerilog/db/stopclock.hif b/stopClockVerilog/db/stopclock.hif
new file mode 100644
index 0000000..54e85f5
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.hif
diff --git a/stopClockVerilog/db/stopclock.ipinfo b/stopClockVerilog/db/stopclock.ipinfo
new file mode 100644
index 0000000..9d13c8b
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.ipinfo
diff --git a/stopClockVerilog/db/stopclock.lpc.html b/stopClockVerilog/db/stopclock.lpc.html
new file mode 100644
index 0000000..efe5ed4
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.lpc.html
@@ -0,0 +1,114 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >dss3</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >dss2</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >dss1</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >dss0</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >timeCount</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >clockConv</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/stopClockVerilog/db/stopclock.lpc.rdb b/stopClockVerilog/db/stopclock.lpc.rdb
new file mode 100644
index 0000000..70ded29
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.lpc.rdb
diff --git a/stopClockVerilog/db/stopclock.lpc.txt b/stopClockVerilog/db/stopclock.lpc.txt
new file mode 100644
index 0000000..d7e3e5f
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.lpc.txt
@@ -0,0 +1,12 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; dss3      ; 5     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; dss2      ; 5     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; dss1      ; 5     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; dss0      ; 5     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; timeCount ; 3     ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; clockConv ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/stopClockVerilog/db/stopclock.map.ammdb b/stopClockVerilog/db/stopclock.map.ammdb
new file mode 100644
index 0000000..e93ac1a
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.map.ammdb
diff --git a/stopClockVerilog/db/stopclock.map.bpm b/stopClockVerilog/db/stopclock.map.bpm
new file mode 100644
index 0000000..95668e4
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.map.bpm
diff --git a/stopClockVerilog/db/stopclock.map.cdb b/stopClockVerilog/db/stopclock.map.cdb
new file mode 100644
index 0000000..66bf703
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.map.cdb
diff --git a/stopClockVerilog/db/stopclock.map.hdb b/stopClockVerilog/db/stopclock.map.hdb
new file mode 100644
index 0000000..fd37d7d
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.map.hdb
diff --git a/stopClockVerilog/db/stopclock.map.kpt b/stopClockVerilog/db/stopclock.map.kpt
new file mode 100644
index 0000000..0381044
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.map.kpt
diff --git a/stopClockVerilog/db/stopclock.map.logdb b/stopClockVerilog/db/stopclock.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/stopClockVerilog/db/stopclock.map.qmsg b/stopClockVerilog/db/stopclock.map.qmsg
new file mode 100644
index 0000000..d8d49a1
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.map.qmsg
@@ -0,0 +1,27 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456932268043 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932268043 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:24:27 2016 " "Processing started: Wed Mar 02 15:24:27 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932268043 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456932268043 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off stopclock -c stopclock " "Command: quartus_map --read_settings_files=on --write_settings_files=off stopclock -c stopclock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456932268044 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1456932268477 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "stopclock.v(11) " "Verilog HDL information at stopclock.v(11): always construct contains both blocking and non-blocking assignments" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 11 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1456932268531 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "stopclock.v(40) " "Verilog HDL information at stopclock.v(40): always construct contains both blocking and non-blocking assignments" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 40 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1456932268531 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stopclock.v 4 4 " "Found 4 design units, including 4 entities, in source file stopclock.v" { { "Info" "ISGN_ENTITY_NAME" "1 hundred_hertz_clock " "Found entity 1: hundred_hertz_clock" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932268533 ""} { "Info" "ISGN_ENTITY_NAME" "2 counter " "Found entity 2: counter" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 31 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932268533 ""} { "Info" "ISGN_ENTITY_NAME" "3 dec_to_seven_segment " "Found entity 3: dec_to_seven_segment" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 80 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932268533 ""} { "Info" "ISGN_ENTITY_NAME" "4 stopclock " "Found entity 4: stopclock" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 122 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932268533 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456932268533 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "stopClock.bdf " "Can't analyze file -- file stopClock.bdf is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1456932268540 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stopclockblock.bdf 1 1 " "Found 1 design units, including 1 entities, in source file stopclockblock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 stopClockBlock " "Found entity 1: stopClockBlock" {  } { { "stopClockBlock.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopClockBlock.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932268542 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456932268542 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "stopclock " "Elaborating entity \"stopclock\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456932268570 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hundred_hertz_clock hundred_hertz_clock:clockConv " "Elaborating entity \"hundred_hertz_clock\" for hierarchy \"hundred_hertz_clock:clockConv\"" {  } { { "stopclock.v" "clockConv" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 133 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456932268573 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:timeCount " "Elaborating entity \"counter\" for hierarchy \"counter:timeCount\"" {  } { { "stopclock.v" "timeCount" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 134 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456932268575 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec_to_seven_segment dec_to_seven_segment:dss0 " "Elaborating entity \"dec_to_seven_segment\" for hierarchy \"dec_to_seven_segment:dss0\"" {  } { { "stopclock.v" "dss0" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 135 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456932268577 ""}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "out stopclock.v(87) " "Verilog HDL Always Construct warning at stopclock.v(87): inferring latch(es) for variable \"out\", which holds its previous value in one or more paths through the always construct" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 87 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1456932268578 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[0\] stopclock.v(89) " "Inferred latch for \"out\[0\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932268578 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[1\] stopclock.v(89) " "Inferred latch for \"out\[1\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932268578 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[2\] stopclock.v(89) " "Inferred latch for \"out\[2\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932268578 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[3\] stopclock.v(89) " "Inferred latch for \"out\[3\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932268578 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[4\] stopclock.v(89) " "Inferred latch for \"out\[4\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932268578 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[5\] stopclock.v(89) " "Inferred latch for \"out\[5\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932268578 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[6\] stopclock.v(89) " "Inferred latch for \"out\[6\]\" at stopclock.v(89)" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932268578 "|stopclock|dec_to_seven_segment:dss0"}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "decimal_point GND " "Pin \"decimal_point\" is stuck at GND" {  } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 124 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456932269197 "|stopclock|decimal_point"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1456932269197 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1456932269330 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.map.smsg " "Generated suppressed messages file C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1456932269529 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1456932269638 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456932269638 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "148 " "Implemented 148 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1456932269717 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1456932269717 ""} { "Info" "ICUT_CUT_TM_LCELLS" "115 " "Implemented 115 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1456932269717 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1456932269717 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "506 " "Peak virtual memory: 506 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932269738 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:24:29 2016 " "Processing ended: Wed Mar 02 15:24:29 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932269738 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932269738 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932269738 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456932269738 ""}
diff --git a/stopClockVerilog/db/stopclock.map.rdb b/stopClockVerilog/db/stopclock.map.rdb
new file mode 100644
index 0000000..c30005b
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.map.rdb
diff --git a/stopClockVerilog/db/stopclock.map_bb.cdb b/stopClockVerilog/db/stopclock.map_bb.cdb
new file mode 100644
index 0000000..de087ad
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.map_bb.cdb
diff --git a/stopClockVerilog/db/stopclock.map_bb.hdb b/stopClockVerilog/db/stopclock.map_bb.hdb
new file mode 100644
index 0000000..b799fe0
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.map_bb.hdb
diff --git a/stopClockVerilog/db/stopclock.map_bb.logdb b/stopClockVerilog/db/stopclock.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/stopClockVerilog/db/stopclock.pplq.rdb b/stopClockVerilog/db/stopclock.pplq.rdb
new file mode 100644
index 0000000..c0f6381
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.pplq.rdb
diff --git a/stopClockVerilog/db/stopclock.pre_map.hdb b/stopClockVerilog/db/stopclock.pre_map.hdb
new file mode 100644
index 0000000..2c35deb
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.pre_map.hdb
diff --git a/stopClockVerilog/db/stopclock.pti_db_list.ddb b/stopClockVerilog/db/stopclock.pti_db_list.ddb
new file mode 100644
index 0000000..e49c504
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.pti_db_list.ddb
diff --git a/stopClockVerilog/db/stopclock.root_partition.map.reg_db.cdb b/stopClockVerilog/db/stopclock.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..7c8f059
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.root_partition.map.reg_db.cdb
diff --git a/stopClockVerilog/db/stopclock.routing.rdb b/stopClockVerilog/db/stopclock.routing.rdb
new file mode 100644
index 0000000..ba51a78
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.routing.rdb
diff --git a/stopClockVerilog/db/stopclock.rtlv.hdb b/stopClockVerilog/db/stopclock.rtlv.hdb
new file mode 100644
index 0000000..6d18b3f
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.rtlv.hdb
diff --git a/stopClockVerilog/db/stopclock.rtlv_sg.cdb b/stopClockVerilog/db/stopclock.rtlv_sg.cdb
new file mode 100644
index 0000000..b3f275d
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.rtlv_sg.cdb
diff --git a/stopClockVerilog/db/stopclock.rtlv_sg_swap.cdb b/stopClockVerilog/db/stopclock.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..3bb7c47
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.rtlv_sg_swap.cdb
diff --git a/stopClockVerilog/db/stopclock.sgdiff.cdb b/stopClockVerilog/db/stopclock.sgdiff.cdb
new file mode 100644
index 0000000..ee18f13
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.sgdiff.cdb
diff --git a/stopClockVerilog/db/stopclock.sgdiff.hdb b/stopClockVerilog/db/stopclock.sgdiff.hdb
new file mode 100644
index 0000000..dc09d46
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.sgdiff.hdb
diff --git a/stopClockVerilog/db/stopclock.sld_design_entry.sci b/stopClockVerilog/db/stopclock.sld_design_entry.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.sld_design_entry.sci
diff --git a/stopClockVerilog/db/stopclock.sld_design_entry_dsc.sci b/stopClockVerilog/db/stopclock.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..19cbed8
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.sld_design_entry_dsc.sci
diff --git a/stopClockVerilog/db/stopclock.smart_action.txt b/stopClockVerilog/db/stopclock.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/stopClockVerilog/db/stopclock.sta.qmsg b/stopClockVerilog/db/stopclock.sta.qmsg
new file mode 100644
index 0000000..3a78039
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.sta.qmsg
@@ -0,0 +1,43 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456932285470 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932285471 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:24:45 2016 " "Processing started: Wed Mar 02 15:24:45 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932285471 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456932285471 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta stopclock -c stopclock " "Command: quartus_sta stopclock -c stopclock" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456932285471 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1456932285611 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1456932285874 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456932285874 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456932285942 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456932285942 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "28 " "TimeQuest Timing Analyzer is analyzing 28 combinational loops as latches." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Quartus II" 0 -1 1456932286104 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "stopclock.sdc " "Synopsys Design Constraints File file not found: 'stopclock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1456932286153 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456932286154 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286155 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name hundred_hertz_clock:clockConv\|clock_out hundred_hertz_clock:clockConv\|clock_out " "create_clock -period 1.000 -name hundred_hertz_clock:clockConv\|clock_out hundred_hertz_clock:clockConv\|clock_out" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286155 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name button2 button2 " "create_clock -period 1.000 -name button2 button2" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286155 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286155 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1456932286304 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286305 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1456932286307 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1456932286317 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456932286332 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456932286332 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.274 " "Worst-case setup slack is -2.274" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286336 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286336 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.274             -38.401 clk  " "   -2.274             -38.401 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286336 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.787             -25.453 hundred_hertz_clock:clockConv\|clock_out  " "   -1.787             -25.453 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286336 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.727             -34.724 button2  " "   -1.727             -34.724 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286336 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932286336 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.504 " "Worst-case hold slack is -0.504" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286341 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286341 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.504              -0.504 clk  " "   -0.504              -0.504 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286341 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.359               0.000 hundred_hertz_clock:clockConv\|clock_out  " "    0.359               0.000 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286341 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.615               0.000 button2  " "    0.615               0.000 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286341 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932286341 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932286345 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932286349 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -23.000 clk  " "   -3.000             -23.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000              -3.000 button2  " "   -3.000              -3.000 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000             -17.000 hundred_hertz_clock:clockConv\|clock_out  " "   -1.000             -17.000 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286353 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932286353 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456932286452 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1456932286476 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1456932286914 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286962 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456932286974 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456932286974 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.965 " "Worst-case setup slack is -1.965" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.965             -33.034 clk  " "   -1.965             -33.034 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.522             -21.435 hundred_hertz_clock:clockConv\|clock_out  " "   -1.522             -21.435 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.393             -27.476 button2  " "   -1.393             -27.476 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286985 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932286985 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.471 " "Worst-case hold slack is -0.471" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286993 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286993 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.471              -0.471 clk  " "   -0.471              -0.471 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286993 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.312               0.000 hundred_hertz_clock:clockConv\|clock_out  " "    0.312               0.000 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286993 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.519               0.000 button2  " "    0.519               0.000 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932286993 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932286993 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932287000 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932287009 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -23.000 clk  " "   -3.000             -23.000 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000              -3.000 button2  " "   -3.000              -3.000 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000             -17.000 hundred_hertz_clock:clockConv\|clock_out  " "   -1.000             -17.000 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287016 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932287016 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456932287144 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287244 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456932287245 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456932287245 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.818 " "Worst-case setup slack is -0.818" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.818             -12.731 clk  " "   -0.818             -12.731 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.550              -6.614 hundred_hertz_clock:clockConv\|clock_out  " "   -0.550              -6.614 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287253 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.418              -4.063 button2  " "   -0.418              -4.063 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287253 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932287253 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.319 " "Worst-case hold slack is -0.319" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287262 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287262 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.319              -0.319 clk  " "   -0.319              -0.319 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287262 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.185               0.000 button2  " "    0.185               0.000 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287262 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.188               0.000 hundred_hertz_clock:clockConv\|clock_out  " "    0.188               0.000 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287262 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932287262 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932287270 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932287280 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287291 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287291 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -24.262 clk  " "   -3.000             -24.262 clk " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287291 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000              -3.414 button2  " "   -3.000              -3.414 button2 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287291 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.000             -17.000 hundred_hertz_clock:clockConv\|clock_out  " "   -1.000             -17.000 hundred_hertz_clock:clockConv\|clock_out " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932287291 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932287291 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456932287628 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456932287628 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "502 " "Peak virtual memory: 502 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932287763 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:24:47 2016 " "Processing ended: Wed Mar 02 15:24:47 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932287763 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932287763 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932287763 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456932287763 ""}
diff --git a/stopClockVerilog/db/stopclock.sta.rdb b/stopClockVerilog/db/stopclock.sta.rdb
new file mode 100644
index 0000000..757d604
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.sta.rdb
diff --git a/stopClockVerilog/db/stopclock.sta_cmp.6_slow_1200mv_85c.tdb b/stopClockVerilog/db/stopclock.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..66bd659
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/stopClockVerilog/db/stopclock.tis_db_list.ddb b/stopClockVerilog/db/stopclock.tis_db_list.ddb
new file mode 100644
index 0000000..87a3929
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.tis_db_list.ddb
diff --git a/stopClockVerilog/db/stopclock.tiscmp.fast_1200mv_0c.ddb b/stopClockVerilog/db/stopclock.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..ddcf386
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.tiscmp.fast_1200mv_0c.ddb
diff --git a/stopClockVerilog/db/stopclock.tiscmp.slow_1200mv_0c.ddb b/stopClockVerilog/db/stopclock.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..b646ef2
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.tiscmp.slow_1200mv_0c.ddb
diff --git a/stopClockVerilog/db/stopclock.tiscmp.slow_1200mv_85c.ddb b/stopClockVerilog/db/stopclock.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..91f2bb3
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.tiscmp.slow_1200mv_85c.ddb
diff --git a/stopClockVerilog/db/stopclock.tmw_info b/stopClockVerilog/db/stopclock.tmw_info
new file mode 100644
index 0000000..0be86e1
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:00:25
+start_analysis_synthesis:s:00:00:04-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:10-start_full_compilation
+start_assembler:s:00:00:03-start_full_compilation
+start_timing_analyzer:s:00:00:05-start_full_compilation
+start_eda_netlist_writer:s:00:00:03-start_full_compilation
diff --git a/stopClockVerilog/db/stopclock.vpr.ammdb b/stopClockVerilog/db/stopclock.vpr.ammdb
new file mode 100644
index 0000000..70ba0bb
--- /dev/null
+++ b/stopClockVerilog/db/stopclock.vpr.ammdb
diff --git a/stopClockVerilog/dec_to_seven_segment.bsf b/stopClockVerilog/dec_to_seven_segment.bsf
new file mode 100644
index 0000000..9a60106
--- /dev/null
+++ b/stopClockVerilog/dec_to_seven_segment.bsf
@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 176 96)
+	(text "dec_to_seven_segment" (rect 5 0 102 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "in[3..0]" (rect 0 0 25 12)(font "Arial" ))
+		(text "in[3..0]" (rect 21 27 46 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "b2" (rect 0 0 9 12)(font "Arial" ))
+		(text "b2" (rect 21 43 30 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "out[6..0]" (rect 0 0 31 12)(font "Arial" ))
+		(text "out[6..0]" (rect 108 27 139 39)(font "Arial" ))
+		(line (pt 160 32)(pt 144 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 144 64)(line_width 1))
+	)
+)
diff --git a/stopClockVerilog/hundred_hertz_clock.bsf b/stopClockVerilog/hundred_hertz_clock.bsf
new file mode 100644
index 0000000..cd2b30b
--- /dev/null
+++ b/stopClockVerilog/hundred_hertz_clock.bsf
@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 184 96)
+	(text "hundred_hertz_clock" (rect 5 0 87 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock_in" (rect 0 0 31 12)(font "Arial" ))
+		(text "clock_in" (rect 21 27 52 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "b1" (rect 0 0 8 12)(font "Arial" ))
+		(text "b1" (rect 21 43 29 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 168 32)
+		(output)
+		(text "clock_out" (rect 0 0 37 12)(font "Arial" ))
+		(text "clock_out" (rect 110 27 147 39)(font "Arial" ))
+		(line (pt 168 32)(pt 152 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 152 64)(line_width 1))
+	)
+)
diff --git a/stopClockVerilog/incremental_db/README b/stopClockVerilog/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/stopClockVerilog/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.db_info b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.db_info
new file mode 100644
index 0000000..9e19058
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Wed Mar 02 15:17:17 2016
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.ammdb b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.ammdb
new file mode 100644
index 0000000..408fa78
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.ammdb
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.cdb b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.cdb
new file mode 100644
index 0000000..5a7dc56
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.cdb
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.dfp b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.dfp
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.hdb b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.hdb
new file mode 100644
index 0000000..c4ae25b
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.hdb
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.logdb b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.rcfdb b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..678f03f
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.cmp.rcfdb
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.cdb b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.cdb
new file mode 100644
index 0000000..addef2f
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.cdb
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.dpi b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.dpi
new file mode 100644
index 0000000..ba23401
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.dpi
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hbdb.cdb b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..4171437
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hbdb.cdb
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hbdb.hb_info b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hbdb.hb_info
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hbdb.hdb b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..307be1d
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hbdb.hdb
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hbdb.sig b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hdb b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hdb
new file mode 100644
index 0000000..e67560d
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.hdb
diff --git a/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.kpt b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.kpt
new file mode 100644
index 0000000..f6552d0
--- /dev/null
+++ b/stopClockVerilog/incremental_db/compiled_partitions/stopclock.root_partition.map.kpt
diff --git a/stopClockVerilog/output_files/stopclock.asm.rpt b/stopClockVerilog/output_files/stopclock.asm.rpt
new file mode 100644
index 0000000..351d6ee
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for stopclock
+Wed Mar 02 15:24:43 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Wed Mar 02 15:24:43 2016 ;
+; Revision Name         ; stopclock                             ;
+; Top-level Entity Name ; stopclock                             ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16U484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Assembler Generated Files                                                                                      ;
++----------------------------------------------------------------------------------------------------------------+
+; File Name                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------+
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.sof ;
++----------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.sof ;
++----------------+-------------------------------------------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                                                                 ;
++----------------+-------------------------------------------------------------------------------------------------------------------------+
+; Device         ; EP3C16U484C6                                                                                                            ;
+; JTAG usercode  ; 0x000D9A1B                                                                                                              ;
+; Checksum       ; 0x000D9A1B                                                                                                              ;
++----------------+-------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Wed Mar 02 15:24:41 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off stopclock -c stopclock
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 465 megabytes
+    Info: Processing ended: Wed Mar 02 15:24:43 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/stopClockVerilog/output_files/stopclock.cdf b/stopClockVerilog/output_files/stopclock.cdf
new file mode 100644
index 0000000..681ecd2
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.cdf
@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP3C16U484) Path("C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/") File("stopclock.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/stopClockVerilog/output_files/stopclock.done b/stopClockVerilog/output_files/stopclock.done
new file mode 100644
index 0000000..4f8bbc0
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.done
@@ -0,0 +1 @@
+Wed Mar 02 15:24:51 2016
diff --git a/stopClockVerilog/output_files/stopclock.eda.rpt b/stopClockVerilog/output_files/stopclock.eda.rpt
new file mode 100644
index 0000000..5cbcfc2
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.eda.rpt
@@ -0,0 +1,107 @@
+EDA Netlist Writer report for stopclock
+Wed Mar 02 15:24:50 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Wed Mar 02 15:24:50 2016 ;
+; Revision Name             ; stopclock                             ;
+; Top-level Entity Name     ; stopclock                             ;
+; Family                    ; Cyclone III                           ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                        ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Option                                                                                            ; Setting                ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (VHDL) ;
+; Generate netlist for functional simulation only                                                   ; Off                    ;
+; Time scale                                                                                        ; 1 ps                   ;
+; Truncate long hierarchy paths                                                                     ; Off                    ;
+; Map illegal HDL characters                                                                        ; Off                    ;
+; Flatten buses into individual nodes                                                               ; Off                    ;
+; Maintain hierarchy                                                                                ; Off                    ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                    ;
+; Enable glitch filtering                                                                           ; Off                    ;
+; Do not write top level VHDL entity                                                                ; Off                    ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                    ;
+; Architecture name in VHDL output netlist                                                          ; structure              ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                    ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                    ;
++---------------------------------------------------------------------------------------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Generated Files                                                                                                                   ;
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; Generated Files                                                                                                                              ;
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/stopclock_6_1200mv_85c_slow.vho      ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/stopclock_6_1200mv_0c_slow.vho       ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/stopclock_min_1200mv_0c_fast.vho     ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/stopclock.vho                        ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/stopclock_6_1200mv_85c_vhd_slow.sdo  ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/stopclock_6_1200mv_0c_vhd_slow.sdo   ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/stopclock_min_1200mv_0c_vhd_fast.sdo ;
+; C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/stopclock_vhd.sdo                    ;
++----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit EDA Netlist Writer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Wed Mar 02 15:24:49 2016
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off stopclock -c stopclock
+Info (204019): Generated file stopclock_6_1200mv_85c_slow.vho in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file stopclock_6_1200mv_0c_slow.vho in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file stopclock_min_1200mv_0c_fast.vho in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file stopclock.vho in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file stopclock_6_1200mv_85c_vhd_slow.sdo in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file stopclock_6_1200mv_0c_vhd_slow.sdo in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file stopclock_min_1200mv_0c_vhd_fast.sdo in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file stopclock_vhd.sdo in folder "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 431 megabytes
+    Info: Processing ended: Wed Mar 02 15:24:50 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/stopClockVerilog/output_files/stopclock.fit.rpt b/stopClockVerilog/output_files/stopclock.fit.rpt
new file mode 100644
index 0000000..e6e2692
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.fit.rpt
@@ -0,0 +1,1645 @@
+Fitter report for stopclock
+Wed Mar 02 15:24:39 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Incremental Compilation Preservation Summary
+  7. Incremental Compilation Partition Settings
+  8. Incremental Compilation Placement Preservation
+  9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Control Signals
+ 21. Global & Other Fast Signals
+ 22. Non-Global High Fan-Out Signals
+ 23. Routing Usage Summary
+ 24. LAB Logic Elements
+ 25. LAB-wide Signals
+ 26. LAB Signals Sourced
+ 27. LAB Signals Sourced Out
+ 28. LAB Distinct Inputs
+ 29. I/O Rules Summary
+ 30. I/O Rules Details
+ 31. I/O Rules Matrix
+ 32. Fitter Device Options
+ 33. Operating Settings and Conditions
+ 34. Estimated Delay Added for Hold Timing Summary
+ 35. Estimated Delay Added for Hold Timing Details
+ 36. Fitter Messages
+ 37. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Fitter Summary                                                                  ;
++------------------------------------+--------------------------------------------+
+; Fitter Status                      ; Successful - Wed Mar 02 15:24:39 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; stopclock                                  ;
+; Top-level Entity Name              ; stopclock                                  ;
+; Family                             ; Cyclone III                                ;
+; Device                             ; EP3C16U484C6                               ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 114 / 15,408 ( < 1 % )                     ;
+;     Total combinational functions  ; 113 / 15,408 ( < 1 % )                     ;
+;     Dedicated logic registers      ; 37 / 15,408 ( < 1 % )                      ;
+; Total registers                    ; 37                                         ;
+; Total pins                         ; 33 / 347 ( 10 % )                          ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16U484C6                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++------------------------------------------------------+
+; I/O Assignment Warnings                              ;
++---------------+--------------------------------------+
+; Pin Name      ; Reason                               ;
++---------------+--------------------------------------+
+; hex0[0]       ; Missing drive strength and slew rate ;
+; hex0[1]       ; Missing drive strength and slew rate ;
+; hex0[2]       ; Missing drive strength and slew rate ;
+; hex0[3]       ; Missing drive strength and slew rate ;
+; hex0[4]       ; Missing drive strength and slew rate ;
+; hex0[5]       ; Missing drive strength and slew rate ;
+; hex0[6]       ; Missing drive strength and slew rate ;
+; hex1[0]       ; Missing drive strength and slew rate ;
+; hex1[1]       ; Missing drive strength and slew rate ;
+; hex1[2]       ; Missing drive strength and slew rate ;
+; hex1[3]       ; Missing drive strength and slew rate ;
+; hex1[4]       ; Missing drive strength and slew rate ;
+; hex1[5]       ; Missing drive strength and slew rate ;
+; hex1[6]       ; Missing drive strength and slew rate ;
+; hex2[0]       ; Missing drive strength and slew rate ;
+; hex2[1]       ; Missing drive strength and slew rate ;
+; hex2[2]       ; Missing drive strength and slew rate ;
+; hex2[3]       ; Missing drive strength and slew rate ;
+; hex2[4]       ; Missing drive strength and slew rate ;
+; hex2[5]       ; Missing drive strength and slew rate ;
+; hex2[6]       ; Missing drive strength and slew rate ;
+; hex3[0]       ; Missing drive strength and slew rate ;
+; hex3[1]       ; Missing drive strength and slew rate ;
+; hex3[2]       ; Missing drive strength and slew rate ;
+; hex3[3]       ; Missing drive strength and slew rate ;
+; hex3[4]       ; Missing drive strength and slew rate ;
+; hex3[5]       ; Missing drive strength and slew rate ;
+; hex3[6]       ; Missing drive strength and slew rate ;
+; decimal_point ; Missing drive strength and slew rate ;
++---------------+--------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 229 ) ; 0.00 % ( 0 / 229 )         ; 0.00 % ( 0 / 229 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 229 ) ; 0.00 % ( 0 / 229 )         ; 0.00 % ( 0 / 229 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 219 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.pin.
+
+
++----------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                        ;
++---------------------------------------------+------------------------+
+; Resource                                    ; Usage                  ;
++---------------------------------------------+------------------------+
+; Total logic elements                        ; 114 / 15,408 ( < 1 % ) ;
+;     -- Combinational with no register       ; 77                     ;
+;     -- Register only                        ; 1                      ;
+;     -- Combinational with a register        ; 36                     ;
+;                                             ;                        ;
+; Logic element usage by number of LUT inputs ;                        ;
+;     -- 4 input functions                    ; 49                     ;
+;     -- 3 input functions                    ; 44                     ;
+;     -- <=2 input functions                  ; 20                     ;
+;     -- Register only                        ; 1                      ;
+;                                             ;                        ;
+; Logic elements by mode                      ;                        ;
+;     -- normal mode                          ; 96                     ;
+;     -- arithmetic mode                      ; 17                     ;
+;                                             ;                        ;
+; Total registers*                            ; 37 / 17,068 ( < 1 % )  ;
+;     -- Dedicated logic registers            ; 37 / 15,408 ( < 1 % )  ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )      ;
+;                                             ;                        ;
+; Total LABs:  partially or completely used   ; 10 / 963 ( 1 % )       ;
+; Virtual pins                                ; 0                      ;
+; I/O pins                                    ; 33 / 347 ( 10 % )      ;
+;     -- Clock pins                           ; 1 / 8 ( 13 % )         ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )          ;
+;                                             ;                        ;
+; Global signals                              ; 2                      ;
+; M9Ks                                        ; 0 / 56 ( 0 % )         ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % )    ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )    ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )        ;
+; PLLs                                        ; 0 / 4 ( 0 % )          ;
+; Global clocks                               ; 2 / 20 ( 10 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )          ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )          ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )          ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )          ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%           ;
+; Peak interconnect usage (total/H/V)         ; 0% / 1% / 0%           ;
+; Maximum fan-out                             ; 28                     ;
+; Highest non-global fan-out                  ; 28                     ;
+; Total fan-out                               ; 558                    ;
+; Average fan-out                             ; 2.44                   ;
++---------------------------------------------+------------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                          ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                   ; Top                   ; hard_block:auto_generated_inst ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                   ; Low                            ;
+;                                             ;                       ;                                ;
+; Total logic elements                        ; 114 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 77                    ; 0                              ;
+;     -- Register only                        ; 1                     ; 0                              ;
+;     -- Combinational with a register        ; 36                    ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic element usage by number of LUT inputs ;                       ;                                ;
+;     -- 4 input functions                    ; 49                    ; 0                              ;
+;     -- 3 input functions                    ; 44                    ; 0                              ;
+;     -- <=2 input functions                  ; 20                    ; 0                              ;
+;     -- Register only                        ; 1                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic elements by mode                      ;                       ;                                ;
+;     -- normal mode                          ; 96                    ; 0                              ;
+;     -- arithmetic mode                      ; 17                    ; 0                              ;
+;                                             ;                       ;                                ;
+; Total registers                             ; 37                    ; 0                              ;
+;     -- Dedicated logic registers            ; 37 / 15408 ( < 1 % )  ; 0 / 15408 ( 0 % )              ;
+;     -- I/O registers                        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Total LABs:  partially or completely used   ; 10 / 963 ( 1 % )      ; 0 / 963 ( 0 % )                ;
+;                                             ;                       ;                                ;
+; Virtual pins                                ; 0                     ; 0                              ;
+; I/O pins                                    ; 33                    ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                     ; 0                              ;
+; Total RAM block bits                        ; 0                     ; 0                              ;
+; Clock control block                         ; 2 / 24 ( 8 % )        ; 0 / 24 ( 0 % )                 ;
+;                                             ;                       ;                                ;
+; Connections                                 ;                       ;                                ;
+;     -- Input Connections                    ; 0                     ; 0                              ;
+;     -- Registered Input Connections         ; 0                     ; 0                              ;
+;     -- Output Connections                   ; 0                     ; 0                              ;
+;     -- Registered Output Connections        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Internal Connections                        ;                       ;                                ;
+;     -- Total Connections                    ; 553                   ; 5                              ;
+;     -- Registered Connections               ; 208                   ; 0                              ;
+;                                             ;                       ;                                ;
+; External Connections                        ;                       ;                                ;
+;     -- Top                                  ; 0                     ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Partition Interface                         ;                       ;                                ;
+;     -- Input Ports                          ; 4                     ; 0                              ;
+;     -- Output Ports                         ; 29                    ; 0                              ;
+;     -- Bidir Ports                          ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Registered Ports                            ;                       ;                                ;
+;     -- Registered Input Ports               ; 0                     ; 0                              ;
+;     -- Registered Output Ports              ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Port Connectivity                           ;                       ;                                ;
+;     -- Input Ports driven by GND            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                     ; 0                              ;
++---------------------------------------------+-----------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; button0 ; H2    ; 1        ; 0            ; 21           ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; button1 ; G3    ; 1        ; 0            ; 23           ; 14           ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; button2 ; F1    ; 1        ; 0            ; 23           ; 0            ; 28                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
+; clk     ; G21   ; 6        ; 41           ; 15           ; 0            ; 20                    ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ;
++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name          ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; decimal_point ; A18   ; 7        ; 32           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex0[0]       ; E11   ; 7        ; 21           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex0[1]       ; F11   ; 7        ; 21           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex0[2]       ; H12   ; 7        ; 26           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex0[3]       ; H13   ; 7        ; 28           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex0[4]       ; G12   ; 7        ; 26           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex0[5]       ; F12   ; 7        ; 28           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex0[6]       ; F13   ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex1[0]       ; A13   ; 7        ; 21           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex1[1]       ; B13   ; 7        ; 21           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex1[2]       ; C13   ; 7        ; 23           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex1[3]       ; A14   ; 7        ; 23           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex1[4]       ; B14   ; 7        ; 23           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex1[5]       ; E14   ; 7        ; 28           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex1[6]       ; A15   ; 7        ; 26           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex2[0]       ; D15   ; 7        ; 32           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex2[1]       ; A16   ; 7        ; 30           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex2[2]       ; B16   ; 7        ; 28           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex2[3]       ; E15   ; 7        ; 30           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex2[4]       ; A17   ; 7        ; 30           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex2[5]       ; B17   ; 7        ; 30           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex2[6]       ; F14   ; 7        ; 37           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex3[0]       ; B18   ; 7        ; 32           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex3[1]       ; F15   ; 7        ; 39           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex3[2]       ; A19   ; 7        ; 32           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex3[3]       ; B19   ; 7        ; 32           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex3[4]       ; C19   ; 7        ; 37           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex3[5]       ; D19   ; 7        ; 37           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; hex3[6]       ; G15   ; 7        ; 39           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                    ;
++----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                               ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
+; D1       ; DIFFIO_L4n, DATA1, ASDO                ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO            ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                                ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                                   ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                                  ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                                ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                              ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; K22      ; DIFFIO_R16n, nCEO                      ; Use as programming pin   ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
+; B18      ; DIFFIO_T27p, PADD0                     ; Use as regular IO        ; hex3[0]                 ; Dual Purpose Pin          ;
+; A17      ; DIFFIO_T25n, PADD1                     ; Use as regular IO        ; hex2[4]                 ; Dual Purpose Pin          ;
+; B17      ; DIFFIO_T25p, PADD2                     ; Use as regular IO        ; hex2[5]                 ; Dual Purpose Pin          ;
+; E14      ; DIFFIO_T23n, PADD3                     ; Use as regular IO        ; hex1[5]                 ; Dual Purpose Pin          ;
+; F13      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8  ; Use as regular IO        ; hex0[6]                 ; Dual Purpose Pin          ;
+; A15      ; DIFFIO_T20n, PADD5                     ; Use as regular IO        ; hex1[6]                 ; Dual Purpose Pin          ;
+; C13      ; DIFFIO_T19n, PADD7                     ; Use as regular IO        ; hex1[2]                 ; Dual Purpose Pin          ;
+; A14      ; DIFFIO_T18n, PADD9                     ; Use as regular IO        ; hex1[3]                 ; Dual Purpose Pin          ;
+; B14      ; DIFFIO_T18p, PADD10                    ; Use as regular IO        ; hex1[4]                 ; Dual Purpose Pin          ;
+; A13      ; DIFFIO_T17n, PADD11                    ; Use as regular IO        ; hex1[0]                 ; Dual Purpose Pin          ;
+; B13      ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO        ; hex1[1]                 ; Dual Purpose Pin          ;
+; E11      ; DIFFIO_T16n, PADD13                    ; Use as regular IO        ; hex0[0]                 ; Dual Purpose Pin          ;
+; F11      ; DIFFIO_T16p, PADD14                    ; Use as regular IO        ; hex0[1]                 ; Dual Purpose Pin          ;
++----------+----------------------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 7 / 33 ( 21 % )  ; 2.5V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
+; 3        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
+; 5        ; 0 / 46 ( 0 % )   ; 2.5V          ; --           ;
+; 6        ; 2 / 43 ( 5 % )   ; 2.5V          ; --           ;
+; 7        ; 29 / 47 ( 62 % ) ; 2.5V          ; --           ;
+; 8        ; 0 / 43 ( 0 % )   ; 2.5V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; hex1[0]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A14      ; 312        ; 7        ; hex1[3]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A15      ; 307        ; 7        ; hex1[6]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A16      ; 298        ; 7        ; hex2[1]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A17      ; 296        ; 7        ; hex2[4]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A18      ; 291        ; 7        ; decimal_point                                             ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A19      ; 290        ; 7        ; hex3[2]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B2       ; 1          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; hex1[1]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B14      ; 313        ; 7        ; hex1[4]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; hex2[2]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B17      ; 297        ; 7        ; hex2[5]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B18      ; 292        ; 7        ; hex3[0]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B19      ; 289        ; 7        ; hex3[3]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C2       ; 6          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; hex1[2]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; hex3[4]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; hex2[0]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; hex3[5]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E4       ; 4          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E11      ; 317        ; 7        ; hex0[0]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; hex1[5]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E15      ; 294        ; 7        ; hex2[3]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; button2                                                   ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F11      ; 318        ; 7        ; hex0[1]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F12      ; 302        ; 7        ; hex0[5]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F13      ; 306        ; 7        ; hex0[6]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F14      ; 279        ; 7        ; hex2[6]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F15      ; 276        ; 7        ; hex3[1]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; button1                                                   ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G4       ; 17         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G5       ; 3          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; hex0[4]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; hex3[6]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; clk                                                       ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H2       ; 25         ; 1        ; button0                                                   ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H6       ; 11         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H7       ; 10         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; hex0[2]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H13      ; 303        ; 7        ; hex0[3]                                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H20      ; 253        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H21      ; 246        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H22      ; 245        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J1       ; 29         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J2       ; 28         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J3       ; 27         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J7       ; 22         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J22      ; 241        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K18      ; 248        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K22      ; 239        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN                ; output ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L22      ; 234        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                        ;
++------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------+--------------+
+; Compilation Hierarchy Node         ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                      ; Library Name ;
++------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------+--------------+
+; |stopclock                         ; 114 (0)     ; 37 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 33   ; 0            ; 77 (0)       ; 1 (0)             ; 36 (0)           ; |stopclock                               ; work         ;
+;    |counter:timeCount|             ; 32 (32)     ; 17 (17)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 0 (0)             ; 17 (17)          ; |stopclock|counter:timeCount             ; work         ;
+;    |dec_to_seven_segment:dss0|     ; 14 (14)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 14 (14)      ; 0 (0)             ; 0 (0)            ; |stopclock|dec_to_seven_segment:dss0     ; work         ;
+;    |dec_to_seven_segment:dss1|     ; 14 (14)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 14 (14)      ; 0 (0)             ; 0 (0)            ; |stopclock|dec_to_seven_segment:dss1     ; work         ;
+;    |dec_to_seven_segment:dss2|     ; 14 (14)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 14 (14)      ; 0 (0)             ; 0 (0)            ; |stopclock|dec_to_seven_segment:dss2     ; work         ;
+;    |dec_to_seven_segment:dss3|     ; 14 (14)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (13)      ; 0 (0)             ; 1 (1)            ; |stopclock|dec_to_seven_segment:dss3     ; work         ;
+;    |hundred_hertz_clock:clockConv| ; 27 (27)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 1 (1)             ; 19 (19)          ; |stopclock|hundred_hertz_clock:clockConv ; work         ;
++------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-----------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                           ;
++---------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name          ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++---------------+----------+---------------+---------------+-----------------------+-----+------+
+; hex0[0]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex0[1]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex0[2]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex0[3]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex0[4]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex0[5]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex0[6]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex1[0]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex1[1]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex1[2]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex1[3]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex1[4]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex1[5]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex1[6]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex2[0]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex2[1]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex2[2]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex2[3]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex2[4]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex2[5]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex2[6]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex3[0]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex3[1]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex3[2]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex3[3]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex3[4]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex3[5]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; hex3[6]       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; decimal_point ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; button2       ; Input    ; --            ; (0) 0 ps      ; --                    ; --  ; --   ;
+; button0       ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; button1       ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; clk           ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
++---------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++--------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                 ;
++--------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                              ; Pad To Core Index ; Setting ;
++--------------------------------------------------+-------------------+---------+
+; button2                                          ;                   ;         ;
+;      - dec_to_seven_segment:dss0|out[0]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss0|out[1]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss0|out[2]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss0|out[3]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss0|out[4]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss0|out[5]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss0|out[6]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss1|out[0]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss1|out[1]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss1|out[2]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss1|out[3]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss1|out[4]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss1|out[5]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss1|out[6]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss2|out[0]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss2|out[1]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss2|out[2]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss2|out[3]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss2|out[4]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss2|out[5]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss2|out[6]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss3|out[0]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss3|out[1]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss3|out[2]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss3|out[3]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss3|out[4]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss3|out[5]          ; 1                 ; 0       ;
+;      - dec_to_seven_segment:dss3|out[6]          ; 1                 ; 0       ;
+; button0                                          ;                   ;         ;
+;      - counter:timeCount|always0~0               ; 0                 ; 6       ;
+;      - counter:timeCount|c0[3]~3                 ; 0                 ; 6       ;
+; button1                                          ;                   ;         ;
+;      - counter:timeCount|always0~0               ; 0                 ; 6       ;
+;      - counter:timeCount|c0[3]~3                 ; 0                 ; 6       ;
+;      - hundred_hertz_clock:clockConv|clock_out~0 ; 0                 ; 6       ;
+;      - hundred_hertz_clock:clockConv|start~0     ; 0                 ; 6       ;
+; clk                                              ;                   ;         ;
++--------------------------------------------------+-------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                        ;
++-------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; Name                                      ; Location           ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; button2                                   ; PIN_F1             ; 28      ; Latch enable ; no     ; --                   ; --               ; --                        ;
+; clk                                       ; PIN_G21            ; 20      ; Clock        ; yes    ; Global Clock         ; GCLK9            ; --                        ;
+; counter:timeCount|c0[3]~3                 ; LCCOMB_X28_Y27_N22 ; 5       ; Clock enable ; no     ; --                   ; --               ; --                        ;
+; counter:timeCount|c2[0]~4                 ; LCCOMB_X28_Y27_N18 ; 4       ; Clock enable ; no     ; --                   ; --               ; --                        ;
+; counter:timeCount|c3[1]~2                 ; LCCOMB_X27_Y28_N28 ; 4       ; Clock enable ; no     ; --                   ; --               ; --                        ;
+; hundred_hertz_clock:clockConv|LessThan0~5 ; LCCOMB_X19_Y27_N24 ; 19      ; Sync. clear  ; no     ; --                   ; --               ; --                        ;
+; hundred_hertz_clock:clockConv|clock_out   ; FF_X19_Y27_N23     ; 17      ; Clock        ; yes    ; Global Clock         ; GCLK14           ; --                        ;
+; hundred_hertz_clock:clockConv|start~0     ; LCCOMB_X19_Y27_N26 ; 19      ; Clock enable ; no     ; --                   ; --               ; --                        ;
++-------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                                                     ;
++-----------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name                                    ; Location       ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-----------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; clk                                     ; PIN_G21        ; 20      ; 5                                    ; Global Clock         ; GCLK9            ; --                        ;
+; hundred_hertz_clock:clockConv|clock_out ; FF_X19_Y27_N23 ; 17      ; 0                                    ; Global Clock         ; GCLK14           ; --                        ;
++-----------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------+
+; Non-Global High Fan-Out Signals                     ;
++-------------------------------------------+---------+
+; Name                                      ; Fan-Out ;
++-------------------------------------------+---------+
+; button2~input                             ; 28      ;
+; hundred_hertz_clock:clockConv|start~0     ; 19      ;
+; hundred_hertz_clock:clockConv|LessThan0~5 ; 19      ;
+; counter:timeCount|always0~0               ; 18      ;
+; counter:timeCount|c3[0]                   ; 12      ;
+; counter:timeCount|c2[0]                   ; 12      ;
+; counter:timeCount|c1[0]                   ; 12      ;
+; counter:timeCount|c3[1]                   ; 11      ;
+; counter:timeCount|c2[1]                   ; 11      ;
+; counter:timeCount|c1[1]                   ; 11      ;
+; counter:timeCount|c0[0]                   ; 11      ;
+; counter:timeCount|c3[2]                   ; 10      ;
+; counter:timeCount|c2[2]                   ; 10      ;
+; counter:timeCount|c1[2]                   ; 10      ;
+; counter:timeCount|c0[2]                   ; 10      ;
+; counter:timeCount|c0[1]                   ; 10      ;
+; counter:timeCount|c3[3]                   ; 9       ;
+; counter:timeCount|c2[3]                   ; 9       ;
+; counter:timeCount|c1[3]                   ; 9       ;
+; counter:timeCount|c0[3]                   ; 9       ;
+; counter:timeCount|c2[0]~1                 ; 6       ;
+; counter:timeCount|c2[0]~0                 ; 6       ;
+; counter:timeCount|c2[0]~2                 ; 5       ;
+; counter:timeCount|c0[3]~3                 ; 5       ;
+; button1~input                             ; 4       ;
+; counter:timeCount|c3[1]~2                 ; 4       ;
+; counter:timeCount|c3[1]~0                 ; 4       ;
+; counter:timeCount|c2[0]~4                 ; 4       ;
+; button0~input                             ; 2       ;
+; dec_to_seven_segment:dss3|out[6]          ; 2       ;
+; dec_to_seven_segment:dss3|out[5]          ; 2       ;
+; dec_to_seven_segment:dss3|out[4]          ; 2       ;
+; dec_to_seven_segment:dss3|out[3]          ; 2       ;
+; dec_to_seven_segment:dss3|out[2]          ; 2       ;
+; dec_to_seven_segment:dss3|out[1]          ; 2       ;
+; dec_to_seven_segment:dss3|out[0]          ; 2       ;
+; dec_to_seven_segment:dss2|out[6]          ; 2       ;
+; dec_to_seven_segment:dss2|out[5]          ; 2       ;
+; dec_to_seven_segment:dss2|out[4]          ; 2       ;
+; dec_to_seven_segment:dss2|out[3]          ; 2       ;
+; dec_to_seven_segment:dss2|out[2]          ; 2       ;
+; dec_to_seven_segment:dss2|out[1]          ; 2       ;
+; dec_to_seven_segment:dss2|out[0]          ; 2       ;
+; dec_to_seven_segment:dss1|out[6]          ; 2       ;
+; dec_to_seven_segment:dss1|out[5]          ; 2       ;
+; dec_to_seven_segment:dss1|out[4]          ; 2       ;
+; dec_to_seven_segment:dss1|out[3]          ; 2       ;
+; dec_to_seven_segment:dss1|out[2]          ; 2       ;
+; dec_to_seven_segment:dss1|out[1]          ; 2       ;
+; dec_to_seven_segment:dss1|out[0]          ; 2       ;
+; dec_to_seven_segment:dss0|out[6]          ; 2       ;
+; dec_to_seven_segment:dss0|out[5]          ; 2       ;
+; dec_to_seven_segment:dss0|out[4]          ; 2       ;
+; dec_to_seven_segment:dss0|out[3]          ; 2       ;
+; dec_to_seven_segment:dss0|out[2]          ; 2       ;
+; dec_to_seven_segment:dss0|out[1]          ; 2       ;
+; dec_to_seven_segment:dss0|out[0]          ; 2       ;
+; hundred_hertz_clock:clockConv|start       ; 2       ;
+; counter:timeCount|Add3~0                  ; 2       ;
+; counter:timeCount|en                      ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[7]      ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[6]      ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[5]      ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[4]      ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[3]      ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[2]      ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[1]      ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[0]      ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[11]     ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[10]     ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[9]      ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[8]      ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[17]     ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[16]     ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[15]     ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[14]     ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[12]     ; 2       ;
+; hundred_hertz_clock:clockConv|ctr[13]     ; 2       ;
+; hundred_hertz_clock:clockConv|clock_out~0 ; 1       ;
+; hundred_hertz_clock:clockConv|LessThan0~4 ; 1       ;
+; hundred_hertz_clock:clockConv|LessThan0~3 ; 1       ;
+; hundred_hertz_clock:clockConv|LessThan0~2 ; 1       ;
+; hundred_hertz_clock:clockConv|LessThan0~1 ; 1       ;
+; hundred_hertz_clock:clockConv|LessThan0~0 ; 1       ;
+; counter:timeCount|c3~5                    ; 1       ;
+; counter:timeCount|Add0~1                  ; 1       ;
+; counter:timeCount|c3~4                    ; 1       ;
+; counter:timeCount|Add0~0                  ; 1       ;
+; counter:timeCount|c3~3                    ; 1       ;
+; counter:timeCount|c3~1                    ; 1       ;
+; counter:timeCount|c2~7                    ; 1       ;
+; counter:timeCount|Add1~1                  ; 1       ;
+; counter:timeCount|c2~6                    ; 1       ;
+; counter:timeCount|Add1~0                  ; 1       ;
+; counter:timeCount|c2~5                    ; 1       ;
+; counter:timeCount|c2~3                    ; 1       ;
+; counter:timeCount|c1~3                    ; 1       ;
+; counter:timeCount|Add2~1                  ; 1       ;
+; counter:timeCount|c1~2                    ; 1       ;
+; counter:timeCount|Add2~0                  ; 1       ;
+; counter:timeCount|c1~1                    ; 1       ;
+; counter:timeCount|c1~0                    ; 1       ;
+; counter:timeCount|c0~4                    ; 1       ;
+; counter:timeCount|c0~2                    ; 1       ;
+; counter:timeCount|c0~1                    ; 1       ;
+; hundred_hertz_clock:clockConv|clock_out   ; 1       ;
+; counter:timeCount|c0~0                    ; 1       ;
+; dec_to_seven_segment:dss3|WideOr0~0       ; 1       ;
+; dec_to_seven_segment:dss3|WideOr1~0       ; 1       ;
+; dec_to_seven_segment:dss3|WideOr2~0       ; 1       ;
+; dec_to_seven_segment:dss3|WideOr3~0       ; 1       ;
+; dec_to_seven_segment:dss3|WideOr4~0       ; 1       ;
+; dec_to_seven_segment:dss3|out~1           ; 1       ;
+; dec_to_seven_segment:dss3|out~0           ; 1       ;
+; dec_to_seven_segment:dss2|WideOr0~0       ; 1       ;
+; dec_to_seven_segment:dss2|WideOr1~0       ; 1       ;
+; dec_to_seven_segment:dss2|WideOr2~0       ; 1       ;
+; dec_to_seven_segment:dss2|WideOr3~0       ; 1       ;
+; dec_to_seven_segment:dss2|WideOr4~0       ; 1       ;
+; dec_to_seven_segment:dss2|out~1           ; 1       ;
+; dec_to_seven_segment:dss2|out~0           ; 1       ;
+; dec_to_seven_segment:dss1|WideOr0~0       ; 1       ;
+; dec_to_seven_segment:dss1|WideOr1~0       ; 1       ;
+; dec_to_seven_segment:dss1|WideOr2~0       ; 1       ;
+; dec_to_seven_segment:dss1|WideOr3~0       ; 1       ;
+; dec_to_seven_segment:dss1|WideOr4~0       ; 1       ;
+; dec_to_seven_segment:dss1|out~1           ; 1       ;
+; dec_to_seven_segment:dss1|out~0           ; 1       ;
+; dec_to_seven_segment:dss0|WideOr0~0       ; 1       ;
+; dec_to_seven_segment:dss0|WideOr1~0       ; 1       ;
+; dec_to_seven_segment:dss0|WideOr2~0       ; 1       ;
+; dec_to_seven_segment:dss0|WideOr3~0       ; 1       ;
+; dec_to_seven_segment:dss0|WideOr4~0       ; 1       ;
+; dec_to_seven_segment:dss0|out~1           ; 1       ;
+; dec_to_seven_segment:dss0|out~0           ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[17]~52  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[16]~51  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[16]~50  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[15]~49  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[15]~48  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[14]~47  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[14]~46  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[13]~45  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[13]~44  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[12]~43  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[12]~42  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[11]~41  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[11]~40  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[10]~39  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[10]~38  ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[9]~37   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[9]~36   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[8]~35   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[8]~34   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[7]~33   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[7]~32   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[6]~31   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[6]~30   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[5]~29   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[5]~28   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[4]~27   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[4]~26   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[3]~25   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[3]~24   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[2]~23   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[2]~22   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[1]~21   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[1]~20   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[0]~19   ; 1       ;
+; hundred_hertz_clock:clockConv|ctr[0]~18   ; 1       ;
++-------------------------------------------+---------+
+
+
++------------------------------------------------+
+; Routing Usage Summary                          ;
++-----------------------+------------------------+
+; Routing Resource Type ; Usage                  ;
++-----------------------+------------------------+
+; Block interconnects   ; 106 / 47,787 ( < 1 % ) ;
+; C16 interconnects     ; 1 / 1,804 ( < 1 % )    ;
+; C4 interconnects      ; 55 / 31,272 ( < 1 % )  ;
+; Direct links          ; 42 / 47,787 ( < 1 % )  ;
+; Global clocks         ; 2 / 20 ( 10 % )        ;
+; Local interconnects   ; 99 / 15,408 ( < 1 % )  ;
+; R24 interconnects     ; 9 / 1,775 ( < 1 % )    ;
+; R4 interconnects      ; 50 / 41,310 ( < 1 % )  ;
++-----------------------+------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Logic Elements                                                         ;
++---------------------------------------------+------------------------------+
+; Number of Logic Elements  (Average = 11.40) ; Number of LABs  (Total = 10) ;
++---------------------------------------------+------------------------------+
+; 1                                           ; 0                            ;
+; 2                                           ; 0                            ;
+; 3                                           ; 0                            ;
+; 4                                           ; 1                            ;
+; 5                                           ; 1                            ;
+; 6                                           ; 1                            ;
+; 7                                           ; 0                            ;
+; 8                                           ; 1                            ;
+; 9                                           ; 0                            ;
+; 10                                          ; 0                            ;
+; 11                                          ; 0                            ;
+; 12                                          ; 0                            ;
+; 13                                          ; 1                            ;
+; 14                                          ; 1                            ;
+; 15                                          ; 0                            ;
+; 16                                          ; 4                            ;
++---------------------------------------------+------------------------------+
+
+
++-------------------------------------------------------------------+
+; LAB-wide Signals                                                  ;
++------------------------------------+------------------------------+
+; LAB-wide Signals  (Average = 0.90) ; Number of LABs  (Total = 10) ;
++------------------------------------+------------------------------+
+; 1 Clock                            ; 6                            ;
+; 1 Clock enable                     ; 2                            ;
+; 1 Sync. clear                      ; 1                            ;
++------------------------------------+------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                         ;
++----------------------------------------------+------------------------------+
+; Number of Signals Sourced  (Average = 15.10) ; Number of LABs  (Total = 10) ;
++----------------------------------------------+------------------------------+
+; 0                                            ; 0                            ;
+; 1                                            ; 0                            ;
+; 2                                            ; 0                            ;
+; 3                                            ; 0                            ;
+; 4                                            ; 1                            ;
+; 5                                            ; 1                            ;
+; 6                                            ; 1                            ;
+; 7                                            ; 0                            ;
+; 8                                            ; 1                            ;
+; 9                                            ; 0                            ;
+; 10                                           ; 0                            ;
+; 11                                           ; 0                            ;
+; 12                                           ; 0                            ;
+; 13                                           ; 0                            ;
+; 14                                           ; 0                            ;
+; 15                                           ; 0                            ;
+; 16                                           ; 0                            ;
+; 17                                           ; 0                            ;
+; 18                                           ; 0                            ;
+; 19                                           ; 0                            ;
+; 20                                           ; 3                            ;
+; 21                                           ; 1                            ;
+; 22                                           ; 1                            ;
+; 23                                           ; 0                            ;
+; 24                                           ; 0                            ;
+; 25                                           ; 1                            ;
++----------------------------------------------+------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                        ;
++-------------------------------------------------+------------------------------+
+; Number of Signals Sourced Out  (Average = 6.40) ; Number of LABs  (Total = 10) ;
++-------------------------------------------------+------------------------------+
+; 0                                               ; 0                            ;
+; 1                                               ; 1                            ;
+; 2                                               ; 0                            ;
+; 3                                               ; 1                            ;
+; 4                                               ; 3                            ;
+; 5                                               ; 0                            ;
+; 6                                               ; 1                            ;
+; 7                                               ; 0                            ;
+; 8                                               ; 0                            ;
+; 9                                               ; 0                            ;
+; 10                                              ; 2                            ;
+; 11                                              ; 2                            ;
++-------------------------------------------------+------------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                        ;
++---------------------------------------------+------------------------------+
+; Number of Distinct Inputs  (Average = 5.90) ; Number of LABs  (Total = 10) ;
++---------------------------------------------+------------------------------+
+; 0                                           ; 0                            ;
+; 1                                           ; 0                            ;
+; 2                                           ; 0                            ;
+; 3                                           ; 0                            ;
+; 4                                           ; 1                            ;
+; 5                                           ; 2                            ;
+; 6                                           ; 6                            ;
+; 7                                           ; 0                            ;
+; 8                                           ; 0                            ;
+; 9                                           ; 1                            ;
++---------------------------------------------+------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 12    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 18    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 33        ; 0            ; 33        ; 0            ; 0            ; 33        ; 33        ; 0            ; 33        ; 33        ; 0            ; 29           ; 0            ; 0            ; 4            ; 0            ; 29           ; 4            ; 0            ; 0            ; 0            ; 29           ; 0            ; 0            ; 0            ; 0            ; 0            ; 33        ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 33           ; 0         ; 33           ; 33           ; 0         ; 0         ; 33           ; 0         ; 0         ; 33           ; 4            ; 33           ; 33           ; 29           ; 33           ; 4            ; 29           ; 33           ; 33           ; 33           ; 4            ; 33           ; 33           ; 33           ; 33           ; 33           ; 0         ; 33           ; 33           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; hex0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex3[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex3[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex3[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex3[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex3[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex3[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; hex3[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; decimal_point      ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; button2            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; button0            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; button1            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; clk                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                      ;
++-----------------------------------------+----------------------+-------------------+
+; Source Clock(s)                         ; Destination Clock(s) ; Delay Added in ns ;
++-----------------------------------------+----------------------+-------------------+
+; I/O                                     ; button2              ; 5.9               ;
+; hundred_hertz_clock:clockConv|clock_out ; button2              ; 5.7               ;
+; clk                                     ; clk                  ; 1.9               ;
++-----------------------------------------+----------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++-------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                         ;
++-----------------------------------------+-----------------------------------------+-------------------+
+; Source Register                         ; Destination Register                    ; Delay Added in ns ;
++-----------------------------------------+-----------------------------------------+-------------------+
+; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.967             ;
+; button2                                 ; dec_to_seven_segment:dss1|out[3]        ; 0.372             ;
+; counter:timeCount|c3[1]                 ; dec_to_seven_segment:dss3|out[3]        ; 0.217             ;
+; counter:timeCount|c0[1]                 ; dec_to_seven_segment:dss0|out[3]        ; 0.217             ;
+; counter:timeCount|c2[1]                 ; dec_to_seven_segment:dss2|out[5]        ; 0.196             ;
+; counter:timeCount|c1[1]                 ; dec_to_seven_segment:dss1|out[5]        ; 0.196             ;
+; counter:timeCount|c3[0]                 ; dec_to_seven_segment:dss3|out[5]        ; 0.192             ;
+; counter:timeCount|c2[0]                 ; dec_to_seven_segment:dss2|out[5]        ; 0.192             ;
+; counter:timeCount|c1[0]                 ; dec_to_seven_segment:dss1|out[5]        ; 0.192             ;
+; counter:timeCount|c0[0]                 ; dec_to_seven_segment:dss0|out[3]        ; 0.187             ;
+; counter:timeCount|c3[2]                 ; dec_to_seven_segment:dss3|out[1]        ; 0.145             ;
+; counter:timeCount|c1[2]                 ; dec_to_seven_segment:dss1|out[1]        ; 0.145             ;
+; counter:timeCount|c0[2]                 ; dec_to_seven_segment:dss0|out[1]        ; 0.142             ;
+; counter:timeCount|c2[2]                 ; dec_to_seven_segment:dss2|out[6]        ; 0.132             ;
+; counter:timeCount|c3[3]                 ; dec_to_seven_segment:dss3|out[6]        ; 0.129             ;
+; counter:timeCount|c2[3]                 ; dec_to_seven_segment:dss2|out[6]        ; 0.129             ;
+; counter:timeCount|c1[3]                 ; dec_to_seven_segment:dss1|out[6]        ; 0.129             ;
+; counter:timeCount|c0[3]                 ; dec_to_seven_segment:dss0|out[6]        ; 0.125             ;
+; hundred_hertz_clock:clockConv|ctr[16]   ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[15]   ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[17]   ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[1]    ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[0]    ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[7]    ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|start     ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; button1                                 ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
+; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|clock_out ; 0.041             ;
++-----------------------------------------+-----------------------------------------+-------------------+
+Note: This table only shows the top 38 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (119006): Selected device EP3C16U484C6 for design "stopclock"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40U484C6 is compatible
+    Info (176445): Device EP3C55U484C6 is compatible
+    Info (176445): Device EP3C80U484C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location K22
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Warning (335093): TimeQuest Timing Analyzer is analyzing 28 combinational loops as latches.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'stopclock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176353): Automatically promoted node clk~input (placed in PIN G21 (CLK4, DIFFCLK_2p))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
+Info (176353): Automatically promoted node hundred_hertz_clock:clockConv|clock_out 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node hundred_hertz_clock:clockConv|clock_out~0
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.28 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Info (144001): Generated suppressed messages file C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 839 megabytes
+    Info: Processing ended: Wed Mar 02 15:24:40 2016
+    Info: Elapsed time: 00:00:09
+    Info: Total CPU time (on all processors): 00:00:08
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.fit.smsg.
+
+
diff --git a/stopClockVerilog/output_files/stopclock.fit.smsg b/stopClockVerilog/output_files/stopclock.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/stopClockVerilog/output_files/stopclock.fit.summary b/stopClockVerilog/output_files/stopclock.fit.summary
new file mode 100644
index 0000000..ae3d392
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Wed Mar 02 15:24:39 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : stopclock
+Top-level Entity Name : stopclock
+Family : Cyclone III
+Device : EP3C16U484C6
+Timing Models : Final
+Total logic elements : 114 / 15,408 ( < 1 % )
+    Total combinational functions : 113 / 15,408 ( < 1 % )
+    Dedicated logic registers : 37 / 15,408 ( < 1 % )
+Total registers : 37
+Total pins : 33 / 347 ( 10 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/stopClockVerilog/output_files/stopclock.flow.rpt b/stopClockVerilog/output_files/stopclock.flow.rpt
new file mode 100644
index 0000000..37a177c
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.flow.rpt
@@ -0,0 +1,128 @@
+Flow report for stopclock
+Wed Mar 02 15:24:50 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Flow Summary                                                                    ;
++------------------------------------+--------------------------------------------+
+; Flow Status                        ; Successful - Wed Mar 02 15:24:50 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; stopclock                                  ;
+; Top-level Entity Name              ; stopclock                                  ;
+; Family                             ; Cyclone III                                ;
+; Device                             ; EP3C16U484C6                               ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 114 / 15,408 ( < 1 % )                     ;
+;     Total combinational functions  ; 113 / 15,408 ( < 1 % )                     ;
+;     Dedicated logic registers      ; 37 / 15,408 ( < 1 % )                      ;
+; Total registers                    ; 37                                         ;
+; Total pins                         ; 33 / 347 ( 10 % )                          ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                            ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 03/02/2016 15:24:28 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; stopclock           ;
++-------------------+---------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; Assignment Name                     ; Value                           ; Default Value ; Entity Name ; Section Id     ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID               ; 190206087543991.145693226816548 ; --            ; --          ; --             ;
+; EDA_OUTPUT_DATA_FORMAT              ; Vhdl                            ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (VHDL)          ; <None>        ; --          ; --             ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                              ; --            ; --          ; --             ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                               ; --            ; --          ; --             ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                            ; --            ; --          ; --             ;
+; PARTITION_COLOR                     ; 16764057                        ; --            ; --          ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING           ; --            ; --          ; Top            ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                          ; --            ; --          ; Top            ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                    ; --            ; --          ; --             ;
++-------------------------------------+---------------------------------+---------------+-------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:02     ; 1.0                     ; 495 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:08     ; 1.0                     ; 839 MB              ; 00:00:08                           ;
+; Assembler                 ; 00:00:02     ; 1.0                     ; 457 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 502 MB              ; 00:00:02                           ;
+; EDA Netlist Writer        ; 00:00:01     ; 1.0                     ; 420 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:15     ; --                      ; --                  ; 00:00:13                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Fitter                    ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; Assembler                 ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; TimeQuest Timing Analyzer ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
+; EDA Netlist Writer        ; n55              ; Windows 7 ; 6.2        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off stopclock -c stopclock
+quartus_fit --read_settings_files=off --write_settings_files=off stopclock -c stopclock
+quartus_asm --read_settings_files=off --write_settings_files=off stopclock -c stopclock
+quartus_sta stopclock -c stopclock
+quartus_eda --read_settings_files=off --write_settings_files=off stopclock -c stopclock
+
+
+
diff --git a/stopClockVerilog/output_files/stopclock.jdi b/stopClockVerilog/output_files/stopclock.jdi
new file mode 100644
index 0000000..50984d2
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="6d68b5e4c56d01cfd9f5"/>
+  </project>
+  <file_info>
+    <file device="EP3C16U484C6" path="stopclock.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/stopClockVerilog/output_files/stopclock.map.rpt b/stopClockVerilog/output_files/stopclock.map.rpt
new file mode 100644
index 0000000..0b50758
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.map.rpt
@@ -0,0 +1,353 @@
+Analysis & Synthesis report for stopclock
+Wed Mar 02 15:24:29 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. User-Specified and Inferred Latches
+  9. General Register Statistics
+ 10. Inverted Register Statistics
+ 11. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 12. Elapsed Time Per Partition
+ 13. Analysis & Synthesis Messages
+ 14. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                    ;
++------------------------------------+--------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Wed Mar 02 15:24:29 2016      ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; stopclock                                  ;
+; Top-level Entity Name              ; stopclock                                  ;
+; Family                             ; Cyclone III                                ;
+; Total logic elements               ; 113                                        ;
+;     Total combinational functions  ; 113                                        ;
+;     Dedicated logic registers      ; 37                                         ;
+; Total registers                    ; 37                                         ;
+; Total pins                         ; 33                                         ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0                                          ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total PLLs                         ; 0                                          ;
++------------------------------------+--------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16U484C6       ;                    ;
+; Top-level entity name                                                      ; stopclock          ; stopclock          ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                  ;
++----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                                    ; Library ;
++----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------------------------+---------+
+; stopclock.v                      ; yes             ; User Verilog HDL File  ; C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v ;         ;
++----------------------------------+-----------------+------------------------+-------------------------------------------------------------------------------------------------+---------+
+
+
++-------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                 ;
++---------------------------------------------+---------------+
+; Resource                                    ; Usage         ;
++---------------------------------------------+---------------+
+; Estimated Total logic elements              ; 113           ;
+;                                             ;               ;
+; Total combinational functions               ; 113           ;
+; Logic element usage by number of LUT inputs ;               ;
+;     -- 4 input functions                    ; 49            ;
+;     -- 3 input functions                    ; 44            ;
+;     -- <=2 input functions                  ; 20            ;
+;                                             ;               ;
+; Logic elements by mode                      ;               ;
+;     -- normal mode                          ; 96            ;
+;     -- arithmetic mode                      ; 17            ;
+;                                             ;               ;
+; Total registers                             ; 37            ;
+;     -- Dedicated logic registers            ; 37            ;
+;     -- I/O registers                        ; 0             ;
+;                                             ;               ;
+; I/O pins                                    ; 33            ;
+; Embedded Multiplier 9-bit elements          ; 0             ;
+; Maximum fan-out node                        ; button2~input ;
+; Maximum fan-out                             ; 28            ;
+; Total fan-out                               ; 550           ;
+; Average fan-out                             ; 2.55          ;
++---------------------------------------------+---------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                      ;
++------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------+--------------+
+; Compilation Hierarchy Node         ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                      ; Library Name ;
++------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------+--------------+
+; |stopclock                         ; 113 (0)           ; 37 (0)       ; 0           ; 0            ; 0       ; 0         ; 33   ; 0            ; |stopclock                               ; work         ;
+;    |counter:timeCount|             ; 31 (31)           ; 17 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopclock|counter:timeCount             ; work         ;
+;    |dec_to_seven_segment:dss0|     ; 14 (14)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopclock|dec_to_seven_segment:dss0     ; work         ;
+;    |dec_to_seven_segment:dss1|     ; 14 (14)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopclock|dec_to_seven_segment:dss1     ; work         ;
+;    |dec_to_seven_segment:dss2|     ; 14 (14)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopclock|dec_to_seven_segment:dss2     ; work         ;
+;    |dec_to_seven_segment:dss3|     ; 14 (14)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopclock|dec_to_seven_segment:dss3     ; work         ;
+;    |hundred_hertz_clock:clockConv| ; 26 (26)           ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |stopclock|hundred_hertz_clock:clockConv ; work         ;
++------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++----------------------------------------------------------------------------------------------------+
+; User-Specified and Inferred Latches                                                                ;
++-----------------------------------------------------+---------------------+------------------------+
+; Latch Name                                          ; Latch Enable Signal ; Free of Timing Hazards ;
++-----------------------------------------------------+---------------------+------------------------+
+; dec_to_seven_segment:dss0|out[0]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss0|out[1]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss0|out[2]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss0|out[3]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss0|out[4]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss0|out[5]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss0|out[6]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss1|out[0]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss1|out[1]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss1|out[2]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss1|out[3]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss1|out[4]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss1|out[5]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss1|out[6]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss2|out[0]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss2|out[1]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss2|out[2]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss2|out[3]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss2|out[4]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss2|out[5]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss2|out[6]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss3|out[0]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss3|out[1]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss3|out[2]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss3|out[3]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss3|out[4]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss3|out[5]                    ; button2             ; yes                    ;
+; dec_to_seven_segment:dss3|out[6]                    ; button2             ; yes                    ;
+; Number of user-specified and inferred latches = 28  ;                     ;                        ;
++-----------------------------------------------------+---------------------+------------------------+
+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 37    ;
+; Number of registers using Synchronous Clear  ; 18    ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 30    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; counter:timeCount|en                   ; 2       ;
+; Total number of inverted registers = 1 ;         ;
++----------------------------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                   ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output         ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
+; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |stopclock|counter:timeCount|c0[3] ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |stopclock|counter:timeCount|c1[0] ;
+; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |stopclock|counter:timeCount|c2[0] ;
+; 6:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |stopclock|counter:timeCount|c3[1] ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Wed Mar 02 15:24:27 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off stopclock -c stopclock
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 4 design units, including 4 entities, in source file stopclock.v
+    Info (12023): Found entity 1: hundred_hertz_clock
+    Info (12023): Found entity 2: counter
+    Info (12023): Found entity 3: dec_to_seven_segment
+    Info (12023): Found entity 4: stopclock
+Warning (12019): Can't analyze file -- file stopClock.bdf is missing
+Info (12021): Found 1 design units, including 1 entities, in source file stopclockblock.bdf
+    Info (12023): Found entity 1: stopClockBlock
+Info (12127): Elaborating entity "stopclock" for the top level hierarchy
+Info (12128): Elaborating entity "hundred_hertz_clock" for hierarchy "hundred_hertz_clock:clockConv"
+Info (12128): Elaborating entity "counter" for hierarchy "counter:timeCount"
+Info (12128): Elaborating entity "dec_to_seven_segment" for hierarchy "dec_to_seven_segment:dss0"
+Warning (10240): Verilog HDL Always Construct warning at stopclock.v(87): inferring latch(es) for variable "out", which holds its previous value in one or more paths through the always construct
+Info (10041): Inferred latch for "out[0]" at stopclock.v(89)
+Info (10041): Inferred latch for "out[1]" at stopclock.v(89)
+Info (10041): Inferred latch for "out[2]" at stopclock.v(89)
+Info (10041): Inferred latch for "out[3]" at stopclock.v(89)
+Info (10041): Inferred latch for "out[4]" at stopclock.v(89)
+Info (10041): Inferred latch for "out[5]" at stopclock.v(89)
+Info (10041): Inferred latch for "out[6]" at stopclock.v(89)
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "decimal_point" is stuck at GND
+Info (286030): Timing-Driven Synthesis is running
+Info (144001): Generated suppressed messages file C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 148 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 4 input pins
+    Info (21059): Implemented 29 output pins
+    Info (21061): Implemented 115 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 506 megabytes
+    Info: Processing ended: Wed Mar 02 15:24:29 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.map.smsg.
+
+
diff --git a/stopClockVerilog/output_files/stopclock.map.smsg b/stopClockVerilog/output_files/stopclock.map.smsg
new file mode 100644
index 0000000..3f508bc
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.map.smsg
@@ -0,0 +1,2 @@
+Warning (10268): Verilog HDL information at stopclock.v(11): always construct contains both blocking and non-blocking assignments
+Warning (10268): Verilog HDL information at stopclock.v(40): always construct contains both blocking and non-blocking assignments
diff --git a/stopClockVerilog/output_files/stopclock.map.summary b/stopClockVerilog/output_files/stopclock.map.summary
new file mode 100644
index 0000000..638d8ab
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Wed Mar 02 15:24:29 2016
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : stopclock
+Top-level Entity Name : stopclock
+Family : Cyclone III
+Total logic elements : 113
+    Total combinational functions : 113
+    Dedicated logic registers : 37
+Total registers : 37
+Total pins : 33
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/stopClockVerilog/output_files/stopclock.pin b/stopClockVerilog/output_files/stopclock.pin
new file mode 100644
index 0000000..5de7a4c
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		2.5V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		2.5V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+CHIP  "stopclock"  ASSIGNED TO AN: EP3C16U484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+hex1[0]                      : A13       : output : 2.5 V             :         : 7         : Y              
+hex1[3]                      : A14       : output : 2.5 V             :         : 7         : Y              
+hex1[6]                      : A15       : output : 2.5 V             :         : 7         : Y              
+hex2[1]                      : A16       : output : 2.5 V             :         : 7         : Y              
+hex2[4]                      : A17       : output : 2.5 V             :         : 7         : Y              
+decimal_point                : A18       : output : 2.5 V             :         : 7         : Y              
+hex3[2]                      : A19       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 2.5V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+hex1[1]                      : B13       : output : 2.5 V             :         : 7         : Y              
+hex1[4]                      : B14       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+hex2[2]                      : B16       : output : 2.5 V             :         : 7         : Y              
+hex2[5]                      : B17       : output : 2.5 V             :         : 7         : Y              
+hex3[0]                      : B18       : output : 2.5 V             :         : 7         : Y              
+hex3[3]                      : B19       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+hex1[2]                      : C13       : output : 2.5 V             :         : 7         : Y              
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+hex3[4]                      : C19       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 1         :                
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 2.5V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 2.5V    : 7         :                
+hex2[0]                      : D15       : output : 2.5 V             :         : 7         : Y              
+VCCIO7                       : D16       : power  :                   : 2.5V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 2.5V    : 7         :                
+hex3[5]                      : D19       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 1         :                
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 2.5 V             :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
+hex0[0]                      : E11       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+hex1[5]                      : E14       : output : 2.5 V             :         : 7         : Y              
+hex2[3]                      : E15       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 2.5V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+button2                      : F1        : input  : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F2        :        :                   :         : 1         :                
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 2.5V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+hex0[1]                      : F11       : output : 2.5 V             :         : 7         : Y              
+hex0[5]                      : F12       : output : 2.5 V             :         : 7         : Y              
+hex0[6]                      : F13       : output : 2.5 V             :         : 7         : Y              
+hex2[6]                      : F14       : output : 2.5 V             :         : 7         : Y              
+hex3[1]                      : F15       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+button1                      : G3        : input  : 2.5 V             :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G4        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+hex0[4]                      : G12       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+hex3[6]                      : G15       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 2.5V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+clk                          : G21       : input  : 2.5 V             :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H1        :        :                   :         : 1         :                
+button0                      : H2        : input  : 2.5 V             :         : 1         : Y              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 2.5V    : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H5        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 1         :                
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+hex0[2]                      : H12       : output : 2.5 V             :         : 7         : Y              
+hex0[3]                      : H13       : output : 2.5 V             :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J3        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 1         :                
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 2.5V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 6         :                
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 2.5 V             :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 2.5 V             :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 2.5V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 2.5 V             :         : 6         : N              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 2.5V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/stopClockVerilog/output_files/stopclock.sof b/stopClockVerilog/output_files/stopclock.sof
new file mode 100644
index 0000000..12f2deb
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.sof
diff --git a/stopClockVerilog/output_files/stopclock.sta.rpt b/stopClockVerilog/output_files/stopclock.sta.rpt
new file mode 100644
index 0000000..550440d
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.sta.rpt
@@ -0,0 +1,3927 @@
+TimeQuest Timing Analyzer report for stopclock
+Wed Mar 02 15:24:47 2016
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Setup: 'clk'
+ 13. Slow 1200mV 85C Model Setup: 'hundred_hertz_clock:clockConv|clock_out'
+ 14. Slow 1200mV 85C Model Setup: 'button2'
+ 15. Slow 1200mV 85C Model Hold: 'clk'
+ 16. Slow 1200mV 85C Model Hold: 'hundred_hertz_clock:clockConv|clock_out'
+ 17. Slow 1200mV 85C Model Hold: 'button2'
+ 18. Slow 1200mV 85C Model Minimum Pulse Width: 'clk'
+ 19. Slow 1200mV 85C Model Minimum Pulse Width: 'button2'
+ 20. Slow 1200mV 85C Model Minimum Pulse Width: 'hundred_hertz_clock:clockConv|clock_out'
+ 21. Setup Times
+ 22. Hold Times
+ 23. Clock to Output Times
+ 24. Minimum Clock to Output Times
+ 25. Slow 1200mV 85C Model Metastability Report
+ 26. Slow 1200mV 0C Model Fmax Summary
+ 27. Slow 1200mV 0C Model Setup Summary
+ 28. Slow 1200mV 0C Model Hold Summary
+ 29. Slow 1200mV 0C Model Recovery Summary
+ 30. Slow 1200mV 0C Model Removal Summary
+ 31. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 32. Slow 1200mV 0C Model Setup: 'clk'
+ 33. Slow 1200mV 0C Model Setup: 'hundred_hertz_clock:clockConv|clock_out'
+ 34. Slow 1200mV 0C Model Setup: 'button2'
+ 35. Slow 1200mV 0C Model Hold: 'clk'
+ 36. Slow 1200mV 0C Model Hold: 'hundred_hertz_clock:clockConv|clock_out'
+ 37. Slow 1200mV 0C Model Hold: 'button2'
+ 38. Slow 1200mV 0C Model Minimum Pulse Width: 'clk'
+ 39. Slow 1200mV 0C Model Minimum Pulse Width: 'button2'
+ 40. Slow 1200mV 0C Model Minimum Pulse Width: 'hundred_hertz_clock:clockConv|clock_out'
+ 41. Setup Times
+ 42. Hold Times
+ 43. Clock to Output Times
+ 44. Minimum Clock to Output Times
+ 45. Slow 1200mV 0C Model Metastability Report
+ 46. Fast 1200mV 0C Model Setup Summary
+ 47. Fast 1200mV 0C Model Hold Summary
+ 48. Fast 1200mV 0C Model Recovery Summary
+ 49. Fast 1200mV 0C Model Removal Summary
+ 50. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 51. Fast 1200mV 0C Model Setup: 'clk'
+ 52. Fast 1200mV 0C Model Setup: 'hundred_hertz_clock:clockConv|clock_out'
+ 53. Fast 1200mV 0C Model Setup: 'button2'
+ 54. Fast 1200mV 0C Model Hold: 'clk'
+ 55. Fast 1200mV 0C Model Hold: 'button2'
+ 56. Fast 1200mV 0C Model Hold: 'hundred_hertz_clock:clockConv|clock_out'
+ 57. Fast 1200mV 0C Model Minimum Pulse Width: 'clk'
+ 58. Fast 1200mV 0C Model Minimum Pulse Width: 'button2'
+ 59. Fast 1200mV 0C Model Minimum Pulse Width: 'hundred_hertz_clock:clockConv|clock_out'
+ 60. Setup Times
+ 61. Hold Times
+ 62. Clock to Output Times
+ 63. Minimum Clock to Output Times
+ 64. Fast 1200mV 0C Model Metastability Report
+ 65. Multicorner Timing Analysis Summary
+ 66. Setup Times
+ 67. Hold Times
+ 68. Clock to Output Times
+ 69. Minimum Clock to Output Times
+ 70. Board Trace Model Assignments
+ 71. Input Transition Times
+ 72. Slow Corner Signal Integrity Metrics
+ 73. Fast Corner Signal Integrity Metrics
+ 74. Setup Transfers
+ 75. Hold Transfers
+ 76. Report TCCS
+ 77. Report RSKM
+ 78. Unconstrained Paths
+ 79. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                       ;
++--------------------+----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name      ; stopclock                                          ;
+; Device Family      ; Cyclone III                                        ;
+; Device Name        ; EP3C16U484C6                                       ;
+; Timing Models      ; Final                                              ;
+; Delay Model        ; Combined                                           ;
+; Rise/Fall Delays   ; Enabled                                            ;
++--------------------+----------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                                                           ;
++-----------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------------------------------------+
+; Clock Name                              ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                     ;
++-----------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------------------------------------+
+; button2                                 ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { button2 }                                 ;
+; clk                                     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk }                                     ;
+; hundred_hertz_clock:clockConv|clock_out ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { hundred_hertz_clock:clockConv|clock_out } ;
++-----------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                                                                     ;
++------------+-----------------+-----------------------------------------+---------------------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name                              ; Note                                                          ;
++------------+-----------------+-----------------------------------------+---------------------------------------------------------------+
+; 305.44 MHz ; 250.0 MHz       ; clk                                     ; limit due to minimum period restriction (max I/O toggle rate) ;
+; 358.81 MHz ; 358.81 MHz      ; hundred_hertz_clock:clockConv|clock_out ;                                                               ;
++------------+-----------------+-----------------------------------------+---------------------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup Summary                              ;
++-----------------------------------------+--------+---------------+
+; Clock                                   ; Slack  ; End Point TNS ;
++-----------------------------------------+--------+---------------+
+; clk                                     ; -2.274 ; -38.401       ;
+; hundred_hertz_clock:clockConv|clock_out ; -1.787 ; -25.453       ;
+; button2                                 ; -1.727 ; -34.724       ;
++-----------------------------------------+--------+---------------+
+
+
++------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold Summary                               ;
++-----------------------------------------+--------+---------------+
+; Clock                                   ; Slack  ; End Point TNS ;
++-----------------------------------------+--------+---------------+
+; clk                                     ; -0.504 ; -0.504        ;
+; hundred_hertz_clock:clockConv|clock_out ; 0.359  ; 0.000         ;
+; button2                                 ; 0.615  ; 0.000         ;
++-----------------------------------------+--------+---------------+
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary                ;
++-----------------------------------------+--------+---------------+
+; Clock                                   ; Slack  ; End Point TNS ;
++-----------------------------------------+--------+---------------+
+; clk                                     ; -3.000 ; -23.000       ;
+; button2                                 ; -3.000 ; -3.000        ;
+; hundred_hertz_clock:clockConv|clock_out ; -1.000 ; -17.000       ;
++-----------------------------------------+--------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'clk'                                                                                                                           ;
++--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                             ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
+; -2.274 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.208      ;
+; -2.274 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.208      ;
+; -2.274 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.208      ;
+; -2.274 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.208      ;
+; -2.274 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.208      ;
+; -2.274 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.208      ;
+; -2.260 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.194      ;
+; -2.260 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.194      ;
+; -2.260 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.194      ;
+; -2.260 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.194      ;
+; -2.260 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.194      ;
+; -2.260 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.194      ;
+; -2.220 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.154      ;
+; -2.220 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.154      ;
+; -2.220 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.154      ;
+; -2.220 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.154      ;
+; -2.220 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.154      ;
+; -2.220 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.154      ;
+; -2.167 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.737      ;
+; -2.167 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.737      ;
+; -2.167 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.737      ;
+; -2.167 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.737      ;
+; -2.167 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.737      ;
+; -2.167 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.737      ;
+; -2.161 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.095      ;
+; -2.161 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.095      ;
+; -2.161 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.095      ;
+; -2.161 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.095      ;
+; -2.161 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.095      ;
+; -2.161 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.095      ;
+; -2.104 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.038      ;
+; -2.104 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.038      ;
+; -2.104 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.038      ;
+; -2.104 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.038      ;
+; -2.104 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.038      ;
+; -2.104 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.038      ;
+; -2.085 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.019      ;
+; -2.085 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.019      ;
+; -2.085 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.019      ;
+; -2.085 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.019      ;
+; -2.085 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.019      ;
+; -2.085 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.061     ; 3.019      ;
+; -2.058 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.628      ;
+; -2.058 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.628      ;
+; -2.058 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.628      ;
+; -2.058 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.628      ;
+; -2.058 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.628      ;
+; -2.058 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.628      ;
+; -2.043 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.977      ;
+; -2.043 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.977      ;
+; -2.043 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.977      ;
+; -2.043 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.977      ;
+; -2.043 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.977      ;
+; -2.043 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.977      ;
+; -2.029 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.599      ;
+; -2.029 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.599      ;
+; -2.029 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.599      ;
+; -2.029 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.599      ;
+; -2.029 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.599      ;
+; -2.029 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.425     ; 2.599      ;
+; -1.950 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.884      ;
+; -1.950 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.884      ;
+; -1.950 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.884      ;
+; -1.950 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.884      ;
+; -1.950 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.884      ;
+; -1.950 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.884      ;
+; -1.935 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[13] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.868      ;
+; -1.935 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[11] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.868      ;
+; -1.935 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[9]  ; clk          ; clk         ; 1.000        ; -0.062     ; 2.868      ;
+; -1.935 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[10] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.868      ;
+; -1.935 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[15] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.868      ;
+; -1.935 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[12] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.868      ;
+; -1.935 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[14] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.868      ;
+; -1.935 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[16] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.868      ;
+; -1.935 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[17] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.868      ;
+; -1.932 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.866      ;
+; -1.932 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.866      ;
+; -1.932 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.866      ;
+; -1.932 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.866      ;
+; -1.932 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.866      ;
+; -1.932 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.061     ; 2.866      ;
+; -1.925 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[1]  ; clk          ; clk         ; 1.000        ; 0.288      ; 3.208      ;
+; -1.925 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[0]  ; clk          ; clk         ; 1.000        ; 0.288      ; 3.208      ;
+; -1.925 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[7]  ; clk          ; clk         ; 1.000        ; 0.288      ; 3.208      ;
+; -1.921 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[13] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.854      ;
+; -1.921 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[11] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.854      ;
+; -1.921 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[9]  ; clk          ; clk         ; 1.000        ; -0.062     ; 2.854      ;
+; -1.921 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[10] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.854      ;
+; -1.921 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[15] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.854      ;
+; -1.921 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[12] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.854      ;
+; -1.921 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[14] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.854      ;
+; -1.921 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[16] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.854      ;
+; -1.921 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[17] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.854      ;
+; -1.911 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[1]  ; clk          ; clk         ; 1.000        ; 0.288      ; 3.194      ;
+; -1.911 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[0]  ; clk          ; clk         ; 1.000        ; 0.288      ; 3.194      ;
+; -1.911 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[7]  ; clk          ; clk         ; 1.000        ; 0.288      ; 3.194      ;
+; -1.881 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[13] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.814      ;
+; -1.881 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[11] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.814      ;
+; -1.881 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[9]  ; clk          ; clk         ; 1.000        ; -0.062     ; 2.814      ;
+; -1.881 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[10] ; clk          ; clk         ; 1.000        ; -0.062     ; 2.814      ;
++--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'hundred_hertz_clock:clockConv|clock_out'                                                                                                                  ;
++--------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock                            ; Latch Clock                             ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+; -1.787 ; counter:timeCount|c0[1] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.722      ;
+; -1.787 ; counter:timeCount|c0[1] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.722      ;
+; -1.787 ; counter:timeCount|c0[1] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.722      ;
+; -1.787 ; counter:timeCount|c0[1] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.722      ;
+; -1.741 ; counter:timeCount|c0[3] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.676      ;
+; -1.741 ; counter:timeCount|c0[3] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.676      ;
+; -1.741 ; counter:timeCount|c0[3] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.676      ;
+; -1.741 ; counter:timeCount|c0[3] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.676      ;
+; -1.738 ; counter:timeCount|c1[1] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.672      ;
+; -1.738 ; counter:timeCount|c1[1] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.672      ;
+; -1.738 ; counter:timeCount|c1[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.672      ;
+; -1.738 ; counter:timeCount|c1[1] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.672      ;
+; -1.714 ; counter:timeCount|c1[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.648      ;
+; -1.714 ; counter:timeCount|c1[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.648      ;
+; -1.714 ; counter:timeCount|c1[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.648      ;
+; -1.714 ; counter:timeCount|c1[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.648      ;
+; -1.687 ; counter:timeCount|en    ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.622      ;
+; -1.687 ; counter:timeCount|en    ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.622      ;
+; -1.687 ; counter:timeCount|en    ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.622      ;
+; -1.687 ; counter:timeCount|en    ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.622      ;
+; -1.621 ; counter:timeCount|c0[0] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.556      ;
+; -1.621 ; counter:timeCount|c0[0] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.556      ;
+; -1.621 ; counter:timeCount|c0[0] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.556      ;
+; -1.621 ; counter:timeCount|c0[0] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.556      ;
+; -1.619 ; counter:timeCount|c1[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.553      ;
+; -1.619 ; counter:timeCount|c1[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.553      ;
+; -1.619 ; counter:timeCount|c1[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.553      ;
+; -1.619 ; counter:timeCount|c1[3] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.553      ;
+; -1.596 ; counter:timeCount|c0[1] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.530      ;
+; -1.596 ; counter:timeCount|c0[1] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.530      ;
+; -1.596 ; counter:timeCount|c0[1] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.530      ;
+; -1.596 ; counter:timeCount|c0[1] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.530      ;
+; -1.588 ; counter:timeCount|c0[1] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.522      ;
+; -1.553 ; counter:timeCount|c0[3] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.487      ;
+; -1.552 ; counter:timeCount|c2[1] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.487      ;
+; -1.552 ; counter:timeCount|c2[1] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.487      ;
+; -1.552 ; counter:timeCount|c2[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.487      ;
+; -1.552 ; counter:timeCount|c2[1] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.487      ;
+; -1.526 ; counter:timeCount|c0[3] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.460      ;
+; -1.526 ; counter:timeCount|c0[3] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.460      ;
+; -1.526 ; counter:timeCount|c0[3] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.460      ;
+; -1.526 ; counter:timeCount|c0[3] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.460      ;
+; -1.520 ; counter:timeCount|c0[2] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.455      ;
+; -1.520 ; counter:timeCount|c0[2] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.455      ;
+; -1.520 ; counter:timeCount|c0[2] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.455      ;
+; -1.520 ; counter:timeCount|c0[2] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.455      ;
+; -1.507 ; counter:timeCount|c2[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.442      ;
+; -1.507 ; counter:timeCount|c2[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.442      ;
+; -1.507 ; counter:timeCount|c2[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.442      ;
+; -1.507 ; counter:timeCount|c2[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.442      ;
+; -1.501 ; counter:timeCount|c1[1] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.062     ; 2.434      ;
+; -1.501 ; counter:timeCount|c1[1] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.062     ; 2.434      ;
+; -1.501 ; counter:timeCount|c1[1] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.062     ; 2.434      ;
+; -1.501 ; counter:timeCount|c1[1] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.062     ; 2.434      ;
+; -1.495 ; counter:timeCount|c0[1] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.430      ;
+; -1.495 ; counter:timeCount|c0[1] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.430      ;
+; -1.495 ; counter:timeCount|c0[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.430      ;
+; -1.495 ; counter:timeCount|c0[1] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.430      ;
+; -1.478 ; counter:timeCount|c0[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.413      ;
+; -1.478 ; counter:timeCount|c0[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.413      ;
+; -1.478 ; counter:timeCount|c0[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.413      ;
+; -1.478 ; counter:timeCount|c0[3] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.413      ;
+; -1.477 ; counter:timeCount|c1[2] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.062     ; 2.410      ;
+; -1.477 ; counter:timeCount|c1[2] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.062     ; 2.410      ;
+; -1.477 ; counter:timeCount|c1[2] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.062     ; 2.410      ;
+; -1.477 ; counter:timeCount|c1[2] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.062     ; 2.410      ;
+; -1.459 ; counter:timeCount|en    ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.393      ;
+; -1.459 ; counter:timeCount|en    ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.393      ;
+; -1.459 ; counter:timeCount|en    ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.393      ;
+; -1.459 ; counter:timeCount|en    ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.393      ;
+; -1.453 ; counter:timeCount|c1[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.387      ;
+; -1.453 ; counter:timeCount|c1[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.387      ;
+; -1.453 ; counter:timeCount|c1[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.387      ;
+; -1.453 ; counter:timeCount|c1[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.387      ;
+; -1.433 ; counter:timeCount|c0[0] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.367      ;
+; -1.411 ; counter:timeCount|c1[3] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.062     ; 2.344      ;
+; -1.411 ; counter:timeCount|c1[3] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.062     ; 2.344      ;
+; -1.411 ; counter:timeCount|c1[3] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.062     ; 2.344      ;
+; -1.411 ; counter:timeCount|c1[3] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.062     ; 2.344      ;
+; -1.406 ; counter:timeCount|c0[0] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.340      ;
+; -1.406 ; counter:timeCount|c0[0] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.340      ;
+; -1.406 ; counter:timeCount|c0[0] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.340      ;
+; -1.406 ; counter:timeCount|c0[0] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.340      ;
+; -1.370 ; counter:timeCount|c2[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.305      ;
+; -1.370 ; counter:timeCount|c2[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.305      ;
+; -1.370 ; counter:timeCount|c2[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.305      ;
+; -1.370 ; counter:timeCount|c2[3] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.305      ;
+; -1.358 ; counter:timeCount|c0[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.293      ;
+; -1.358 ; counter:timeCount|c0[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.293      ;
+; -1.358 ; counter:timeCount|c0[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.293      ;
+; -1.358 ; counter:timeCount|c0[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.293      ;
+; -1.329 ; counter:timeCount|c0[2] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.263      ;
+; -1.329 ; counter:timeCount|c0[2] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.263      ;
+; -1.329 ; counter:timeCount|c0[2] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.263      ;
+; -1.329 ; counter:timeCount|c0[2] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.263      ;
+; -1.321 ; counter:timeCount|c0[2] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.255      ;
+; -1.287 ; counter:timeCount|c3[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.061     ; 2.221      ;
+; -1.267 ; counter:timeCount|c2[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.202      ;
+; -1.267 ; counter:timeCount|c2[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.202      ;
+; -1.267 ; counter:timeCount|c2[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.060     ; 2.202      ;
++--------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'button2'                                                                                                                               ;
++--------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                          ; Launch Clock                            ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; -1.727 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.467      ; 1.533      ;
+; -1.714 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.467      ; 1.520      ;
+; -1.492 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.467      ; 1.298      ;
+; -1.435 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.475      ; 1.421      ;
+; -1.419 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.467      ; 1.225      ;
+; -1.415 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.479      ; 1.404      ;
+; -1.341 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.465      ; 1.434      ;
+; -1.319 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.465      ; 1.413      ;
+; -1.308 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.465      ; 1.401      ;
+; -1.306 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.475      ; 1.292      ;
+; -1.298 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.563      ; 1.455      ;
+; -1.286 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.463      ; 1.383      ;
+; -1.282 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.465      ; 1.376      ;
+; -1.277 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.479      ; 1.266      ;
+; -1.275 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.463      ; 1.372      ;
+; -1.271 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.565      ; 1.435      ;
+; -1.268 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.563      ; 1.425      ;
+; -1.257 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.462      ; 1.352      ;
+; -1.254 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.463      ; 1.351      ;
+; -1.249 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.469      ; 1.429      ;
+; -1.247 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.462      ; 1.342      ;
+; -1.245 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.463      ; 1.342      ;
+; -1.242 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.463      ; 1.339      ;
+; -1.234 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.469      ; 1.410      ;
+; -1.225 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.469      ; 1.401      ;
+; -1.223 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.469      ; 1.403      ;
+; -1.217 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.469      ; 1.397      ;
+; -1.215 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.495      ; 1.421      ;
+; -1.214 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.565      ; 1.378      ;
+; -1.212 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.465      ; 1.386      ;
+; -1.209 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.496      ; 1.416      ;
+; -1.209 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.463      ; 1.306      ;
+; -1.197 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.494      ; 1.399      ;
+; -1.196 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.469      ; 1.376      ;
+; -1.196 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.465      ; 1.370      ;
+; -1.192 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.561      ; 1.354      ;
+; -1.191 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.453      ; 1.423      ;
+; -1.190 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.563      ; 1.347      ;
+; -1.189 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.495      ; 1.395      ;
+; -1.188 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.496      ; 1.395      ;
+; -1.187 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.465      ; 1.280      ;
+; -1.185 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.449      ; 1.412      ;
+; -1.183 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.494      ; 1.385      ;
+; -1.177 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.449      ; 1.404      ;
+; -1.170 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.484      ; 1.404      ;
+; -1.155 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.561      ; 1.317      ;
+; -1.154 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.496      ; 1.361      ;
+; -1.152 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.495      ; 1.358      ;
+; -1.146 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.453      ; 1.378      ;
+; -1.145 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.465      ; 1.239      ;
+; -1.136 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.475      ; 1.122      ;
+; -1.134 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.479      ; 1.123      ;
+; -1.122 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.560      ; 1.283      ;
+; -1.122 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.463      ; 1.219      ;
+; -1.122 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.462      ; 1.217      ;
+; -1.122 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.463      ; 1.219      ;
+; -1.119 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.560      ; 1.280      ;
+; -1.114 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.484      ; 1.348      ;
+; -1.108 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.475      ; 1.094      ;
+; -1.105 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.540      ; 1.397      ;
+; -1.105 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.479      ; 1.094      ;
+; -1.104 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.506      ; 1.384      ;
+; -1.098 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.506      ; 1.378      ;
+; -1.098 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.540      ; 1.390      ;
+; -1.096 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.463      ; 1.193      ;
+; -1.091 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.505      ; 1.369      ;
+; -1.091 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.497      ; 1.460      ;
+; -1.086 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.563      ; 1.525      ;
+; -1.083 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.497      ; 1.452      ;
+; -1.083 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.505      ; 1.361      ;
+; -1.077 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.563      ; 1.516      ;
+; -1.067 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.563      ; 1.224      ;
+; -1.065 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.565      ; 1.229      ;
+; -1.058 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.465      ; 1.232      ;
+; -1.045 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.561      ; 1.207      ;
+; -1.026 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.465      ; 1.119      ;
+; -1.023 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.469      ; 1.199      ;
+; -1.021 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.469      ; 1.201      ;
+; -1.018 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.469      ; 1.198      ;
+; -1.017 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.462      ; 1.112      ;
+; -1.016 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.463      ; 1.113      ;
+; -1.013 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.465      ; 1.107      ;
+; -1.013 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.463      ; 1.110      ;
+; -1.008 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.505      ; 1.286      ;
+; -1.003 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.463      ; 1.100      ;
+; -0.998 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.506      ; 1.278      ;
+; -0.989 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.494      ; 1.191      ;
+; -0.988 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.497      ; 1.357      ;
+; -0.987 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.484      ; 1.221      ;
+; -0.976 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.540      ; 1.268      ;
+; -0.965 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.449      ; 1.192      ;
+; -0.959 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.560      ; 1.120      ;
+; -0.955 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.453      ; 1.187      ;
+; -0.941 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.565      ; 1.105      ;
+; -0.937 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.561      ; 1.099      ;
+; -0.933 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.469      ; 1.113      ;
+; -0.931 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.469      ; 1.111      ;
+; -0.927 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.495      ; 1.133      ;
+; -0.927 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.465      ; 1.101      ;
+; -0.920 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.469      ; 1.096      ;
++--------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'clk'                                                                                                                                                           ;
++--------+-----------------------------------------+-----------------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                               ; To Node                                 ; Launch Clock                            ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------------------------------------+-----------------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; -0.504 ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; clk         ; 0.000        ; 2.749      ; 2.631      ;
+; 0.080  ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; clk         ; -0.500       ; 2.749      ; 2.715      ;
+; 0.344  ; hundred_hertz_clock:clockConv|start     ; hundred_hertz_clock:clockConv|start     ; clk                                     ; clk         ; 0.000        ; 0.076      ; 0.577      ;
+; 0.379  ; hundred_hertz_clock:clockConv|ctr[17]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 0.598      ;
+; 0.482  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.425      ; 1.064      ;
+; 0.545  ; hundred_hertz_clock:clockConv|ctr[1]    ; hundred_hertz_clock:clockConv|ctr[1]    ; clk                                     ; clk         ; 0.000        ; 0.076      ; 0.778      ;
+; 0.545  ; hundred_hertz_clock:clockConv|ctr[7]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.076      ; 0.778      ;
+; 0.558  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 0.776      ;
+; 0.558  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 0.776      ;
+; 0.558  ; hundred_hertz_clock:clockConv|ctr[15]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 0.777      ;
+; 0.558  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 0.777      ;
+; 0.559  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[4]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 0.777      ;
+; 0.559  ; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 0.778      ;
+; 0.560  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 0.779      ;
+; 0.563  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[2]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 0.781      ;
+; 0.563  ; hundred_hertz_clock:clockConv|ctr[16]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 0.782      ;
+; 0.568  ; hundred_hertz_clock:clockConv|ctr[0]    ; hundred_hertz_clock:clockConv|ctr[0]    ; clk                                     ; clk         ; 0.000        ; 0.076      ; 0.801      ;
+; 0.570  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.062      ; 0.789      ;
+; 0.571  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 0.790      ;
+; 0.572  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 0.791      ;
+; 0.573  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[3]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 0.791      ;
+; 0.595  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.425      ; 1.177      ;
+; 0.705  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.425      ; 1.287      ;
+; 0.708  ; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|ctr[5]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 0.926      ;
+; 0.710  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.425      ; 1.292      ;
+; 0.729  ; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.425      ; 1.311      ;
+; 0.833  ; hundred_hertz_clock:clockConv|ctr[15]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.052      ;
+; 0.834  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.053      ;
+; 0.835  ; hundred_hertz_clock:clockConv|ctr[0]    ; hundred_hertz_clock:clockConv|ctr[1]    ; clk                                     ; clk         ; 0.000        ; 0.076      ; 1.068      ;
+; 0.840  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; clk         ; 0.000        ; 0.426      ; 1.423      ;
+; 0.844  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.063      ;
+; 0.845  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.064      ;
+; 0.846  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.065      ;
+; 0.846  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.064      ;
+; 0.847  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[4]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.065      ;
+; 0.847  ; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.066      ;
+; 0.847  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[5]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.065      ;
+; 0.848  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.066      ;
+; 0.848  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.067      ;
+; 0.848  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.066      ;
+; 0.849  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.067      ;
+; 0.849  ; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.068      ;
+; 0.850  ; hundred_hertz_clock:clockConv|ctr[16]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.069      ;
+; 0.850  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[3]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.068      ;
+; 0.852  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[4]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.070      ;
+; 0.859  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.078      ;
+; 0.861  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.080      ;
+; 0.870  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; clk         ; 0.000        ; 0.426      ; 1.453      ;
+; 0.876  ; hundred_hertz_clock:clockConv|start     ; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; clk         ; 0.000        ; 0.076      ; 1.109      ;
+; 0.943  ; hundred_hertz_clock:clockConv|ctr[15]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.162      ;
+; 0.944  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.163      ;
+; 0.946  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.165      ;
+; 0.954  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.173      ;
+; 0.955  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.174      ;
+; 0.956  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.175      ;
+; 0.957  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[5]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.175      ;
+; 0.957  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.176      ;
+; 0.958  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.176      ;
+; 0.958  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.177      ;
+; 0.958  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.176      ;
+; 0.959  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.177      ;
+; 0.959  ; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.178      ;
+; 0.960  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.178      ;
+; 0.960  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.179      ;
+; 0.960  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.178      ;
+; 0.961  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.179      ;
+; 0.962  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[5]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.180      ;
+; 0.964  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.182      ;
+; 0.971  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.190      ;
+; 0.973  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.192      ;
+; 0.983  ; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.201      ;
+; 1.056  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.275      ;
+; 1.066  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.285      ;
+; 1.067  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.286      ;
+; 1.068  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.287      ;
+; 1.069  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.288      ;
+; 1.070  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.288      ;
+; 1.070  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.289      ;
+; 1.070  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.288      ;
+; 1.071  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.289      ;
+; 1.071  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.289      ;
+; 1.072  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.290      ;
+; 1.072  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.290      ;
+; 1.073  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.291      ;
+; 1.076  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.294      ;
+; 1.083  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.302      ;
+; 1.085  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.304      ;
+; 1.095  ; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.313      ;
+; 1.153  ; hundred_hertz_clock:clockConv|ctr[1]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.076      ; 1.386      ;
+; 1.166  ; hundred_hertz_clock:clockConv|ctr[15]   ; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; clk         ; 0.000        ; 0.426      ; 1.749      ;
+; 1.171  ; hundred_hertz_clock:clockConv|ctr[0]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.076      ; 1.404      ;
+; 1.178  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.397      ;
+; 1.179  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.398      ;
+; 1.180  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.062      ; 1.399      ;
+; 1.181  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.399      ;
+; 1.182  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.400      ;
+; 1.182  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.400      ;
+; 1.183  ; hundred_hertz_clock:clockConv|ctr[1]    ; hundred_hertz_clock:clockConv|ctr[2]    ; clk                                     ; clk         ; 0.000        ; -0.288     ; 1.052      ;
+; 1.183  ; hundred_hertz_clock:clockConv|ctr[7]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; -0.288     ; 1.052      ;
+; 1.183  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.061      ; 1.401      ;
++--------+-----------------------------------------+-----------------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'hundred_hertz_clock:clockConv|clock_out'                                                                                                                  ;
++-------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                 ; Launch Clock                            ; Latch Clock                             ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+; 0.359 ; counter:timeCount|c3[1] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; counter:timeCount|c2[1] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; counter:timeCount|c1[1] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; counter:timeCount|c0[1] ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; counter:timeCount|c0[2] ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; counter:timeCount|c0[3] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.577      ;
+; 0.362 ; counter:timeCount|c3[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.580      ;
+; 0.362 ; counter:timeCount|c2[0] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.580      ;
+; 0.362 ; counter:timeCount|c1[0] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.580      ;
+; 0.362 ; counter:timeCount|c0[0] ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.580      ;
+; 0.636 ; counter:timeCount|c3[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.854      ;
+; 0.683 ; counter:timeCount|c2[0] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.901      ;
+; 0.744 ; counter:timeCount|c0[2] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.962      ;
+; 0.778 ; counter:timeCount|c0[0] ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 0.996      ;
+; 0.794 ; counter:timeCount|c1[0] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.012      ;
+; 0.807 ; counter:timeCount|c0[2] ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.025      ;
+; 0.838 ; counter:timeCount|en    ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.056      ;
+; 0.842 ; counter:timeCount|en    ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.060      ;
+; 0.843 ; counter:timeCount|en    ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.061      ;
+; 0.964 ; counter:timeCount|c2[2] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.182      ;
+; 1.008 ; counter:timeCount|c0[3] ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.226      ;
+; 1.012 ; counter:timeCount|c1[2] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.230      ;
+; 1.034 ; counter:timeCount|c2[2] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.252      ;
+; 1.037 ; counter:timeCount|c3[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.255      ;
+; 1.038 ; counter:timeCount|c2[2] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.256      ;
+; 1.041 ; counter:timeCount|c3[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.259      ;
+; 1.041 ; counter:timeCount|c3[3] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.259      ;
+; 1.045 ; counter:timeCount|en    ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.263      ;
+; 1.050 ; counter:timeCount|c2[2] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.268      ;
+; 1.055 ; counter:timeCount|c0[2] ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.273      ;
+; 1.065 ; counter:timeCount|c2[3] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.283      ;
+; 1.098 ; counter:timeCount|c0[1] ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.316      ;
+; 1.099 ; counter:timeCount|c2[3] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.317      ;
+; 1.102 ; counter:timeCount|c2[3] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.320      ;
+; 1.103 ; counter:timeCount|c1[0] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.321      ;
+; 1.107 ; counter:timeCount|c1[0] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.325      ;
+; 1.118 ; counter:timeCount|en    ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 1.337      ;
+; 1.123 ; counter:timeCount|en    ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 1.342      ;
+; 1.129 ; counter:timeCount|c2[3] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.347      ;
+; 1.147 ; counter:timeCount|c2[1] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.365      ;
+; 1.155 ; counter:timeCount|en    ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.373      ;
+; 1.159 ; counter:timeCount|c2[0] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.377      ;
+; 1.160 ; counter:timeCount|c3[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.378      ;
+; 1.182 ; counter:timeCount|c0[0] ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.400      ;
+; 1.192 ; counter:timeCount|c1[2] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.410      ;
+; 1.210 ; counter:timeCount|c1[3] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.428      ;
+; 1.216 ; counter:timeCount|en    ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.434      ;
+; 1.222 ; counter:timeCount|c3[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.440      ;
+; 1.223 ; counter:timeCount|c3[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.441      ;
+; 1.223 ; counter:timeCount|c3[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.441      ;
+; 1.225 ; counter:timeCount|en    ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 1.444      ;
+; 1.226 ; counter:timeCount|c1[3] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.444      ;
+; 1.229 ; counter:timeCount|en    ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 1.448      ;
+; 1.230 ; counter:timeCount|c1[3] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.448      ;
+; 1.230 ; counter:timeCount|c1[3] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.448      ;
+; 1.243 ; counter:timeCount|c2[0] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.461      ;
+; 1.269 ; counter:timeCount|c3[1] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.487      ;
+; 1.270 ; counter:timeCount|c3[1] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.488      ;
+; 1.271 ; counter:timeCount|c0[3] ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.489      ;
+; 1.293 ; counter:timeCount|c0[1] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.511      ;
+; 1.300 ; counter:timeCount|c1[1] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.518      ;
+; 1.306 ; counter:timeCount|c2[1] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.524      ;
+; 1.306 ; counter:timeCount|c0[1] ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.524      ;
+; 1.314 ; counter:timeCount|en    ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 1.533      ;
+; 1.318 ; counter:timeCount|c2[1] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.536      ;
+; 1.323 ; counter:timeCount|c1[1] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.541      ;
+; 1.343 ; counter:timeCount|c1[2] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.561      ;
+; 1.346 ; counter:timeCount|en    ; counter:timeCount|en    ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.564      ;
+; 1.347 ; counter:timeCount|c1[2] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.565      ;
+; 1.357 ; counter:timeCount|c1[1] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.575      ;
+; 1.377 ; counter:timeCount|c0[0] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.595      ;
+; 1.385 ; counter:timeCount|c0[3] ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.603      ;
+; 1.412 ; counter:timeCount|en    ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 1.631      ;
+; 1.422 ; counter:timeCount|en    ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 1.641      ;
+; 1.429 ; counter:timeCount|en    ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.647      ;
+; 1.458 ; counter:timeCount|c3[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.676      ;
+; 1.471 ; counter:timeCount|en    ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.689      ;
+; 1.519 ; counter:timeCount|c3[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.737      ;
+; 1.577 ; counter:timeCount|c3[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.795      ;
+; 1.676 ; counter:timeCount|c3[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 1.894      ;
+; 1.896 ; counter:timeCount|c1[0] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.060      ; 2.113      ;
+; 1.896 ; counter:timeCount|c1[0] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.060      ; 2.113      ;
+; 1.896 ; counter:timeCount|c1[0] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.060      ; 2.113      ;
+; 1.896 ; counter:timeCount|c1[0] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.060      ; 2.113      ;
+; 1.913 ; counter:timeCount|c2[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 2.132      ;
+; 1.913 ; counter:timeCount|c2[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 2.132      ;
+; 1.913 ; counter:timeCount|c2[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 2.132      ;
+; 1.913 ; counter:timeCount|c2[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 2.132      ;
+; 1.916 ; counter:timeCount|c0[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 2.135      ;
+; 1.916 ; counter:timeCount|c0[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 2.135      ;
+; 1.916 ; counter:timeCount|c0[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 2.135      ;
+; 1.916 ; counter:timeCount|c0[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 2.135      ;
+; 1.962 ; counter:timeCount|c0[2] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 2.180      ;
+; 1.962 ; counter:timeCount|c0[2] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 2.180      ;
+; 1.962 ; counter:timeCount|c0[2] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 2.180      ;
+; 1.962 ; counter:timeCount|c0[2] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.061      ; 2.180      ;
+; 1.985 ; counter:timeCount|c0[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 2.204      ;
+; 1.985 ; counter:timeCount|c0[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 2.204      ;
+; 1.985 ; counter:timeCount|c0[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 2.204      ;
+; 1.985 ; counter:timeCount|c0[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.062      ; 2.204      ;
++-------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'button2'                                                                                                                               ;
++-------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                          ; Launch Clock                            ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; 0.615 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.751      ; 0.896      ;
+; 0.702 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.747      ; 0.979      ;
+; 0.707 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.751      ; 0.988      ;
+; 0.712 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.756      ; 0.998      ;
+; 0.721 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.722      ; 0.973      ;
+; 0.723 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.723      ; 0.976      ;
+; 0.724 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.752      ; 1.006      ;
+; 0.748 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.691      ; 0.969      ;
+; 0.779 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.688      ; 0.997      ;
+; 0.779 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.683      ; 0.992      ;
+; 0.784 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.683      ; 0.997      ;
+; 0.786 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.663      ; 0.979      ;
+; 0.786 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.688      ; 1.004      ;
+; 0.788 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.677      ; 0.995      ;
+; 0.789 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.683      ; 1.002      ;
+; 0.790 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.754      ; 1.074      ;
+; 0.791 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.683      ; 1.004      ;
+; 0.796 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.656      ; 0.982      ;
+; 0.797 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.657      ; 0.984      ;
+; 0.805 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.684      ; 1.019      ;
+; 0.807 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.752      ; 1.089      ;
+; 0.808 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.751      ; 1.089      ;
+; 0.811 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.652      ; 0.993      ;
+; 0.812 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.013      ;
+; 0.812 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.670      ; 1.012      ;
+; 0.814 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.659      ; 1.003      ;
+; 0.814 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.751      ; 1.095      ;
+; 0.816 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.017      ;
+; 0.818 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.019      ;
+; 0.818 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.677      ; 1.025      ;
+; 0.820 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.656      ; 1.006      ;
+; 0.827 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.747      ; 1.104      ;
+; 0.842 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.756      ; 1.128      ;
+; 0.848 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.691      ; 1.069      ;
+; 0.858 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.754      ; 1.142      ;
+; 0.859 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.723      ; 1.112      ;
+; 0.862 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.685      ; 1.077      ;
+; 0.864 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.722      ; 1.116      ;
+; 0.879 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.655      ; 1.064      ;
+; 0.882 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.683      ; 1.095      ;
+; 0.887 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.747      ; 1.164      ;
+; 0.887 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.688      ; 1.105      ;
+; 0.892 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.754      ; 1.176      ;
+; 0.898 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.747      ; 1.175      ;
+; 0.899 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.652      ; 1.081      ;
+; 0.904 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.752      ; 1.186      ;
+; 0.904 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.105      ;
+; 0.904 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.105      ;
+; 0.905 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.663      ; 1.098      ;
+; 0.905 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.106      ;
+; 0.907 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.670      ; 1.107      ;
+; 0.914 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.659      ; 1.103      ;
+; 0.916 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.683      ; 1.129      ;
+; 0.921 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.756      ; 1.207      ;
+; 0.922 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.656      ; 1.108      ;
+; 0.923 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.656      ; 1.109      ;
+; 0.924 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.677      ; 1.131      ;
+; 0.924 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.657      ; 1.111      ;
+; 0.928 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.754      ; 1.212      ;
+; 0.928 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.677      ; 1.135      ;
+; 0.934 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.723      ; 1.187      ;
+; 0.942 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.752      ; 1.224      ;
+; 0.952 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.685      ; 1.167      ;
+; 0.957 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.754      ; 1.241      ;
+; 0.960 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.683      ; 1.173      ;
+; 0.964 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.754      ; 1.248      ;
+; 0.966 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.722      ; 1.218      ;
+; 0.970 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.722      ; 1.222      ;
+; 0.976 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.659      ; 1.165      ;
+; 0.976 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.656      ; 1.162      ;
+; 0.977 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.691      ; 1.198      ;
+; 0.977 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.657      ; 1.164      ;
+; 0.979 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.663      ; 1.172      ;
+; 0.980 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.756      ; 1.266      ;
+; 0.981 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.182      ;
+; 0.982 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.656      ; 1.168      ;
+; 0.983 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.723      ; 1.236      ;
+; 0.983 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.683      ; 1.196      ;
+; 0.984 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.657      ; 1.171      ;
+; 0.985 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.652      ; 1.167      ;
+; 0.987 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.659      ; 1.176      ;
+; 0.988 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.652      ; 1.170      ;
+; 0.990 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.656      ; 1.176      ;
+; 0.991 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.684      ; 1.205      ;
+; 0.995 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.684      ; 1.209      ;
+; 0.996 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.683      ; 1.209      ;
+; 0.996 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.197      ;
+; 0.996 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.197      ;
+; 0.997 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.198      ;
+; 0.998 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.691      ; 1.219      ;
+; 0.999 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.754      ; 1.283      ;
+; 0.999 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.754      ; 1.283      ;
+; 0.999 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.655      ; 1.184      ;
+; 1.004 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.205      ;
+; 1.007 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.683      ; 1.220      ;
+; 1.007 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.670      ; 1.207      ;
+; 1.009 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.670      ; 1.209      ;
+; 1.011 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.677      ; 1.218      ;
+; 1.011 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.684      ; 1.225      ;
+; 1.012 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.677      ; 1.219      ;
++-------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'clk'                                                                         ;
++--------+--------------+----------------+------------------+-------+------------+-----------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                  ;
++--------+--------------+----------------+------------------+-------+------------+-----------------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; clk   ; Rise       ; clk                                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[0]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[10]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[11]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[12]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[13]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[14]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[15]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[16]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[17]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[1]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[2]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[3]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[4]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[5]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[6]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[7]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[8]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[9]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|start     ;
+; 0.168  ; 0.352        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; 0.168  ; 0.352        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|start     ;
+; 0.169  ; 0.353        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[0]    ;
+; 0.169  ; 0.353        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[1]    ;
+; 0.169  ; 0.353        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[7]    ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[10]   ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[11]   ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[12]   ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[13]   ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[14]   ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[15]   ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[16]   ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[17]   ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[2]    ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[3]    ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[4]    ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[5]    ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[6]    ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[8]    ;
+; 0.189  ; 0.373        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[9]    ;
+; 0.330  ; 0.330        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|clock_out|clk                 ;
+; 0.330  ; 0.330        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|start|clk                     ;
+; 0.331  ; 0.331        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[0]|clk                    ;
+; 0.331  ; 0.331        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[1]|clk                    ;
+; 0.331  ; 0.331        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[7]|clk                    ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|o                             ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[10]|clk                   ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[11]|clk                   ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[12]|clk                   ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[13]|clk                   ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[14]|clk                   ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[15]|clk                   ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[16]|clk                   ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[17]|clk                   ;
+; 0.350  ; 0.350        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[9]|clk                    ;
+; 0.351  ; 0.351        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[2]|clk                    ;
+; 0.351  ; 0.351        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[3]|clk                    ;
+; 0.351  ; 0.351        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[4]|clk                    ;
+; 0.351  ; 0.351        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[5]|clk                    ;
+; 0.351  ; 0.351        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[6]|clk                    ;
+; 0.351  ; 0.351        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[8]|clk                    ;
+; 0.356  ; 0.356        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~inputclkctrl|inclk[0]               ;
+; 0.356  ; 0.356        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~inputclkctrl|outclk                 ;
+; 0.409  ; 0.625        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[2]    ;
+; 0.409  ; 0.625        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[3]    ;
+; 0.409  ; 0.625        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[4]    ;
+; 0.409  ; 0.625        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[5]    ;
+; 0.409  ; 0.625        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[6]    ;
+; 0.409  ; 0.625        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[8]    ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[10]   ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[11]   ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[12]   ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[13]   ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[14]   ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[15]   ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[16]   ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[17]   ;
+; 0.410  ; 0.626        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[9]    ;
+; 0.429  ; 0.645        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[0]    ;
+; 0.429  ; 0.645        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[1]    ;
+; 0.429  ; 0.645        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[7]    ;
+; 0.430  ; 0.646        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; 0.430  ; 0.646        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|start     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|i                             ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|i                             ;
+; 0.643  ; 0.643        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~inputclkctrl|inclk[0]               ;
+; 0.643  ; 0.643        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~inputclkctrl|outclk                 ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[10]|clk                   ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[11]|clk                   ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[12]|clk                   ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[13]|clk                   ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[14]|clk                   ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[15]|clk                   ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[16]|clk                   ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[17]|clk                   ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[2]|clk                    ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[3]|clk                    ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[4]|clk                    ;
+; 0.649  ; 0.649        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[5]|clk                    ;
++--------+--------------+----------------+------------------+-------+------------+-----------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'button2'                                                                ;
++--------+--------------+----------------+------------------+---------+------------+----------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                           ;
++--------+--------------+----------------+------------------+---------+------------+----------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; button2 ; Rise       ; button2                          ;
+; 0.231  ; 0.231        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[6] ;
+; 0.233  ; 0.233        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[6] ;
+; 0.244  ; 0.244        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[1] ;
+; 0.244  ; 0.244        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[4] ;
+; 0.245  ; 0.245        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[0] ;
+; 0.245  ; 0.245        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[5] ;
+; 0.245  ; 0.245        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[6]|datab                ;
+; 0.246  ; 0.246        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[6]|dataa                ;
+; 0.249  ; 0.249        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[4] ;
+; 0.249  ; 0.249        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[4]|dataa                ;
+; 0.249  ; 0.249        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[4]|datab                ;
+; 0.250  ; 0.250        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[5] ;
+; 0.250  ; 0.250        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[0]|dataa                ;
+; 0.250  ; 0.250        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[1]|dataa                ;
+; 0.250  ; 0.250        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[5]|datab                ;
+; 0.251  ; 0.251        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[5]|dataa                ;
+; 0.252  ; 0.252        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[2] ;
+; 0.252  ; 0.252        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[3] ;
+; 0.257  ; 0.257        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[2] ;
+; 0.258  ; 0.258        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[0] ;
+; 0.258  ; 0.258        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[3] ;
+; 0.259  ; 0.259        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[1] ;
+; 0.259  ; 0.259        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[2]|datab                ;
+; 0.259  ; 0.259        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[3]|datab                ;
+; 0.259  ; 0.259        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[3]|datad                ;
+; 0.259  ; 0.259        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[4]|datad                ;
+; 0.259  ; 0.259        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[5]|datad                ;
+; 0.260  ; 0.260        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[1]|datad                ;
+; 0.262  ; 0.262        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[2]|dataa                ;
+; 0.263  ; 0.263        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[0]|dataa                ;
+; 0.263  ; 0.263        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[3]|dataa                ;
+; 0.263  ; 0.263        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[6]|datad                ;
+; 0.264  ; 0.264        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[1]|dataa                ;
+; 0.270  ; 0.270        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[4] ;
+; 0.270  ; 0.270        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[3]|datad                ;
+; 0.271  ; 0.271        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[2]|datad                ;
+; 0.271  ; 0.271        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[4]|datac                ;
+; 0.273  ; 0.273        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[1]|datad                ;
+; 0.273  ; 0.273        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[0]|datac                ;
+; 0.274  ; 0.274        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[6]|datad                ;
+; 0.275  ; 0.275        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[0] ;
+; 0.276  ; 0.276        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[2] ;
+; 0.277  ; 0.277        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[2]|datac                ;
+; 0.279  ; 0.279        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[5] ;
+; 0.279  ; 0.279        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[3] ;
+; 0.279  ; 0.279        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[4] ;
+; 0.279  ; 0.279        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[5] ;
+; 0.280  ; 0.280        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[1] ;
+; 0.280  ; 0.280        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[5]|datac                ;
+; 0.281  ; 0.281        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[0] ;
+; 0.282  ; 0.282        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[0]|datac                ;
+; 0.283  ; 0.283        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[6] ;
+; 0.290  ; 0.290        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[3] ;
+; 0.291  ; 0.291        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[2] ;
+; 0.293  ; 0.293        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[1] ;
+; 0.294  ; 0.294        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[6] ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; button2~input|o                  ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; button2~input|i                  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; button2~input|i                  ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; button2~input|o                  ;
+; 0.705  ; 0.705        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[6] ;
+; 0.707  ; 0.707        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[1] ;
+; 0.709  ; 0.709        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[2] ;
+; 0.710  ; 0.710        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[3] ;
+; 0.716  ; 0.716        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[6] ;
+; 0.718  ; 0.718        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[1] ;
+; 0.718  ; 0.718        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[0]|datac                ;
+; 0.719  ; 0.719        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[0] ;
+; 0.720  ; 0.720        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[3] ;
+; 0.720  ; 0.720        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[4] ;
+; 0.720  ; 0.720        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[5] ;
+; 0.720  ; 0.720        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[5]|datac                ;
+; 0.721  ; 0.721        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[5] ;
+; 0.723  ; 0.723        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss3|out[2]|datac                ;
+; 0.724  ; 0.724        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[2] ;
+; 0.725  ; 0.725        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[0] ;
+; 0.725  ; 0.725        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[6]|datad                ;
+; 0.727  ; 0.727        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[1]|datad                ;
+; 0.727  ; 0.727        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss3|out[0]|datac                ;
+; 0.728  ; 0.728        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[4]|datac                ;
+; 0.729  ; 0.729        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[4] ;
+; 0.729  ; 0.729        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[2]|datad                ;
+; 0.730  ; 0.730        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[3]|datad                ;
+; 0.734  ; 0.734        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[2] ;
+; 0.735  ; 0.735        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[3] ;
+; 0.735  ; 0.735        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[1] ;
+; 0.735  ; 0.735        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[3] ;
+; 0.735  ; 0.735        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[5] ;
+; 0.736  ; 0.736        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[0] ;
+; 0.736  ; 0.736        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[2] ;
+; 0.736  ; 0.736        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[1]|dataa                ;
+; 0.736  ; 0.736        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[3]|dataa                ;
+; 0.736  ; 0.736        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss3|out[6]|datad                ;
+; 0.737  ; 0.737        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[4] ;
+; 0.737  ; 0.737        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[0]|dataa                ;
+; 0.737  ; 0.737        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[2]|dataa                ;
+; 0.738  ; 0.738        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss3|out[1]|datad                ;
+; 0.739  ; 0.739        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[5] ;
+; 0.740  ; 0.740        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[1] ;
++--------+--------------+----------------+------------------+---------+------------+----------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'hundred_hertz_clock:clockConv|clock_out'                                                                    ;
++--------+--------------+----------------+------------------+-----------------------------------------+------------+--------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                   ; Clock Edge ; Target                               ;
++--------+--------------+----------------+------------------+-----------------------------------------+------------+--------------------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|en                 ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[0]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[1]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[2]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[3]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[0]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[1]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[2]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[3]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[0]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[1]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[2]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[3]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[0]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[1]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[2]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[3]              ;
+; 0.285  ; 0.469        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|en                 ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[0]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[1]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[2]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[3]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[0]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[1]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[2]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[3]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[0]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[1]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[2]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[3]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[0]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[1]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[2]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[3]              ;
+; 0.311  ; 0.527        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|en                 ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[0]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[1]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[2]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[3]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[0]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[1]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[2]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[3]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[0]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[1]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[2]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[3]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[0]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[1]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[2]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[3]|clk                  ;
+; 0.447  ; 0.447        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|en|clk                     ;
+; 0.454  ; 0.454        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out~clkctrl|inclk[0] ;
+; 0.454  ; 0.454        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out~clkctrl|outclk   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out|q                ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out|q                ;
+; 0.544  ; 0.544        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out~clkctrl|inclk[0] ;
+; 0.544  ; 0.544        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out~clkctrl|outclk   ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[0]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[1]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[2]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[3]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[0]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[1]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[2]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[3]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[0]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[1]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[2]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[3]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[0]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[1]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[2]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[3]|clk                  ;
+; 0.551  ; 0.551        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|en|clk                     ;
++--------+--------------+----------------+------------------+-----------------------------------------+------------+--------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                                ;
++-----------+-----------------------------------------+-------+-------+------------+-----------------------------------------+
+; Data Port ; Clock Port                              ; Rise  ; Fall  ; Clock Edge ; Clock Reference                         ;
++-----------+-----------------------------------------+-------+-------+------------+-----------------------------------------+
+; button1   ; clk                                     ; 3.367 ; 3.857 ; Rise       ; clk                                     ;
+; button0   ; hundred_hertz_clock:clockConv|clock_out ; 4.454 ; 4.869 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; button1   ; hundred_hertz_clock:clockConv|clock_out ; 3.955 ; 4.458 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
++-----------+-----------------------------------------+-------+-------+------------+-----------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                                   ;
++-----------+-----------------------------------------+--------+--------+------------+-----------------------------------------+
+; Data Port ; Clock Port                              ; Rise   ; Fall   ; Clock Edge ; Clock Reference                         ;
++-----------+-----------------------------------------+--------+--------+------------+-----------------------------------------+
+; button1   ; clk                                     ; -1.437 ; -1.894 ; Rise       ; clk                                     ;
+; button0   ; hundred_hertz_clock:clockConv|clock_out ; -2.542 ; -2.946 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; button1   ; hundred_hertz_clock:clockConv|clock_out ; -2.140 ; -2.619 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
++-----------+-----------------------------------------+--------+--------+------------+-----------------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; hex0[*]   ; button2    ; 5.900 ; 5.818 ; Fall       ; button2         ;
+;  hex0[0]  ; button2    ; 5.877 ; 5.812 ; Fall       ; button2         ;
+;  hex0[1]  ; button2    ; 5.900 ; 5.818 ; Fall       ; button2         ;
+;  hex0[2]  ; button2    ; 5.389 ; 5.322 ; Fall       ; button2         ;
+;  hex0[3]  ; button2    ; 5.379 ; 5.314 ; Fall       ; button2         ;
+;  hex0[4]  ; button2    ; 5.655 ; 5.589 ; Fall       ; button2         ;
+;  hex0[5]  ; button2    ; 5.427 ; 5.364 ; Fall       ; button2         ;
+;  hex0[6]  ; button2    ; 5.579 ; 5.511 ; Fall       ; button2         ;
+; hex1[*]   ; button2    ; 5.927 ; 5.863 ; Fall       ; button2         ;
+;  hex1[0]  ; button2    ; 5.663 ; 5.606 ; Fall       ; button2         ;
+;  hex1[1]  ; button2    ; 5.736 ; 5.676 ; Fall       ; button2         ;
+;  hex1[2]  ; button2    ; 5.659 ; 5.601 ; Fall       ; button2         ;
+;  hex1[3]  ; button2    ; 5.673 ; 5.603 ; Fall       ; button2         ;
+;  hex1[4]  ; button2    ; 5.927 ; 5.863 ; Fall       ; button2         ;
+;  hex1[5]  ; button2    ; 5.688 ; 5.621 ; Fall       ; button2         ;
+;  hex1[6]  ; button2    ; 5.697 ; 5.635 ; Fall       ; button2         ;
+; hex2[*]   ; button2    ; 6.018 ; 5.928 ; Fall       ; button2         ;
+;  hex2[0]  ; button2    ; 5.595 ; 5.525 ; Fall       ; button2         ;
+;  hex2[1]  ; button2    ; 5.535 ; 5.506 ; Fall       ; button2         ;
+;  hex2[2]  ; button2    ; 5.387 ; 5.330 ; Fall       ; button2         ;
+;  hex2[3]  ; button2    ; 5.615 ; 5.551 ; Fall       ; button2         ;
+;  hex2[4]  ; button2    ; 5.599 ; 5.534 ; Fall       ; button2         ;
+;  hex2[5]  ; button2    ; 5.640 ; 5.575 ; Fall       ; button2         ;
+;  hex2[6]  ; button2    ; 6.018 ; 5.928 ; Fall       ; button2         ;
+; hex3[*]   ; button2    ; 6.130 ; 6.027 ; Fall       ; button2         ;
+;  hex3[0]  ; button2    ; 5.862 ; 5.774 ; Fall       ; button2         ;
+;  hex3[1]  ; button2    ; 6.130 ; 6.027 ; Fall       ; button2         ;
+;  hex3[2]  ; button2    ; 5.852 ; 5.766 ; Fall       ; button2         ;
+;  hex3[3]  ; button2    ; 5.802 ; 5.717 ; Fall       ; button2         ;
+;  hex3[4]  ; button2    ; 5.969 ; 5.871 ; Fall       ; button2         ;
+;  hex3[5]  ; button2    ; 5.969 ; 5.868 ; Fall       ; button2         ;
+;  hex3[6]  ; button2    ; 5.942 ; 5.841 ; Fall       ; button2         ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; hex0[*]   ; button2    ; 5.279 ; 5.214 ; Fall       ; button2         ;
+;  hex0[0]  ; button2    ; 5.755 ; 5.691 ; Fall       ; button2         ;
+;  hex0[1]  ; button2    ; 5.779 ; 5.698 ; Fall       ; button2         ;
+;  hex0[2]  ; button2    ; 5.288 ; 5.222 ; Fall       ; button2         ;
+;  hex0[3]  ; button2    ; 5.279 ; 5.214 ; Fall       ; button2         ;
+;  hex0[4]  ; button2    ; 5.542 ; 5.477 ; Fall       ; button2         ;
+;  hex0[5]  ; button2    ; 5.324 ; 5.261 ; Fall       ; button2         ;
+;  hex0[6]  ; button2    ; 5.469 ; 5.401 ; Fall       ; button2         ;
+; hex1[*]   ; button2    ; 5.522 ; 5.465 ; Fall       ; button2         ;
+;  hex1[0]  ; button2    ; 5.530 ; 5.474 ; Fall       ; button2         ;
+;  hex1[1]  ; button2    ; 5.594 ; 5.534 ; Fall       ; button2         ;
+;  hex1[2]  ; button2    ; 5.522 ; 5.465 ; Fall       ; button2         ;
+;  hex1[3]  ; button2    ; 5.537 ; 5.467 ; Fall       ; button2         ;
+;  hex1[4]  ; button2    ; 5.784 ; 5.720 ; Fall       ; button2         ;
+;  hex1[5]  ; button2    ; 5.548 ; 5.481 ; Fall       ; button2         ;
+;  hex1[6]  ; button2    ; 5.567 ; 5.506 ; Fall       ; button2         ;
+; hex2[*]   ; button2    ; 5.266 ; 5.209 ; Fall       ; button2         ;
+;  hex2[0]  ; button2    ; 5.464 ; 5.396 ; Fall       ; button2         ;
+;  hex2[1]  ; button2    ; 5.408 ; 5.377 ; Fall       ; button2         ;
+;  hex2[2]  ; button2    ; 5.266 ; 5.209 ; Fall       ; button2         ;
+;  hex2[3]  ; button2    ; 5.484 ; 5.420 ; Fall       ; button2         ;
+;  hex2[4]  ; button2    ; 5.467 ; 5.402 ; Fall       ; button2         ;
+;  hex2[5]  ; button2    ; 5.506 ; 5.442 ; Fall       ; button2         ;
+;  hex2[6]  ; button2    ; 5.872 ; 5.785 ; Fall       ; button2         ;
+; hex3[*]   ; button2    ; 5.684 ; 5.600 ; Fall       ; button2         ;
+;  hex3[0]  ; button2    ; 5.742 ; 5.655 ; Fall       ; button2         ;
+;  hex3[1]  ; button2    ; 5.998 ; 5.897 ; Fall       ; button2         ;
+;  hex3[2]  ; button2    ; 5.733 ; 5.648 ; Fall       ; button2         ;
+;  hex3[3]  ; button2    ; 5.684 ; 5.600 ; Fall       ; button2         ;
+;  hex3[4]  ; button2    ; 5.845 ; 5.749 ; Fall       ; button2         ;
+;  hex3[5]  ; button2    ; 5.845 ; 5.746 ; Fall       ; button2         ;
+;  hex3[6]  ; button2    ; 5.818 ; 5.719 ; Fall       ; button2         ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                                                                      ;
++------------+-----------------+-----------------------------------------+---------------------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name                              ; Note                                                          ;
++------------+-----------------+-----------------------------------------+---------------------------------------------------------------+
+; 337.27 MHz ; 250.0 MHz       ; clk                                     ; limit due to minimum period restriction (max I/O toggle rate) ;
+; 396.51 MHz ; 396.51 MHz      ; hundred_hertz_clock:clockConv|clock_out ;                                                               ;
++------------+-----------------+-----------------------------------------+---------------------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup Summary                               ;
++-----------------------------------------+--------+---------------+
+; Clock                                   ; Slack  ; End Point TNS ;
++-----------------------------------------+--------+---------------+
+; clk                                     ; -1.965 ; -33.034       ;
+; hundred_hertz_clock:clockConv|clock_out ; -1.522 ; -21.435       ;
+; button2                                 ; -1.393 ; -27.476       ;
++-----------------------------------------+--------+---------------+
+
+
++------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold Summary                                ;
++-----------------------------------------+--------+---------------+
+; Clock                                   ; Slack  ; End Point TNS ;
++-----------------------------------------+--------+---------------+
+; clk                                     ; -0.471 ; -0.471        ;
+; hundred_hertz_clock:clockConv|clock_out ; 0.312  ; 0.000         ;
+; button2                                 ; 0.519  ; 0.000         ;
++-----------------------------------------+--------+---------------+
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary                 ;
++-----------------------------------------+--------+---------------+
+; Clock                                   ; Slack  ; End Point TNS ;
++-----------------------------------------+--------+---------------+
+; clk                                     ; -3.000 ; -23.000       ;
+; button2                                 ; -3.000 ; -3.000        ;
+; hundred_hertz_clock:clockConv|clock_out ; -1.000 ; -17.000       ;
++-----------------------------------------+--------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'clk'                                                                                                                            ;
++--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                             ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
+; -1.965 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.906      ;
+; -1.965 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.906      ;
+; -1.965 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.906      ;
+; -1.965 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.906      ;
+; -1.965 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.906      ;
+; -1.965 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.906      ;
+; -1.942 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.883      ;
+; -1.942 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.883      ;
+; -1.942 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.883      ;
+; -1.942 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.883      ;
+; -1.942 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.883      ;
+; -1.942 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.883      ;
+; -1.897 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.507      ;
+; -1.897 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.507      ;
+; -1.897 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.507      ;
+; -1.897 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.507      ;
+; -1.897 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.507      ;
+; -1.897 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.507      ;
+; -1.895 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.835      ;
+; -1.895 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.835      ;
+; -1.895 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.835      ;
+; -1.895 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.835      ;
+; -1.895 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.835      ;
+; -1.895 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.835      ;
+; -1.869 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.810      ;
+; -1.869 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.810      ;
+; -1.869 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.810      ;
+; -1.869 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.810      ;
+; -1.869 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.810      ;
+; -1.869 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.054     ; 2.810      ;
+; -1.809 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.749      ;
+; -1.809 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.749      ;
+; -1.809 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.749      ;
+; -1.809 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.749      ;
+; -1.809 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.749      ;
+; -1.809 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.749      ;
+; -1.807 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.417      ;
+; -1.807 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.417      ;
+; -1.807 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.417      ;
+; -1.807 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.417      ;
+; -1.807 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.417      ;
+; -1.807 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.417      ;
+; -1.805 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.745      ;
+; -1.805 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.745      ;
+; -1.805 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.745      ;
+; -1.805 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.745      ;
+; -1.805 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.745      ;
+; -1.805 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.745      ;
+; -1.774 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.384      ;
+; -1.774 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.384      ;
+; -1.774 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.384      ;
+; -1.774 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.384      ;
+; -1.774 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.384      ;
+; -1.774 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.385     ; 2.384      ;
+; -1.734 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.674      ;
+; -1.734 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.674      ;
+; -1.734 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.674      ;
+; -1.734 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.674      ;
+; -1.734 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.674      ;
+; -1.734 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.674      ;
+; -1.691 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.631      ;
+; -1.691 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.631      ;
+; -1.691 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.631      ;
+; -1.691 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.631      ;
+; -1.691 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.631      ;
+; -1.691 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.631      ;
+; -1.664 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[13] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.604      ;
+; -1.664 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[11] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.604      ;
+; -1.664 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[9]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.604      ;
+; -1.664 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[10] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.604      ;
+; -1.664 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[15] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.604      ;
+; -1.664 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[12] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.604      ;
+; -1.664 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[14] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.604      ;
+; -1.664 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[16] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.604      ;
+; -1.664 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[17] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.604      ;
+; -1.650 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.590      ;
+; -1.650 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.590      ;
+; -1.650 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.590      ;
+; -1.650 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.590      ;
+; -1.650 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.590      ;
+; -1.650 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.590      ;
+; -1.648 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[1]  ; clk          ; clk         ; 1.000        ; 0.263      ; 2.906      ;
+; -1.648 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[0]  ; clk          ; clk         ; 1.000        ; 0.263      ; 2.906      ;
+; -1.648 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[7]  ; clk          ; clk         ; 1.000        ; 0.263      ; 2.906      ;
+; -1.641 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[13] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.581      ;
+; -1.641 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[11] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.581      ;
+; -1.641 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[9]  ; clk          ; clk         ; 1.000        ; -0.055     ; 2.581      ;
+; -1.641 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[10] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.581      ;
+; -1.641 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[15] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.581      ;
+; -1.641 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[12] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.581      ;
+; -1.641 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[14] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.581      ;
+; -1.641 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[16] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.581      ;
+; -1.641 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[17] ; clk          ; clk         ; 1.000        ; -0.055     ; 2.581      ;
+; -1.625 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[1]  ; clk          ; clk         ; 1.000        ; 0.263      ; 2.883      ;
+; -1.625 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[0]  ; clk          ; clk         ; 1.000        ; 0.263      ; 2.883      ;
+; -1.625 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[7]  ; clk          ; clk         ; 1.000        ; 0.263      ; 2.883      ;
+; -1.589 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[13] ; clk          ; clk         ; 1.000        ; -0.056     ; 2.528      ;
+; -1.589 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[11] ; clk          ; clk         ; 1.000        ; -0.056     ; 2.528      ;
+; -1.589 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[9]  ; clk          ; clk         ; 1.000        ; -0.056     ; 2.528      ;
+; -1.589 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[10] ; clk          ; clk         ; 1.000        ; -0.056     ; 2.528      ;
++--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'hundred_hertz_clock:clockConv|clock_out'                                                                                                                   ;
++--------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock                            ; Latch Clock                             ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+; -1.522 ; counter:timeCount|c0[1] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.464      ;
+; -1.522 ; counter:timeCount|c0[1] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.464      ;
+; -1.522 ; counter:timeCount|c0[1] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.464      ;
+; -1.522 ; counter:timeCount|c0[1] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.464      ;
+; -1.484 ; counter:timeCount|c1[1] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.425      ;
+; -1.484 ; counter:timeCount|c1[1] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.425      ;
+; -1.484 ; counter:timeCount|c1[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.425      ;
+; -1.484 ; counter:timeCount|c1[1] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.425      ;
+; -1.479 ; counter:timeCount|c0[3] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.421      ;
+; -1.479 ; counter:timeCount|c0[3] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.421      ;
+; -1.479 ; counter:timeCount|c0[3] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.421      ;
+; -1.479 ; counter:timeCount|c0[3] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.421      ;
+; -1.470 ; counter:timeCount|c1[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.411      ;
+; -1.470 ; counter:timeCount|c1[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.411      ;
+; -1.470 ; counter:timeCount|c1[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.411      ;
+; -1.470 ; counter:timeCount|c1[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.411      ;
+; -1.411 ; counter:timeCount|en    ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.353      ;
+; -1.411 ; counter:timeCount|en    ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.353      ;
+; -1.411 ; counter:timeCount|en    ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.353      ;
+; -1.411 ; counter:timeCount|en    ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.353      ;
+; -1.372 ; counter:timeCount|c0[0] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.314      ;
+; -1.372 ; counter:timeCount|c0[0] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.314      ;
+; -1.372 ; counter:timeCount|c0[0] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.314      ;
+; -1.372 ; counter:timeCount|c0[0] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.314      ;
+; -1.362 ; counter:timeCount|c0[1] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.303      ;
+; -1.362 ; counter:timeCount|c0[1] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.303      ;
+; -1.362 ; counter:timeCount|c0[1] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.303      ;
+; -1.362 ; counter:timeCount|c0[1] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.303      ;
+; -1.356 ; counter:timeCount|c1[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.297      ;
+; -1.356 ; counter:timeCount|c1[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.297      ;
+; -1.356 ; counter:timeCount|c1[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.297      ;
+; -1.356 ; counter:timeCount|c1[3] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.297      ;
+; -1.336 ; counter:timeCount|c0[1] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.277      ;
+; -1.321 ; counter:timeCount|c2[1] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.263      ;
+; -1.321 ; counter:timeCount|c2[1] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.263      ;
+; -1.321 ; counter:timeCount|c2[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.263      ;
+; -1.321 ; counter:timeCount|c2[1] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.263      ;
+; -1.311 ; counter:timeCount|c0[3] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.252      ;
+; -1.280 ; counter:timeCount|c0[2] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.222      ;
+; -1.280 ; counter:timeCount|c0[2] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.222      ;
+; -1.280 ; counter:timeCount|c0[2] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.222      ;
+; -1.280 ; counter:timeCount|c0[2] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.222      ;
+; -1.273 ; counter:timeCount|c0[3] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.214      ;
+; -1.273 ; counter:timeCount|c0[3] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.214      ;
+; -1.273 ; counter:timeCount|c0[3] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.214      ;
+; -1.273 ; counter:timeCount|c0[3] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.214      ;
+; -1.268 ; counter:timeCount|c0[1] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.210      ;
+; -1.268 ; counter:timeCount|c0[1] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.210      ;
+; -1.268 ; counter:timeCount|c0[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.210      ;
+; -1.268 ; counter:timeCount|c0[1] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.210      ;
+; -1.257 ; counter:timeCount|c1[1] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.055     ; 2.197      ;
+; -1.257 ; counter:timeCount|c1[1] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.055     ; 2.197      ;
+; -1.257 ; counter:timeCount|c1[1] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.055     ; 2.197      ;
+; -1.257 ; counter:timeCount|c1[1] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.055     ; 2.197      ;
+; -1.249 ; counter:timeCount|c2[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.191      ;
+; -1.249 ; counter:timeCount|c2[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.191      ;
+; -1.249 ; counter:timeCount|c2[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.191      ;
+; -1.249 ; counter:timeCount|c2[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.191      ;
+; -1.243 ; counter:timeCount|c1[2] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.055     ; 2.183      ;
+; -1.243 ; counter:timeCount|c1[2] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.055     ; 2.183      ;
+; -1.243 ; counter:timeCount|c1[2] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.055     ; 2.183      ;
+; -1.243 ; counter:timeCount|c1[2] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.055     ; 2.183      ;
+; -1.225 ; counter:timeCount|c0[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.167      ;
+; -1.225 ; counter:timeCount|c0[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.167      ;
+; -1.225 ; counter:timeCount|c0[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.167      ;
+; -1.225 ; counter:timeCount|c0[3] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.167      ;
+; -1.213 ; counter:timeCount|en    ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.154      ;
+; -1.213 ; counter:timeCount|en    ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.154      ;
+; -1.213 ; counter:timeCount|en    ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.154      ;
+; -1.213 ; counter:timeCount|en    ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.154      ;
+; -1.204 ; counter:timeCount|c0[0] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.145      ;
+; -1.199 ; counter:timeCount|c1[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.140      ;
+; -1.199 ; counter:timeCount|c1[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.140      ;
+; -1.199 ; counter:timeCount|c1[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.140      ;
+; -1.199 ; counter:timeCount|c1[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.140      ;
+; -1.173 ; counter:timeCount|c1[3] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.055     ; 2.113      ;
+; -1.173 ; counter:timeCount|c1[3] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.055     ; 2.113      ;
+; -1.173 ; counter:timeCount|c1[3] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.055     ; 2.113      ;
+; -1.173 ; counter:timeCount|c1[3] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.055     ; 2.113      ;
+; -1.166 ; counter:timeCount|c0[0] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.107      ;
+; -1.166 ; counter:timeCount|c0[0] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.107      ;
+; -1.166 ; counter:timeCount|c0[0] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.107      ;
+; -1.166 ; counter:timeCount|c0[0] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.107      ;
+; -1.127 ; counter:timeCount|c2[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.069      ;
+; -1.127 ; counter:timeCount|c2[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.069      ;
+; -1.127 ; counter:timeCount|c2[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.069      ;
+; -1.127 ; counter:timeCount|c2[3] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.069      ;
+; -1.120 ; counter:timeCount|c0[2] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.061      ;
+; -1.120 ; counter:timeCount|c0[2] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.061      ;
+; -1.120 ; counter:timeCount|c0[2] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.061      ;
+; -1.120 ; counter:timeCount|c0[2] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.061      ;
+; -1.118 ; counter:timeCount|c0[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.060      ;
+; -1.118 ; counter:timeCount|c0[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.060      ;
+; -1.118 ; counter:timeCount|c0[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.060      ;
+; -1.118 ; counter:timeCount|c0[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.060      ;
+; -1.094 ; counter:timeCount|c0[2] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.054     ; 2.035      ;
+; -1.062 ; counter:timeCount|c2[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.004      ;
+; -1.062 ; counter:timeCount|c2[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.004      ;
+; -1.062 ; counter:timeCount|c2[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.004      ;
+; -1.062 ; counter:timeCount|c2[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.053     ; 2.004      ;
++--------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'button2'                                                                                                                                ;
++--------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                          ; Launch Clock                            ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; -1.393 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.516      ; 1.366      ;
+; -1.377 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.516      ; 1.350      ;
+; -1.197 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.516      ; 1.170      ;
+; -1.160 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.498      ; 1.271      ;
+; -1.130 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.503      ; 1.245      ;
+; -1.115 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.516      ; 1.088      ;
+; -1.098 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.490      ; 1.300      ;
+; -1.059 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.490      ; 1.262      ;
+; -1.048 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.498      ; 1.159      ;
+; -1.040 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.490      ; 1.242      ;
+; -1.033 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.590      ; 1.312      ;
+; -1.025 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.231      ;
+; -1.019 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.225      ;
+; -1.016 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.490      ; 1.219      ;
+; -1.012 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.503      ; 1.127      ;
+; -1.010 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.215      ;
+; -1.009 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.215      ;
+; -1.000 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.206      ;
+; -1.000 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.205      ;
+; -0.998 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.204      ;
+; -0.994 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.590      ; 1.273      ;
+; -0.982 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.592      ; 1.267      ;
+; -0.968 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.174      ;
+; -0.966 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.518      ; 1.276      ;
+; -0.964 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.512      ; 1.264      ;
+; -0.961 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.523      ; 1.276      ;
+; -0.954 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.526      ; 1.272      ;
+; -0.951 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.512      ; 1.251      ;
+; -0.948 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.523      ; 1.260      ;
+; -0.947 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.518      ; 1.257      ;
+; -0.947 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.490      ; 1.149      ;
+; -0.943 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.518      ; 1.253      ;
+; -0.941 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.513      ; 1.244      ;
+; -0.941 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.485      ; 1.271      ;
+; -0.941 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.590      ; 1.220      ;
+; -0.940 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.481      ; 1.265      ;
+; -0.936 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.588      ; 1.218      ;
+; -0.935 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.592      ; 1.220      ;
+; -0.931 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.523      ; 1.246      ;
+; -0.930 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.523      ; 1.242      ;
+; -0.930 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.481      ; 1.255      ;
+; -0.929 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.518      ; 1.239      ;
+; -0.925 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.509      ; 1.261      ;
+; -0.925 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.526      ; 1.243      ;
+; -0.924 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.513      ; 1.227      ;
+; -0.910 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.485      ; 1.240      ;
+; -0.910 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.490      ; 1.113      ;
+; -0.903 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.498      ; 1.014      ;
+; -0.902 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.526      ; 1.220      ;
+; -0.901 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.588      ; 1.183      ;
+; -0.900 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.523      ; 1.215      ;
+; -0.899 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.503      ; 1.014      ;
+; -0.882 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.088      ;
+; -0.882 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.088      ;
+; -0.881 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.086      ;
+; -0.880 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.586      ; 1.161      ;
+; -0.876 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.498      ; 0.987      ;
+; -0.873 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.503      ; 0.988      ;
+; -0.871 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.528      ; 1.245      ;
+; -0.871 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.077      ;
+; -0.870 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.557      ; 1.255      ;
+; -0.870 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.586      ; 1.151      ;
+; -0.866 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.509      ; 1.202      ;
+; -0.862 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.557      ; 1.247      ;
+; -0.860 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.528      ; 1.234      ;
+; -0.859 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.527      ; 1.231      ;
+; -0.851 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.527      ; 1.223      ;
+; -0.849 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.527      ; 1.303      ;
+; -0.846 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.527      ; 1.300      ;
+; -0.825 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.600      ; 1.356      ;
+; -0.824 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.600      ; 1.355      ;
+; -0.818 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.490      ; 1.020      ;
+; -0.817 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.592      ; 1.102      ;
+; -0.813 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.590      ; 1.092      ;
+; -0.804 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.513      ; 1.107      ;
+; -0.802 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.008      ;
+; -0.800 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.005      ;
+; -0.798 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 1.004      ;
+; -0.797 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.588      ; 1.079      ;
+; -0.781 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.512      ; 1.081      ;
+; -0.780 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.527      ; 1.152      ;
+; -0.778 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.490      ; 0.981      ;
+; -0.777 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.488      ; 0.983      ;
+; -0.772 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.518      ; 1.082      ;
+; -0.770 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.528      ; 1.144      ;
+; -0.769 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.518      ; 1.079      ;
+; -0.763 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.509      ; 1.099      ;
+; -0.757 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.523      ; 1.069      ;
+; -0.756 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.557      ; 1.141      ;
+; -0.754 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.527      ; 1.208      ;
+; -0.749 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.481      ; 1.074      ;
+; -0.740 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.485      ; 1.070      ;
+; -0.719 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.586      ; 1.000      ;
+; -0.712 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.588      ; 0.994      ;
+; -0.706 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.592      ; 0.991      ;
+; -0.699 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.523      ; 1.014      ;
+; -0.687 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.512      ; 0.987      ;
+; -0.686 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.518      ; 0.996      ;
+; -0.684 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.518      ; 0.994      ;
+; -0.684 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.513      ; 0.987      ;
++--------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'clk'                                                                                                                                                            ;
++--------+-----------------------------------------+-----------------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                               ; To Node                                 ; Launch Clock                            ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------------------------------------+-----------------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; -0.471 ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; clk         ; 0.000        ; 2.528      ; 2.411      ;
+; 0.047  ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; clk         ; -0.500       ; 2.528      ; 2.429      ;
+; 0.299  ; hundred_hertz_clock:clockConv|start     ; hundred_hertz_clock:clockConv|start     ; clk                                     ; clk         ; 0.000        ; 0.068      ; 0.511      ;
+; 0.336  ; hundred_hertz_clock:clockConv|ctr[17]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.535      ;
+; 0.420  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.385      ; 0.949      ;
+; 0.488  ; hundred_hertz_clock:clockConv|ctr[7]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.068      ; 0.700      ;
+; 0.490  ; hundred_hertz_clock:clockConv|ctr[1]    ; hundred_hertz_clock:clockConv|ctr[1]    ; clk                                     ; clk         ; 0.000        ; 0.068      ; 0.702      ;
+; 0.500  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[4]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.699      ;
+; 0.501  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501  ; hundred_hertz_clock:clockConv|ctr[15]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.700      ;
+; 0.502  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.701      ;
+; 0.503  ; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.702      ;
+; 0.504  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[2]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.703      ;
+; 0.506  ; hundred_hertz_clock:clockConv|ctr[16]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.705      ;
+; 0.508  ; hundred_hertz_clock:clockConv|ctr[0]    ; hundred_hertz_clock:clockConv|ctr[0]    ; clk                                     ; clk         ; 0.000        ; 0.068      ; 0.720      ;
+; 0.512  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.711      ;
+; 0.513  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.712      ;
+; 0.514  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[3]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.713      ;
+; 0.515  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.385      ; 1.044      ;
+; 0.614  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.385      ; 1.143      ;
+; 0.615  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.385      ; 1.144      ;
+; 0.641  ; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.385      ; 1.170      ;
+; 0.644  ; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|ctr[5]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.843      ;
+; 0.741  ; hundred_hertz_clock:clockConv|ctr[0]    ; hundred_hertz_clock:clockConv|ctr[1]    ; clk                                     ; clk         ; 0.000        ; 0.068      ; 0.953      ;
+; 0.745  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; clk         ; 0.000        ; 0.387      ; 1.276      ;
+; 0.745  ; hundred_hertz_clock:clockConv|ctr[15]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.944      ;
+; 0.747  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.946      ;
+; 0.749  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[5]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.948      ;
+; 0.750  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.949      ;
+; 0.751  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.054      ; 0.949      ;
+; 0.752  ; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.951      ;
+; 0.753  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[3]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.952      ;
+; 0.755  ; hundred_hertz_clock:clockConv|ctr[16]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.954      ;
+; 0.756  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.955      ;
+; 0.757  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.956      ;
+; 0.757  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.956      ;
+; 0.757  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.956      ;
+; 0.758  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.957      ;
+; 0.758  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 0.956      ;
+; 0.759  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[4]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.958      ;
+; 0.759  ; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.958      ;
+; 0.760  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[4]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.959      ;
+; 0.764  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.963      ;
+; 0.771  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 0.970      ;
+; 0.775  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; clk         ; 0.000        ; 0.387      ; 1.306      ;
+; 0.791  ; hundred_hertz_clock:clockConv|start     ; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; clk         ; 0.000        ; 0.068      ; 1.003      ;
+; 0.834  ; hundred_hertz_clock:clockConv|ctr[15]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.033      ;
+; 0.836  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.035      ;
+; 0.843  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.042      ;
+; 0.846  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.045      ;
+; 0.846  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.045      ;
+; 0.847  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.046      ;
+; 0.847  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.045      ;
+; 0.847  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.045      ;
+; 0.848  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[5]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.047      ;
+; 0.848  ; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.047      ;
+; 0.849  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[5]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.048      ;
+; 0.852  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.051      ;
+; 0.853  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.052      ;
+; 0.853  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.052      ;
+; 0.854  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.053      ;
+; 0.854  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.052      ;
+; 0.854  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.052      ;
+; 0.855  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.054      ;
+; 0.856  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.055      ;
+; 0.860  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.059      ;
+; 0.867  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.066      ;
+; 0.888  ; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.087      ;
+; 0.932  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.131      ;
+; 0.942  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.140      ;
+; 0.942  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.141      ;
+; 0.942  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.141      ;
+; 0.943  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.142      ;
+; 0.943  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.141      ;
+; 0.943  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.141      ;
+; 0.949  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.147      ;
+; 0.949  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.148      ;
+; 0.950  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.149      ;
+; 0.950  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.148      ;
+; 0.950  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.148      ;
+; 0.951  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.150      ;
+; 0.952  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.151      ;
+; 0.956  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.155      ;
+; 0.963  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.162      ;
+; 0.984  ; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.183      ;
+; 1.016  ; hundred_hertz_clock:clockConv|ctr[1]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.068      ; 1.228      ;
+; 1.029  ; hundred_hertz_clock:clockConv|ctr[0]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.068      ; 1.241      ;
+; 1.038  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.236      ;
+; 1.038  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.237      ;
+; 1.039  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.238      ;
+; 1.039  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.237      ;
+; 1.039  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.237      ;
+; 1.041  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.239      ;
+; 1.042  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.240      ;
+; 1.045  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.243      ;
+; 1.045  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.055      ; 1.244      ;
+; 1.046  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.054      ; 1.244      ;
++--------+-----------------------------------------+-----------------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'hundred_hertz_clock:clockConv|clock_out'                                                                                                                   ;
++-------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                 ; Launch Clock                            ; Latch Clock                             ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+; 0.312 ; counter:timeCount|c3[1] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 0.511      ;
+; 0.313 ; counter:timeCount|c2[1] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; counter:timeCount|c1[1] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; counter:timeCount|c0[1] ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; counter:timeCount|c0[2] ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; counter:timeCount|c0[3] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.511      ;
+; 0.320 ; counter:timeCount|c3[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 0.519      ;
+; 0.321 ; counter:timeCount|c2[0] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.519      ;
+; 0.321 ; counter:timeCount|c1[0] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.519      ;
+; 0.321 ; counter:timeCount|c0[0] ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.519      ;
+; 0.569 ; counter:timeCount|c3[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 0.768      ;
+; 0.603 ; counter:timeCount|c2[0] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.801      ;
+; 0.676 ; counter:timeCount|c0[2] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.874      ;
+; 0.711 ; counter:timeCount|c0[0] ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.909      ;
+; 0.721 ; counter:timeCount|c1[0] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.919      ;
+; 0.725 ; counter:timeCount|c0[2] ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.923      ;
+; 0.751 ; counter:timeCount|en    ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.949      ;
+; 0.755 ; counter:timeCount|en    ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.953      ;
+; 0.756 ; counter:timeCount|en    ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 0.954      ;
+; 0.874 ; counter:timeCount|c2[2] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.072      ;
+; 0.899 ; counter:timeCount|c0[3] ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.097      ;
+; 0.910 ; counter:timeCount|c1[2] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.108      ;
+; 0.930 ; counter:timeCount|c2[2] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.128      ;
+; 0.935 ; counter:timeCount|c2[2] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.133      ;
+; 0.937 ; counter:timeCount|c3[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.136      ;
+; 0.941 ; counter:timeCount|en    ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.139      ;
+; 0.942 ; counter:timeCount|c3[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.141      ;
+; 0.942 ; counter:timeCount|c3[3] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.141      ;
+; 0.942 ; counter:timeCount|c2[2] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.140      ;
+; 0.942 ; counter:timeCount|c0[2] ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.140      ;
+; 0.956 ; counter:timeCount|c2[3] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.154      ;
+; 0.987 ; counter:timeCount|c2[3] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.185      ;
+; 0.990 ; counter:timeCount|c2[3] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.188      ;
+; 1.003 ; counter:timeCount|c1[0] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.201      ;
+; 1.004 ; counter:timeCount|c0[1] ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.202      ;
+; 1.006 ; counter:timeCount|c1[0] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.204      ;
+; 1.010 ; counter:timeCount|c2[3] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.208      ;
+; 1.011 ; counter:timeCount|en    ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.210      ;
+; 1.015 ; counter:timeCount|en    ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.214      ;
+; 1.031 ; counter:timeCount|en    ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.229      ;
+; 1.042 ; counter:timeCount|c2[1] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.240      ;
+; 1.043 ; counter:timeCount|c2[0] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.241      ;
+; 1.047 ; counter:timeCount|c3[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.246      ;
+; 1.074 ; counter:timeCount|c0[0] ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.272      ;
+; 1.095 ; counter:timeCount|c1[2] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.293      ;
+; 1.104 ; counter:timeCount|en    ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.302      ;
+; 1.107 ; counter:timeCount|en    ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.306      ;
+; 1.111 ; counter:timeCount|c2[0] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.309      ;
+; 1.111 ; counter:timeCount|c1[3] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.309      ;
+; 1.112 ; counter:timeCount|en    ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.311      ;
+; 1.112 ; counter:timeCount|c1[3] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.310      ;
+; 1.115 ; counter:timeCount|c1[3] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.313      ;
+; 1.116 ; counter:timeCount|c1[3] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.314      ;
+; 1.122 ; counter:timeCount|c3[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.321      ;
+; 1.123 ; counter:timeCount|c3[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.322      ;
+; 1.123 ; counter:timeCount|c3[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.322      ;
+; 1.137 ; counter:timeCount|c0[3] ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.335      ;
+; 1.159 ; counter:timeCount|c3[1] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.358      ;
+; 1.160 ; counter:timeCount|c3[1] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.359      ;
+; 1.168 ; counter:timeCount|c0[1] ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.366      ;
+; 1.174 ; counter:timeCount|c2[1] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.372      ;
+; 1.181 ; counter:timeCount|c2[1] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.379      ;
+; 1.183 ; counter:timeCount|c1[1] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.381      ;
+; 1.188 ; counter:timeCount|c0[1] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.386      ;
+; 1.191 ; counter:timeCount|c1[2] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.389      ;
+; 1.195 ; counter:timeCount|c1[2] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.393      ;
+; 1.197 ; counter:timeCount|en    ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.397      ;
+; 1.202 ; counter:timeCount|c1[1] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.400      ;
+; 1.207 ; counter:timeCount|c1[1] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.405      ;
+; 1.222 ; counter:timeCount|en    ; counter:timeCount|en    ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.420      ;
+; 1.248 ; counter:timeCount|c0[3] ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.446      ;
+; 1.258 ; counter:timeCount|c0[0] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.456      ;
+; 1.287 ; counter:timeCount|en    ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.487      ;
+; 1.296 ; counter:timeCount|en    ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.496      ;
+; 1.300 ; counter:timeCount|en    ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.498      ;
+; 1.316 ; counter:timeCount|c3[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.515      ;
+; 1.339 ; counter:timeCount|en    ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.537      ;
+; 1.393 ; counter:timeCount|c3[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.592      ;
+; 1.421 ; counter:timeCount|c3[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.620      ;
+; 1.530 ; counter:timeCount|c3[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.055      ; 1.729      ;
+; 1.722 ; counter:timeCount|c0[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.922      ;
+; 1.722 ; counter:timeCount|c0[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.922      ;
+; 1.722 ; counter:timeCount|c0[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.922      ;
+; 1.722 ; counter:timeCount|c0[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.922      ;
+; 1.722 ; counter:timeCount|c2[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.922      ;
+; 1.722 ; counter:timeCount|c2[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.922      ;
+; 1.722 ; counter:timeCount|c2[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.922      ;
+; 1.722 ; counter:timeCount|c2[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.922      ;
+; 1.724 ; counter:timeCount|c1[0] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.053      ; 1.921      ;
+; 1.724 ; counter:timeCount|c1[0] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.053      ; 1.921      ;
+; 1.724 ; counter:timeCount|c1[0] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.053      ; 1.921      ;
+; 1.724 ; counter:timeCount|c1[0] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.053      ; 1.921      ;
+; 1.770 ; counter:timeCount|c0[2] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.968      ;
+; 1.770 ; counter:timeCount|c0[2] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.968      ;
+; 1.770 ; counter:timeCount|c0[2] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.968      ;
+; 1.770 ; counter:timeCount|c0[2] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.054      ; 1.968      ;
+; 1.799 ; counter:timeCount|c0[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.999      ;
+; 1.799 ; counter:timeCount|c0[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.999      ;
+; 1.799 ; counter:timeCount|c0[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.999      ;
+; 1.799 ; counter:timeCount|c0[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.056      ; 1.999      ;
++-------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'button2'                                                                                                                                ;
++-------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                          ; Launch Clock                            ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; 0.519 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.755      ; 0.804      ;
+; 0.605 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.755      ; 0.890      ;
+; 0.612 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.763      ; 0.905      ;
+; 0.616 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.741      ; 0.887      ;
+; 0.625 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.757      ; 0.912      ;
+; 0.635 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.719      ; 0.884      ;
+; 0.637 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.720      ; 0.887      ;
+; 0.653 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.876      ;
+; 0.666 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.771      ; 0.967      ;
+; 0.673 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.684      ; 0.887      ;
+; 0.676 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.684      ; 0.890      ;
+; 0.677 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.688      ; 0.895      ;
+; 0.680 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.687      ; 0.897      ;
+; 0.682 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.676      ; 0.888      ;
+; 0.684 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.682      ; 0.896      ;
+; 0.685 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.679      ; 0.894      ;
+; 0.690 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.688      ; 0.908      ;
+; 0.691 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.668      ; 0.889      ;
+; 0.693 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.691      ; 0.914      ;
+; 0.694 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.678      ; 0.902      ;
+; 0.694 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.687      ; 0.911      ;
+; 0.695 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.755      ; 0.980      ;
+; 0.696 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.755      ; 0.981      ;
+; 0.696 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.757      ; 0.983      ;
+; 0.698 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.682      ; 0.910      ;
+; 0.710 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.664      ; 0.904      ;
+; 0.718 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 0.919      ;
+; 0.719 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 0.920      ;
+; 0.721 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.741      ; 0.992      ;
+; 0.723 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.672      ; 0.925      ;
+; 0.729 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.763      ; 1.022      ;
+; 0.733 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.672      ; 0.935      ;
+; 0.735 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.675      ; 0.940      ;
+; 0.737 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.960      ;
+; 0.746 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.682      ; 0.958      ;
+; 0.751 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.771      ; 1.052      ;
+; 0.752 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.692      ; 0.974      ;
+; 0.752 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.720      ; 1.002      ;
+; 0.758 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.719      ; 1.007      ;
+; 0.761 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.679      ; 0.970      ;
+; 0.764 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.687      ; 0.981      ;
+; 0.765 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.759      ; 1.054      ;
+; 0.765 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.688      ; 0.983      ;
+; 0.776 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.741      ; 1.047      ;
+; 0.778 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.684      ; 0.992      ;
+; 0.780 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.741      ; 1.051      ;
+; 0.783 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.684      ; 0.997      ;
+; 0.786 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.678      ; 0.994      ;
+; 0.786 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.668      ; 0.984      ;
+; 0.789 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.757      ; 1.076      ;
+; 0.793 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.664      ; 0.987      ;
+; 0.798 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.672      ; 1.000      ;
+; 0.799 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.676      ; 1.005      ;
+; 0.799 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.000      ;
+; 0.799 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.672      ; 1.001      ;
+; 0.801 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.002      ;
+; 0.802 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.682      ; 1.014      ;
+; 0.813 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.763      ; 1.106      ;
+; 0.814 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.759      ; 1.103      ;
+; 0.815 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.720      ; 1.065      ;
+; 0.824 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.759      ; 1.113      ;
+; 0.825 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.757      ; 1.112      ;
+; 0.825 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.675      ; 1.030      ;
+; 0.826 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.692      ; 1.048      ;
+; 0.833 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.688      ; 1.051      ;
+; 0.837 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.759      ; 1.126      ;
+; 0.838 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.684      ; 1.052      ;
+; 0.840 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.684      ; 1.054      ;
+; 0.840 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.679      ; 1.049      ;
+; 0.841 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.678      ; 1.049      ;
+; 0.843 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.719      ; 1.092      ;
+; 0.843 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.679      ; 1.052      ;
+; 0.843 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.678      ; 1.051      ;
+; 0.844 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.771      ; 1.145      ;
+; 0.844 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.682      ; 1.056      ;
+; 0.845 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.771      ; 1.146      ;
+; 0.845 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.684      ; 1.059      ;
+; 0.850 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.719      ; 1.099      ;
+; 0.852 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.668      ; 1.050      ;
+; 0.854 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.763      ; 1.147      ;
+; 0.854 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 1.077      ;
+; 0.857 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.720      ; 1.107      ;
+; 0.859 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.664      ; 1.053      ;
+; 0.859 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.664      ; 1.053      ;
+; 0.862 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.691      ; 1.083      ;
+; 0.867 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 1.090      ;
+; 0.867 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.688      ; 1.085      ;
+; 0.870 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.691      ; 1.091      ;
+; 0.874 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.688      ; 1.092      ;
+; 0.875 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.676      ; 1.081      ;
+; 0.876 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.684      ; 1.090      ;
+; 0.882 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.083      ;
+; 0.884 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.676      ; 1.090      ;
+; 0.888 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.672      ; 1.090      ;
+; 0.888 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.672      ; 1.090      ;
+; 0.889 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.672      ; 1.091      ;
+; 0.891 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.668      ; 1.089      ;
+; 0.892 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.671      ; 1.093      ;
+; 0.893 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.672      ; 1.095      ;
+; 0.894 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.688      ; 1.112      ;
++-------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'clk'                                                                          ;
++--------+--------------+----------------+------------------+-------+------------+-----------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                  ;
++--------+--------------+----------------+------------------+-------+------------+-----------------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; clk   ; Rise       ; clk                                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[0]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[10]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[11]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[12]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[13]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[14]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[15]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[16]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[17]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[1]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[2]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[3]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[4]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[5]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[6]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[7]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[8]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[9]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|start     ;
+; 0.179  ; 0.363        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; 0.179  ; 0.363        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[0]    ;
+; 0.179  ; 0.363        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[1]    ;
+; 0.179  ; 0.363        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[7]    ;
+; 0.179  ; 0.363        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|start     ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[10]   ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[11]   ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[12]   ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[13]   ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[14]   ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[15]   ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[16]   ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[17]   ;
+; 0.184  ; 0.368        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[9]    ;
+; 0.185  ; 0.369        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[2]    ;
+; 0.185  ; 0.369        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[3]    ;
+; 0.185  ; 0.369        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[4]    ;
+; 0.185  ; 0.369        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[5]    ;
+; 0.185  ; 0.369        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[6]    ;
+; 0.185  ; 0.369        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[8]    ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|o                             ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|clock_out|clk                 ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[0]|clk                    ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[1]|clk                    ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[7]|clk                    ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|start|clk                     ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[10]|clk                   ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[11]|clk                   ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[12]|clk                   ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[13]|clk                   ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[14]|clk                   ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[15]|clk                   ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[16]|clk                   ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[17]|clk                   ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[9]|clk                    ;
+; 0.345  ; 0.345        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[2]|clk                    ;
+; 0.345  ; 0.345        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[3]|clk                    ;
+; 0.345  ; 0.345        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[4]|clk                    ;
+; 0.345  ; 0.345        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[5]|clk                    ;
+; 0.345  ; 0.345        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[6]|clk                    ;
+; 0.345  ; 0.345        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[8]|clk                    ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~inputclkctrl|inclk[0]               ;
+; 0.348  ; 0.348        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~inputclkctrl|outclk                 ;
+; 0.414  ; 0.630        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[2]    ;
+; 0.414  ; 0.630        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[3]    ;
+; 0.414  ; 0.630        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[4]    ;
+; 0.414  ; 0.630        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[5]    ;
+; 0.414  ; 0.630        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[6]    ;
+; 0.414  ; 0.630        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[8]    ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[10]   ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[11]   ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[12]   ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[13]   ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[14]   ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[15]   ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[16]   ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[17]   ;
+; 0.415  ; 0.631        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[9]    ;
+; 0.420  ; 0.636        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; 0.420  ; 0.636        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[0]    ;
+; 0.420  ; 0.636        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[1]    ;
+; 0.420  ; 0.636        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[7]    ;
+; 0.420  ; 0.636        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|start     ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|i                             ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|i                             ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~inputclkctrl|inclk[0]               ;
+; 0.651  ; 0.651        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~inputclkctrl|outclk                 ;
+; 0.654  ; 0.654        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[2]|clk                    ;
+; 0.654  ; 0.654        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[3]|clk                    ;
+; 0.654  ; 0.654        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[4]|clk                    ;
+; 0.654  ; 0.654        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[5]|clk                    ;
+; 0.654  ; 0.654        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[6]|clk                    ;
+; 0.654  ; 0.654        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[8]|clk                    ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[10]|clk                   ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[11]|clk                   ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[12]|clk                   ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[13]|clk                   ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[14]|clk                   ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[15]|clk                   ;
++--------+--------------+----------------+------------------+-------+------------+-----------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'button2'                                                                 ;
++--------+--------------+----------------+------------------+---------+------------+----------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                           ;
++--------+--------------+----------------+------------------+---------+------------+----------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; button2 ; Rise       ; button2                          ;
+; 0.293  ; 0.293        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[6] ;
+; 0.298  ; 0.298        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[6]|dataa                ;
+; 0.301  ; 0.301        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[4]|dataa                ;
+; 0.303  ; 0.303        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[0]|dataa                ;
+; 0.303  ; 0.303        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[1]|dataa                ;
+; 0.304  ; 0.304        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[1] ;
+; 0.304  ; 0.304        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[4] ;
+; 0.304  ; 0.304        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[5]|dataa                ;
+; 0.305  ; 0.305        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[5] ;
+; 0.306  ; 0.306        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[0] ;
+; 0.309  ; 0.309        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[3]|datad                ;
+; 0.309  ; 0.309        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[4]|datad                ;
+; 0.310  ; 0.310        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[6] ;
+; 0.311  ; 0.311        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[1]|datad                ;
+; 0.314  ; 0.314        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[6]|datad                ;
+; 0.315  ; 0.315        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[6]|datab                ;
+; 0.315  ; 0.315        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[5]|datad                ;
+; 0.319  ; 0.319        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[4]|datab                ;
+; 0.320  ; 0.320        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[0]|dataa                ;
+; 0.320  ; 0.320        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[1]|dataa                ;
+; 0.320  ; 0.320        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[2]|dataa                ;
+; 0.320  ; 0.320        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[3]|dataa                ;
+; 0.320  ; 0.320        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[0]|datac                ;
+; 0.321  ; 0.321        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[5]|datab                ;
+; 0.323  ; 0.323        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[0] ;
+; 0.323  ; 0.323        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[1] ;
+; 0.323  ; 0.323        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[2] ;
+; 0.323  ; 0.323        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[3] ;
+; 0.325  ; 0.325        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[0] ;
+; 0.327  ; 0.327        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[4] ;
+; 0.329  ; 0.329        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[5] ;
+; 0.330  ; 0.330        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[2]|datab                ;
+; 0.330  ; 0.330        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[3]|datab                ;
+; 0.332  ; 0.332        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[3] ;
+; 0.332  ; 0.332        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[3] ;
+; 0.332  ; 0.332        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[4] ;
+; 0.333  ; 0.333        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[2] ;
+; 0.334  ; 0.334        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[1] ;
+; 0.336  ; 0.336        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[2]|datac                ;
+; 0.337  ; 0.337        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[6] ;
+; 0.338  ; 0.338        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[2] ;
+; 0.338  ; 0.338        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[5] ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; button2~input|o                  ;
+; 0.339  ; 0.339        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[4]|datac                ;
+; 0.341  ; 0.341        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[4] ;
+; 0.341  ; 0.341        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[3]|datad                ;
+; 0.342  ; 0.342        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[5]|datac                ;
+; 0.344  ; 0.344        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[5] ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[0]|datac                ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[1]|datad                ;
+; 0.344  ; 0.344        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[2]|datad                ;
+; 0.346  ; 0.346        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[0] ;
+; 0.347  ; 0.347        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[6]|datad                ;
+; 0.363  ; 0.363        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[3] ;
+; 0.366  ; 0.366        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[1] ;
+; 0.366  ; 0.366        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[2] ;
+; 0.369  ; 0.369        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[6] ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; button2~input|i                  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; button2~input|i                  ;
+; 0.628  ; 0.628        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[6] ;
+; 0.631  ; 0.631        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[1] ;
+; 0.631  ; 0.631        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[2] ;
+; 0.634  ; 0.634        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[3] ;
+; 0.652  ; 0.652        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[6]|datad                ;
+; 0.653  ; 0.653        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[0] ;
+; 0.655  ; 0.655        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[5] ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[0]|datac                ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[1]|datad                ;
+; 0.655  ; 0.655        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[2]|datad                ;
+; 0.657  ; 0.657        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[5]|datac                ;
+; 0.658  ; 0.658        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[4] ;
+; 0.658  ; 0.658        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[3]|datad                ;
+; 0.660  ; 0.660        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[2] ;
+; 0.660  ; 0.660        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[3] ;
+; 0.660  ; 0.660        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[4]|datac                ;
+; 0.661  ; 0.661        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; button2~input|o                  ;
+; 0.661  ; 0.661        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[5] ;
+; 0.662  ; 0.662        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[2] ;
+; 0.662  ; 0.662        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[6] ;
+; 0.664  ; 0.664        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss3|out[2]|datac                ;
+; 0.665  ; 0.665        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[5] ;
+; 0.665  ; 0.665        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[1] ;
+; 0.667  ; 0.667        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[4] ;
+; 0.667  ; 0.667        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[3] ;
+; 0.667  ; 0.667        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[4] ;
+; 0.669  ; 0.669        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss1|out[2]|datab                ;
+; 0.670  ; 0.670        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss1|out[3]|datab                ;
+; 0.673  ; 0.673        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[1] ;
+; 0.673  ; 0.673        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[3] ;
+; 0.674  ; 0.674        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[0] ;
+; 0.674  ; 0.674        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[2] ;
+; 0.674  ; 0.674        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[0] ;
+; 0.679  ; 0.679        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[1]|dataa                ;
+; 0.679  ; 0.679        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[3]|dataa                ;
+; 0.679  ; 0.679        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[5]|datab                ;
+; 0.679  ; 0.679        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss3|out[0]|datac                ;
+; 0.680  ; 0.680        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[0]|dataa                ;
+; 0.680  ; 0.680        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[2]|dataa                ;
+; 0.681  ; 0.681        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[4]|datab                ;
++--------+--------------+----------------+------------------+---------+------------+----------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'hundred_hertz_clock:clockConv|clock_out'                                                                     ;
++--------+--------------+----------------+------------------+-----------------------------------------+------------+--------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                   ; Clock Edge ; Target                               ;
++--------+--------------+----------------+------------------+-----------------------------------------+------------+--------------------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|en                 ;
+; 0.291  ; 0.507        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[0]              ;
+; 0.291  ; 0.507        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[1]              ;
+; 0.291  ; 0.507        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[2]              ;
+; 0.291  ; 0.507        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[3]              ;
+; 0.291  ; 0.507        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[0]              ;
+; 0.291  ; 0.507        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[1]              ;
+; 0.291  ; 0.507        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[2]              ;
+; 0.291  ; 0.507        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[3]              ;
+; 0.291  ; 0.507        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|en                 ;
+; 0.292  ; 0.508        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[0]              ;
+; 0.292  ; 0.508        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[1]              ;
+; 0.292  ; 0.508        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[2]              ;
+; 0.292  ; 0.508        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[3]              ;
+; 0.292  ; 0.508        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[0]              ;
+; 0.292  ; 0.508        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[1]              ;
+; 0.292  ; 0.508        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[2]              ;
+; 0.292  ; 0.508        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[3]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[0]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[1]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[2]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[3]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[0]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[1]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[2]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[3]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[0]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[1]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[2]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[3]              ;
+; 0.306  ; 0.490        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|en                 ;
+; 0.307  ; 0.491        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[0]              ;
+; 0.307  ; 0.491        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[1]              ;
+; 0.307  ; 0.491        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[2]              ;
+; 0.307  ; 0.491        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[3]              ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[0]|clk                  ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[1]|clk                  ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[2]|clk                  ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[3]|clk                  ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[0]|clk                  ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[1]|clk                  ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[2]|clk                  ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[3]|clk                  ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[0]|clk                  ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[1]|clk                  ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[2]|clk                  ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[3]|clk                  ;
+; 0.466  ; 0.466        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|en|clk                     ;
+; 0.467  ; 0.467        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[0]|clk                  ;
+; 0.467  ; 0.467        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[1]|clk                  ;
+; 0.467  ; 0.467        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[2]|clk                  ;
+; 0.467  ; 0.467        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[3]|clk                  ;
+; 0.472  ; 0.472        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out~clkctrl|inclk[0] ;
+; 0.472  ; 0.472        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out~clkctrl|outclk   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out|q                ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out|q                ;
+; 0.526  ; 0.526        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out~clkctrl|inclk[0] ;
+; 0.526  ; 0.526        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out~clkctrl|outclk   ;
+; 0.531  ; 0.531        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[0]|clk                  ;
+; 0.531  ; 0.531        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[1]|clk                  ;
+; 0.531  ; 0.531        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[2]|clk                  ;
+; 0.531  ; 0.531        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[3]|clk                  ;
+; 0.531  ; 0.531        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[0]|clk                  ;
+; 0.531  ; 0.531        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[1]|clk                  ;
+; 0.531  ; 0.531        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[2]|clk                  ;
+; 0.531  ; 0.531        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[3]|clk                  ;
+; 0.531  ; 0.531        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|en|clk                     ;
+; 0.532  ; 0.532        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[0]|clk                  ;
+; 0.532  ; 0.532        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[1]|clk                  ;
+; 0.532  ; 0.532        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[2]|clk                  ;
+; 0.532  ; 0.532        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[3]|clk                  ;
+; 0.532  ; 0.532        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[0]|clk                  ;
+; 0.532  ; 0.532        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[1]|clk                  ;
+; 0.532  ; 0.532        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[2]|clk                  ;
+; 0.532  ; 0.532        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[3]|clk                  ;
++--------+--------------+----------------+------------------+-----------------------------------------+------------+--------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                                ;
++-----------+-----------------------------------------+-------+-------+------------+-----------------------------------------+
+; Data Port ; Clock Port                              ; Rise  ; Fall  ; Clock Edge ; Clock Reference                         ;
++-----------+-----------------------------------------+-------+-------+------------+-----------------------------------------+
+; button1   ; clk                                     ; 2.956 ; 3.363 ; Rise       ; clk                                     ;
+; button0   ; hundred_hertz_clock:clockConv|clock_out ; 3.994 ; 4.340 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; button1   ; hundred_hertz_clock:clockConv|clock_out ; 3.585 ; 3.963 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
++-----------+-----------------------------------------+-------+-------+------------+-----------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                                   ;
++-----------+-----------------------------------------+--------+--------+------------+-----------------------------------------+
+; Data Port ; Clock Port                              ; Rise   ; Fall   ; Clock Edge ; Clock Reference                         ;
++-----------+-----------------------------------------+--------+--------+------------+-----------------------------------------+
+; button1   ; clk                                     ; -1.217 ; -1.576 ; Rise       ; clk                                     ;
+; button0   ; hundred_hertz_clock:clockConv|clock_out ; -2.287 ; -2.588 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; button1   ; hundred_hertz_clock:clockConv|clock_out ; -1.925 ; -2.321 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
++-----------+-----------------------------------------+--------+--------+------------+-----------------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; hex0[*]   ; button2    ; 5.613 ; 5.495 ; Fall       ; button2         ;
+;  hex0[0]  ; button2    ; 5.599 ; 5.491 ; Fall       ; button2         ;
+;  hex0[1]  ; button2    ; 5.613 ; 5.495 ; Fall       ; button2         ;
+;  hex0[2]  ; button2    ; 5.132 ; 5.048 ; Fall       ; button2         ;
+;  hex0[3]  ; button2    ; 5.125 ; 5.044 ; Fall       ; button2         ;
+;  hex0[4]  ; button2    ; 5.382 ; 5.289 ; Fall       ; button2         ;
+;  hex0[5]  ; button2    ; 5.172 ; 5.093 ; Fall       ; button2         ;
+;  hex0[6]  ; button2    ; 5.305 ; 5.213 ; Fall       ; button2         ;
+; hex1[*]   ; button2    ; 5.629 ; 5.530 ; Fall       ; button2         ;
+;  hex1[0]  ; button2    ; 5.382 ; 5.298 ; Fall       ; button2         ;
+;  hex1[1]  ; button2    ; 5.449 ; 5.363 ; Fall       ; button2         ;
+;  hex1[2]  ; button2    ; 5.375 ; 5.304 ; Fall       ; button2         ;
+;  hex1[3]  ; button2    ; 5.398 ; 5.305 ; Fall       ; button2         ;
+;  hex1[4]  ; button2    ; 5.629 ; 5.530 ; Fall       ; button2         ;
+;  hex1[5]  ; button2    ; 5.404 ; 5.315 ; Fall       ; button2         ;
+;  hex1[6]  ; button2    ; 5.408 ; 5.322 ; Fall       ; button2         ;
+; hex2[*]   ; button2    ; 5.711 ; 5.583 ; Fall       ; button2         ;
+;  hex2[0]  ; button2    ; 5.317 ; 5.237 ; Fall       ; button2         ;
+;  hex2[1]  ; button2    ; 5.262 ; 5.214 ; Fall       ; button2         ;
+;  hex2[2]  ; button2    ; 5.122 ; 5.050 ; Fall       ; button2         ;
+;  hex2[3]  ; button2    ; 5.336 ; 5.254 ; Fall       ; button2         ;
+;  hex2[4]  ; button2    ; 5.331 ; 5.248 ; Fall       ; button2         ;
+;  hex2[5]  ; button2    ; 5.364 ; 5.277 ; Fall       ; button2         ;
+;  hex2[6]  ; button2    ; 5.711 ; 5.583 ; Fall       ; button2         ;
+; hex3[*]   ; button2    ; 5.848 ; 5.706 ; Fall       ; button2         ;
+;  hex3[0]  ; button2    ; 5.593 ; 5.481 ; Fall       ; button2         ;
+;  hex3[1]  ; button2    ; 5.848 ; 5.706 ; Fall       ; button2         ;
+;  hex3[2]  ; button2    ; 5.572 ; 5.469 ; Fall       ; button2         ;
+;  hex3[3]  ; button2    ; 5.540 ; 5.419 ; Fall       ; button2         ;
+;  hex3[4]  ; button2    ; 5.696 ; 5.573 ; Fall       ; button2         ;
+;  hex3[5]  ; button2    ; 5.689 ; 5.556 ; Fall       ; button2         ;
+;  hex3[6]  ; button2    ; 5.670 ; 5.544 ; Fall       ; button2         ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; hex0[*]   ; button2    ; 5.037 ; 4.957 ; Fall       ; button2         ;
+;  hex0[0]  ; button2    ; 5.490 ; 5.384 ; Fall       ; button2         ;
+;  hex0[1]  ; button2    ; 5.506 ; 5.390 ; Fall       ; button2         ;
+;  hex0[2]  ; button2    ; 5.043 ; 4.960 ; Fall       ; button2         ;
+;  hex0[3]  ; button2    ; 5.037 ; 4.957 ; Fall       ; button2         ;
+;  hex0[4]  ; button2    ; 5.282 ; 5.190 ; Fall       ; button2         ;
+;  hex0[5]  ; button2    ; 5.080 ; 5.003 ; Fall       ; button2         ;
+;  hex0[6]  ; button2    ; 5.209 ; 5.119 ; Fall       ; button2         ;
+; hex1[*]   ; button2    ; 5.256 ; 5.182 ; Fall       ; button2         ;
+;  hex1[0]  ; button2    ; 5.264 ; 5.182 ; Fall       ; button2         ;
+;  hex1[1]  ; button2    ; 5.322 ; 5.237 ; Fall       ; button2         ;
+;  hex1[2]  ; button2    ; 5.256 ; 5.185 ; Fall       ; button2         ;
+;  hex1[3]  ; button2    ; 5.277 ; 5.186 ; Fall       ; button2         ;
+;  hex1[4]  ; button2    ; 5.501 ; 5.404 ; Fall       ; button2         ;
+;  hex1[5]  ; button2    ; 5.279 ; 5.191 ; Fall       ; button2         ;
+;  hex1[6]  ; button2    ; 5.292 ; 5.207 ; Fall       ; button2         ;
+; hex2[*]   ; button2    ; 5.016 ; 4.944 ; Fall       ; button2         ;
+;  hex2[0]  ; button2    ; 5.202 ; 5.123 ; Fall       ; button2         ;
+;  hex2[1]  ; button2    ; 5.149 ; 5.100 ; Fall       ; button2         ;
+;  hex2[2]  ; button2    ; 5.016 ; 4.944 ; Fall       ; button2         ;
+;  hex2[3]  ; button2    ; 5.219 ; 5.138 ; Fall       ; button2         ;
+;  hex2[4]  ; button2    ; 5.216 ; 5.134 ; Fall       ; button2         ;
+;  hex2[5]  ; button2    ; 5.247 ; 5.162 ; Fall       ; button2         ;
+;  hex2[6]  ; button2    ; 5.581 ; 5.455 ; Fall       ; button2         ;
+; hex3[*]   ; button2    ; 5.435 ; 5.317 ; Fall       ; button2         ;
+;  hex3[0]  ; button2    ; 5.484 ; 5.375 ; Fall       ; button2         ;
+;  hex3[1]  ; button2    ; 5.730 ; 5.592 ; Fall       ; button2         ;
+;  hex3[2]  ; button2    ; 5.465 ; 5.364 ; Fall       ; button2         ;
+;  hex3[3]  ; button2    ; 5.435 ; 5.317 ; Fall       ; button2         ;
+;  hex3[4]  ; button2    ; 5.585 ; 5.465 ; Fall       ; button2         ;
+;  hex3[5]  ; button2    ; 5.578 ; 5.449 ; Fall       ; button2         ;
+;  hex3[6]  ; button2    ; 5.559 ; 5.436 ; Fall       ; button2         ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup Summary                               ;
++-----------------------------------------+--------+---------------+
+; Clock                                   ; Slack  ; End Point TNS ;
++-----------------------------------------+--------+---------------+
+; clk                                     ; -0.818 ; -12.731       ;
+; hundred_hertz_clock:clockConv|clock_out ; -0.550 ; -6.614        ;
+; button2                                 ; -0.418 ; -4.063        ;
++-----------------------------------------+--------+---------------+
+
+
++------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold Summary                                ;
++-----------------------------------------+--------+---------------+
+; Clock                                   ; Slack  ; End Point TNS ;
++-----------------------------------------+--------+---------------+
+; clk                                     ; -0.319 ; -0.319        ;
+; button2                                 ; 0.185  ; 0.000         ;
+; hundred_hertz_clock:clockConv|clock_out ; 0.188  ; 0.000         ;
++-----------------------------------------+--------+---------------+
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary                 ;
++-----------------------------------------+--------+---------------+
+; Clock                                   ; Slack  ; End Point TNS ;
++-----------------------------------------+--------+---------------+
+; clk                                     ; -3.000 ; -24.262       ;
+; button2                                 ; -3.000 ; -3.414        ;
+; hundred_hertz_clock:clockConv|clock_out ; -1.000 ; -17.000       ;
++-----------------------------------------+--------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'clk'                                                                                                                            ;
++--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                             ; To Node                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
+; -0.818 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.770      ;
+; -0.818 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.770      ;
+; -0.818 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.770      ;
+; -0.818 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.770      ;
+; -0.818 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.770      ;
+; -0.818 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.770      ;
+; -0.811 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.763      ;
+; -0.811 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.763      ;
+; -0.811 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.763      ;
+; -0.811 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.763      ;
+; -0.811 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.763      ;
+; -0.811 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.763      ;
+; -0.809 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.760      ;
+; -0.809 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.760      ;
+; -0.809 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.760      ;
+; -0.809 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.760      ;
+; -0.809 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.760      ;
+; -0.809 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.760      ;
+; -0.770 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.525      ;
+; -0.770 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.525      ;
+; -0.770 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.525      ;
+; -0.770 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.525      ;
+; -0.770 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.525      ;
+; -0.770 ; hundred_hertz_clock:clockConv|ctr[0]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.525      ;
+; -0.759 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.711      ;
+; -0.759 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.711      ;
+; -0.759 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.711      ;
+; -0.759 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.711      ;
+; -0.759 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.711      ;
+; -0.759 ; hundred_hertz_clock:clockConv|ctr[11] ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.711      ;
+; -0.736 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.687      ;
+; -0.736 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.687      ;
+; -0.736 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.687      ;
+; -0.736 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.687      ;
+; -0.736 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.687      ;
+; -0.736 ; hundred_hertz_clock:clockConv|ctr[8]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.687      ;
+; -0.722 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.673      ;
+; -0.722 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.673      ;
+; -0.722 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.673      ;
+; -0.722 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.673      ;
+; -0.722 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.673      ;
+; -0.722 ; hundred_hertz_clock:clockConv|ctr[3]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.673      ;
+; -0.713 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.664      ;
+; -0.713 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.664      ;
+; -0.713 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.664      ;
+; -0.713 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.664      ;
+; -0.713 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.664      ;
+; -0.713 ; hundred_hertz_clock:clockConv|ctr[4]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.664      ;
+; -0.712 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.467      ;
+; -0.712 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.467      ;
+; -0.712 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.467      ;
+; -0.712 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.467      ;
+; -0.712 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.467      ;
+; -0.712 ; hundred_hertz_clock:clockConv|ctr[1]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.467      ;
+; -0.697 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.452      ;
+; -0.697 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.452      ;
+; -0.697 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.452      ;
+; -0.697 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.452      ;
+; -0.697 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.452      ;
+; -0.697 ; hundred_hertz_clock:clockConv|ctr[7]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.232     ; 1.452      ;
+; -0.662 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.613      ;
+; -0.662 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.613      ;
+; -0.662 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.613      ;
+; -0.662 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.613      ;
+; -0.662 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.613      ;
+; -0.662 ; hundred_hertz_clock:clockConv|ctr[5]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.613      ;
+; -0.644 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[2]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.595      ;
+; -0.644 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[3]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.595      ;
+; -0.644 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[4]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.595      ;
+; -0.644 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[5]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.595      ;
+; -0.644 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[6]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.595      ;
+; -0.644 ; hundred_hertz_clock:clockConv|ctr[2]  ; hundred_hertz_clock:clockConv|ctr[8]  ; clk          ; clk         ; 1.000        ; -0.036     ; 1.595      ;
+; -0.629 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[1]  ; clk          ; clk         ; 1.000        ; 0.154      ; 1.770      ;
+; -0.629 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[0]  ; clk          ; clk         ; 1.000        ; 0.154      ; 1.770      ;
+; -0.629 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[7]  ; clk          ; clk         ; 1.000        ; 0.154      ; 1.770      ;
+; -0.622 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[1]  ; clk          ; clk         ; 1.000        ; 0.154      ; 1.763      ;
+; -0.622 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[0]  ; clk          ; clk         ; 1.000        ; 0.154      ; 1.763      ;
+; -0.622 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[7]  ; clk          ; clk         ; 1.000        ; 0.154      ; 1.763      ;
+; -0.620 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[1]  ; clk          ; clk         ; 1.000        ; 0.153      ; 1.760      ;
+; -0.620 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[0]  ; clk          ; clk         ; 1.000        ; 0.153      ; 1.760      ;
+; -0.620 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[7]  ; clk          ; clk         ; 1.000        ; 0.153      ; 1.760      ;
+; -0.611 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[13] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.563      ;
+; -0.611 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[11] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.563      ;
+; -0.611 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[9]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.563      ;
+; -0.611 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[10] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.563      ;
+; -0.611 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[15] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.563      ;
+; -0.611 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[12] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.563      ;
+; -0.611 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[14] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.563      ;
+; -0.611 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[16] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.563      ;
+; -0.611 ; hundred_hertz_clock:clockConv|ctr[10] ; hundred_hertz_clock:clockConv|ctr[17] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.563      ;
+; -0.604 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[13] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.556      ;
+; -0.604 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[11] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.556      ;
+; -0.604 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[9]  ; clk          ; clk         ; 1.000        ; -0.035     ; 1.556      ;
+; -0.604 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[10] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.556      ;
+; -0.604 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[15] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.556      ;
+; -0.604 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[12] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.556      ;
+; -0.604 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[14] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.556      ;
+; -0.604 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[16] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.556      ;
+; -0.604 ; hundred_hertz_clock:clockConv|ctr[9]  ; hundred_hertz_clock:clockConv|ctr[17] ; clk          ; clk         ; 1.000        ; -0.035     ; 1.556      ;
+; -0.602 ; hundred_hertz_clock:clockConv|ctr[6]  ; hundred_hertz_clock:clockConv|ctr[13] ; clk          ; clk         ; 1.000        ; -0.036     ; 1.553      ;
++--------+---------------------------------------+---------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'hundred_hertz_clock:clockConv|clock_out'                                                                                                                   ;
++--------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                 ; Launch Clock                            ; Latch Clock                             ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+; -0.550 ; counter:timeCount|c0[1] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.502      ;
+; -0.550 ; counter:timeCount|c0[1] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.502      ;
+; -0.550 ; counter:timeCount|c0[1] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.502      ;
+; -0.550 ; counter:timeCount|c0[1] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.502      ;
+; -0.535 ; counter:timeCount|c0[3] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.487      ;
+; -0.535 ; counter:timeCount|c0[3] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.487      ;
+; -0.535 ; counter:timeCount|c0[3] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.487      ;
+; -0.535 ; counter:timeCount|c0[3] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.487      ;
+; -0.510 ; counter:timeCount|en    ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.463      ;
+; -0.510 ; counter:timeCount|en    ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.463      ;
+; -0.510 ; counter:timeCount|en    ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.463      ;
+; -0.510 ; counter:timeCount|en    ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.463      ;
+; -0.501 ; counter:timeCount|c1[1] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.453      ;
+; -0.501 ; counter:timeCount|c1[1] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.453      ;
+; -0.501 ; counter:timeCount|c1[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.453      ;
+; -0.501 ; counter:timeCount|c1[1] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.453      ;
+; -0.484 ; counter:timeCount|c1[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.436      ;
+; -0.484 ; counter:timeCount|c1[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.436      ;
+; -0.484 ; counter:timeCount|c1[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.436      ;
+; -0.484 ; counter:timeCount|c1[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.436      ;
+; -0.474 ; counter:timeCount|c1[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.426      ;
+; -0.474 ; counter:timeCount|c1[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.426      ;
+; -0.474 ; counter:timeCount|c1[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.426      ;
+; -0.474 ; counter:timeCount|c1[3] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.426      ;
+; -0.465 ; counter:timeCount|c0[0] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.417      ;
+; -0.465 ; counter:timeCount|c0[0] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.417      ;
+; -0.465 ; counter:timeCount|c0[0] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.417      ;
+; -0.465 ; counter:timeCount|c0[0] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.417      ;
+; -0.456 ; counter:timeCount|c0[1] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.408      ;
+; -0.432 ; counter:timeCount|c0[3] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.383      ;
+; -0.432 ; counter:timeCount|c0[3] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.383      ;
+; -0.432 ; counter:timeCount|c0[3] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.383      ;
+; -0.432 ; counter:timeCount|c0[3] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.383      ;
+; -0.427 ; counter:timeCount|c0[1] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.378      ;
+; -0.427 ; counter:timeCount|c0[1] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.378      ;
+; -0.427 ; counter:timeCount|c0[1] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.378      ;
+; -0.427 ; counter:timeCount|c0[1] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.378      ;
+; -0.422 ; counter:timeCount|c0[3] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.374      ;
+; -0.408 ; counter:timeCount|c2[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.361      ;
+; -0.408 ; counter:timeCount|c2[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.361      ;
+; -0.408 ; counter:timeCount|c2[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.361      ;
+; -0.408 ; counter:timeCount|c2[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.361      ;
+; -0.395 ; counter:timeCount|c2[1] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.348      ;
+; -0.395 ; counter:timeCount|c2[1] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.348      ;
+; -0.395 ; counter:timeCount|c2[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.348      ;
+; -0.395 ; counter:timeCount|c2[1] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.348      ;
+; -0.394 ; counter:timeCount|c0[2] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.346      ;
+; -0.394 ; counter:timeCount|c0[2] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.346      ;
+; -0.394 ; counter:timeCount|c0[2] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.346      ;
+; -0.394 ; counter:timeCount|c0[2] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.346      ;
+; -0.387 ; counter:timeCount|c1[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.339      ;
+; -0.387 ; counter:timeCount|c1[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.339      ;
+; -0.387 ; counter:timeCount|c1[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.339      ;
+; -0.387 ; counter:timeCount|c1[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.339      ;
+; -0.386 ; counter:timeCount|c0[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.338      ;
+; -0.386 ; counter:timeCount|c0[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.338      ;
+; -0.386 ; counter:timeCount|c0[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.338      ;
+; -0.386 ; counter:timeCount|c0[3] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.338      ;
+; -0.371 ; counter:timeCount|c0[1] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.323      ;
+; -0.371 ; counter:timeCount|c0[1] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.323      ;
+; -0.371 ; counter:timeCount|c0[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.323      ;
+; -0.371 ; counter:timeCount|c0[1] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.323      ;
+; -0.371 ; counter:timeCount|c1[1] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.322      ;
+; -0.371 ; counter:timeCount|c1[1] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.322      ;
+; -0.371 ; counter:timeCount|c1[1] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.322      ;
+; -0.371 ; counter:timeCount|c1[1] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.322      ;
+; -0.366 ; counter:timeCount|en    ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.318      ;
+; -0.366 ; counter:timeCount|en    ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.318      ;
+; -0.366 ; counter:timeCount|en    ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.318      ;
+; -0.366 ; counter:timeCount|en    ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.318      ;
+; -0.362 ; counter:timeCount|c0[0] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.313      ;
+; -0.362 ; counter:timeCount|c0[0] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.313      ;
+; -0.362 ; counter:timeCount|c0[0] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.313      ;
+; -0.362 ; counter:timeCount|c0[0] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.313      ;
+; -0.354 ; counter:timeCount|c1[2] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.305      ;
+; -0.354 ; counter:timeCount|c1[2] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.305      ;
+; -0.354 ; counter:timeCount|c1[2] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.305      ;
+; -0.354 ; counter:timeCount|c1[2] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.305      ;
+; -0.352 ; counter:timeCount|c0[0] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.304      ;
+; -0.344 ; counter:timeCount|c1[3] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.295      ;
+; -0.344 ; counter:timeCount|c1[3] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.295      ;
+; -0.344 ; counter:timeCount|c1[3] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.295      ;
+; -0.344 ; counter:timeCount|c1[3] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.295      ;
+; -0.332 ; counter:timeCount|c2[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.285      ;
+; -0.332 ; counter:timeCount|c2[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.285      ;
+; -0.332 ; counter:timeCount|c2[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.285      ;
+; -0.332 ; counter:timeCount|c2[3] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.034     ; 1.285      ;
+; -0.316 ; counter:timeCount|c0[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.268      ;
+; -0.316 ; counter:timeCount|c0[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.268      ;
+; -0.316 ; counter:timeCount|c0[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.268      ;
+; -0.316 ; counter:timeCount|c0[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.268      ;
+; -0.300 ; counter:timeCount|c0[2] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.252      ;
+; -0.271 ; counter:timeCount|c0[2] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.222      ;
+; -0.271 ; counter:timeCount|c0[2] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.222      ;
+; -0.271 ; counter:timeCount|c0[2] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.222      ;
+; -0.271 ; counter:timeCount|c0[2] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.222      ;
+; -0.266 ; counter:timeCount|c3[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.035     ; 1.218      ;
+; -0.257 ; counter:timeCount|c1[0] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.208      ;
+; -0.257 ; counter:timeCount|c1[0] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.208      ;
+; -0.257 ; counter:timeCount|c1[0] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 1.000        ; -0.036     ; 1.208      ;
++--------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'button2'                                                                                                                                ;
++--------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node               ; To Node                          ; Launch Clock                            ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; -0.418 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.603      ; 0.855      ;
+; -0.410 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.603      ; 0.847      ;
+; -0.274 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.576      ; 0.787      ;
+; -0.269 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.603      ; 0.706      ;
+; -0.261 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.580      ; 0.778      ;
+; -0.240 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.603      ; 0.677      ;
+; -0.208 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.783      ;
+; -0.207 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.781      ;
+; -0.204 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.778      ;
+; -0.201 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.576      ; 0.714      ;
+; -0.192 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.569      ; 0.771      ;
+; -0.184 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.759      ;
+; -0.184 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.569      ; 0.763      ;
+; -0.179 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.580      ; 0.696      ;
+; -0.168 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.569      ; 0.747      ;
+; -0.167 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.643      ; 0.796      ;
+; -0.165 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.745      ;
+; -0.161 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.569      ; 0.740      ;
+; -0.160 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.741      ;
+; -0.157 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.650      ; 0.793      ;
+; -0.157 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.737      ;
+; -0.154 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.650      ; 0.790      ;
+; -0.138 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.643      ; 0.767      ;
+; -0.137 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.718      ;
+; -0.135 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.608      ; 0.790      ;
+; -0.135 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.709      ;
+; -0.128 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.565      ; 0.784      ;
+; -0.127 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.604      ; 0.778      ;
+; -0.125 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.562      ; 0.778      ;
+; -0.117 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.608      ; 0.773      ;
+; -0.117 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.604      ; 0.768      ;
+; -0.117 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.562      ; 0.770      ;
+; -0.116 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.614      ; 0.778      ;
+; -0.114 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.579      ; 0.769      ;
+; -0.114 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.618      ; 0.779      ;
+; -0.113 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.608      ; 0.769      ;
+; -0.111 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.602      ; 0.761      ;
+; -0.109 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.648      ; 0.745      ;
+; -0.105 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.616      ; 0.769      ;
+; -0.105 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.614      ; 0.767      ;
+; -0.104 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.608      ; 0.759      ;
+; -0.102 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.618      ; 0.767      ;
+; -0.101 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.676      ;
+; -0.100 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.565      ; 0.756      ;
+; -0.095 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.616      ; 0.759      ;
+; -0.094 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.576      ; 0.607      ;
+; -0.094 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.602      ; 0.744      ;
+; -0.093 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.673      ;
+; -0.092 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.569      ; 0.671      ;
+; -0.090 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.580      ; 0.607      ;
+; -0.088 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.669      ;
+; -0.087 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.648      ; 0.723      ;
+; -0.086 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.579      ; 0.741      ;
+; -0.086 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.650      ; 0.722      ;
+; -0.083 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.576      ; 0.596      ;
+; -0.083 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.618      ; 0.748      ;
+; -0.081 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.608      ; 0.767      ;
+; -0.081 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.614      ; 0.743      ;
+; -0.079 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.580      ; 0.596      ;
+; -0.074 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.595      ; 0.760      ;
+; -0.074 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.595      ; 0.760      ;
+; -0.071 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.608      ; 0.757      ;
+; -0.070 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.649      ; 0.707      ;
+; -0.070 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.569      ; 0.649      ;
+; -0.068 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.595      ; 0.754      ;
+; -0.066 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.649      ; 0.703      ;
+; -0.060 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.595      ; 0.746      ;
+; -0.046 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.645      ; 0.841      ;
+; -0.046 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.619      ; 0.809      ;
+; -0.046 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.650      ; 0.682      ;
+; -0.041 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.643      ; 0.670      ;
+; -0.039 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.645      ; 0.834      ;
+; -0.036 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.619      ; 0.799      ;
+; -0.036 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.611      ;
+; -0.035 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.609      ;
+; -0.034 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.614      ;
+; -0.032 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.569      ; 0.611      ;
+; -0.031 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.569      ; 0.610      ;
+; -0.027 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.570      ; 0.608      ;
+; -0.027 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.648      ; 0.663      ;
+; -0.025 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.602      ; 0.675      ;
+; -0.021 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.595      ; 0.707      ;
+; -0.013 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.595      ; 0.699      ;
+; -0.008 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.579      ; 0.663      ;
+; -0.005 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.608      ; 0.691      ;
+; 0.002  ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.604      ; 0.649      ;
+; 0.006  ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.608      ; 0.650      ;
+; 0.009  ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.608      ; 0.646      ;
+; 0.010  ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.562      ; 0.643      ;
+; 0.016  ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.619      ; 0.747      ;
+; 0.018  ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.616      ; 0.646      ;
+; 0.020  ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.565      ; 0.636      ;
+; 0.025  ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.649      ; 0.612      ;
+; 0.030  ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.643      ; 0.599      ;
+; 0.036  ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.648      ; 0.600      ;
+; 0.045  ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.614      ; 0.617      ;
+; 0.046  ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.608      ; 0.610      ;
+; 0.049  ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.608      ; 0.606      ;
+; 0.051  ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.565      ; 0.605      ;
+; 0.053  ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; 0.500        ; 0.602      ; 0.597      ;
++--------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'clk'                                                                                                                                                            ;
++--------+-----------------------------------------+-----------------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                               ; To Node                                 ; Launch Clock                            ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-----------------------------------------+-----------------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; -0.319 ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; clk         ; 0.000        ; 1.574      ; 1.474      ;
+; 0.180  ; hundred_hertz_clock:clockConv|start     ; hundred_hertz_clock:clockConv|start     ; clk                                     ; clk         ; 0.000        ; 0.043      ; 0.307      ;
+; 0.199  ; hundred_hertz_clock:clockConv|ctr[17]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.318      ;
+; 0.260  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.232      ; 0.576      ;
+; 0.291  ; hundred_hertz_clock:clockConv|ctr[1]    ; hundred_hertz_clock:clockConv|ctr[1]    ; clk                                     ; clk         ; 0.000        ; 0.043      ; 0.418      ;
+; 0.291  ; hundred_hertz_clock:clockConv|ctr[7]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.043      ; 0.418      ;
+; 0.298  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.418      ;
+; 0.299  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[4]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299  ; hundred_hertz_clock:clockConv|ctr[15]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.418      ;
+; 0.300  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[2]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.419      ;
+; 0.301  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.420      ;
+; 0.301  ; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.420      ;
+; 0.302  ; hundred_hertz_clock:clockConv|ctr[16]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.421      ;
+; 0.304  ; hundred_hertz_clock:clockConv|ctr[0]    ; hundred_hertz_clock:clockConv|ctr[0]    ; clk                                     ; clk         ; 0.000        ; 0.043      ; 0.431      ;
+; 0.306  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[3]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.425      ;
+; 0.307  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.426      ;
+; 0.316  ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; clk         ; -0.500       ; 1.574      ; 1.609      ;
+; 0.327  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.232      ; 0.643      ;
+; 0.372  ; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|ctr[5]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.492      ;
+; 0.388  ; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.232      ; 0.704      ;
+; 0.388  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.232      ; 0.704      ;
+; 0.394  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.232      ; 0.710      ;
+; 0.448  ; hundred_hertz_clock:clockConv|ctr[15]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.567      ;
+; 0.450  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.569      ;
+; 0.451  ; hundred_hertz_clock:clockConv|ctr[0]    ; hundred_hertz_clock:clockConv|ctr[1]    ; clk                                     ; clk         ; 0.000        ; 0.043      ; 0.578      ;
+; 0.453  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; clk         ; 0.000        ; 0.232      ; 0.769      ;
+; 0.455  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[4]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.575      ;
+; 0.455  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.574      ;
+; 0.456  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.575      ;
+; 0.457  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.576      ;
+; 0.457  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[5]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.577      ;
+; 0.458  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.577      ;
+; 0.458  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[3]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.578      ;
+; 0.459  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.579      ;
+; 0.459  ; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.578      ;
+; 0.460  ; hundred_hertz_clock:clockConv|ctr[16]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.579      ;
+; 0.460  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.580      ;
+; 0.460  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.579      ;
+; 0.461  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.580      ;
+; 0.461  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[4]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.581      ;
+; 0.462  ; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.581      ;
+; 0.465  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.584      ;
+; 0.467  ; hundred_hertz_clock:clockConv|start     ; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; clk         ; 0.000        ; 0.043      ; 0.594      ;
+; 0.468  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.587      ;
+; 0.470  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; clk         ; 0.000        ; 0.232      ; 0.786      ;
+; 0.511  ; hundred_hertz_clock:clockConv|ctr[15]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.630      ;
+; 0.513  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.632      ;
+; 0.516  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.635      ;
+; 0.518  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[5]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.638      ;
+; 0.518  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.637      ;
+; 0.519  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.638      ;
+; 0.521  ; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.641      ;
+; 0.521  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.641      ;
+; 0.521  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.640      ;
+; 0.522  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.641      ;
+; 0.523  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.642      ;
+; 0.523  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.642      ;
+; 0.524  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.643      ;
+; 0.524  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[5]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.644      ;
+; 0.525  ; hundred_hertz_clock:clockConv|ctr[14]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.644      ;
+; 0.526  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.646      ;
+; 0.526  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.645      ;
+; 0.526  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.645      ;
+; 0.527  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.646      ;
+; 0.527  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[6]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.647      ;
+; 0.531  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.650      ;
+; 0.534  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.653      ;
+; 0.579  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.698      ;
+; 0.584  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.703      ;
+; 0.585  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.704      ;
+; 0.587  ; hundred_hertz_clock:clockConv|ctr[5]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.707      ;
+; 0.587  ; hundred_hertz_clock:clockConv|ctr[3]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.707      ;
+; 0.587  ; hundred_hertz_clock:clockConv|ctr[9]    ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.706      ;
+; 0.588  ; hundred_hertz_clock:clockConv|ctr[11]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.707      ;
+; 0.589  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.708      ;
+; 0.589  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[13]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.708      ;
+; 0.590  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.709      ;
+; 0.590  ; hundred_hertz_clock:clockConv|ctr[12]   ; hundred_hertz_clock:clockConv|ctr[17]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.709      ;
+; 0.592  ; hundred_hertz_clock:clockConv|ctr[6]    ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.711      ;
+; 0.592  ; hundred_hertz_clock:clockConv|ctr[8]    ; hundred_hertz_clock:clockConv|ctr[14]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.711      ;
+; 0.593  ; hundred_hertz_clock:clockConv|ctr[4]    ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.712      ;
+; 0.593  ; hundred_hertz_clock:clockConv|ctr[2]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; 0.036      ; 0.713      ;
+; 0.597  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[15]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.716      ;
+; 0.600  ; hundred_hertz_clock:clockConv|ctr[10]   ; hundred_hertz_clock:clockConv|ctr[16]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.719      ;
+; 0.615  ; hundred_hertz_clock:clockConv|ctr[15]   ; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; clk         ; 0.000        ; 0.232      ; 0.931      ;
+; 0.632  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[1]    ; clk                                     ; clk         ; 0.000        ; 0.232      ; 0.948      ;
+; 0.632  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[0]    ; clk                                     ; clk         ; 0.000        ; 0.232      ; 0.948      ;
+; 0.632  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.232      ; 0.948      ;
+; 0.635  ; hundred_hertz_clock:clockConv|ctr[1]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.043      ; 0.762      ;
+; 0.636  ; hundred_hertz_clock:clockConv|ctr[1]    ; hundred_hertz_clock:clockConv|ctr[2]    ; clk                                     ; clk         ; 0.000        ; -0.153     ; 0.567      ;
+; 0.636  ; hundred_hertz_clock:clockConv|ctr[7]    ; hundred_hertz_clock:clockConv|ctr[8]    ; clk                                     ; clk         ; 0.000        ; -0.153     ; 0.567      ;
+; 0.649  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[11]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.768      ;
+; 0.649  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[9]    ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.768      ;
+; 0.649  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[10]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.768      ;
+; 0.649  ; hundred_hertz_clock:clockConv|ctr[13]   ; hundred_hertz_clock:clockConv|ctr[12]   ; clk                                     ; clk         ; 0.000        ; 0.035      ; 0.768      ;
+; 0.649  ; hundred_hertz_clock:clockConv|ctr[0]    ; hundred_hertz_clock:clockConv|ctr[7]    ; clk                                     ; clk         ; 0.000        ; 0.043      ; 0.776      ;
++--------+-----------------------------------------+-----------------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'button2'                                                                                                                                ;
++-------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                          ; Launch Clock                            ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+; 0.185 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.762      ; 0.477      ;
+; 0.235 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.762      ; 0.527      ;
+; 0.240 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.761      ; 0.531      ;
+; 0.241 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.755      ; 0.526      ;
+; 0.270 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.730      ; 0.530      ;
+; 0.270 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.720      ; 0.520      ;
+; 0.273 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.720      ; 0.523      ;
+; 0.273 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.727      ; 0.530      ;
+; 0.274 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.719      ; 0.523      ;
+; 0.275 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.719      ; 0.524      ;
+; 0.283 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.725      ; 0.538      ;
+; 0.287 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.761      ; 0.578      ;
+; 0.288 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.704      ; 0.522      ;
+; 0.289 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.758      ; 0.577      ;
+; 0.296 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.713      ; 0.539      ;
+; 0.297 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.729      ; 0.556      ;
+; 0.302 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.715      ; 0.547      ;
+; 0.302 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.763      ; 0.595      ;
+; 0.304 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.698      ; 0.532      ;
+; 0.304 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.762      ; 0.596      ;
+; 0.305 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.704      ; 0.539      ;
+; 0.305 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.762      ; 0.597      ;
+; 0.306 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.691      ; 0.527      ;
+; 0.308 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.700      ; 0.538      ;
+; 0.309 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.698      ; 0.537      ;
+; 0.311 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.534      ;
+; 0.312 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.535      ;
+; 0.312 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.535      ;
+; 0.314 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.537      ;
+; 0.316 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.704      ; 0.550      ;
+; 0.318 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.730      ; 0.578      ;
+; 0.319 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.700      ; 0.549      ;
+; 0.323 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.755      ; 0.608      ;
+; 0.326 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.714      ; 0.570      ;
+; 0.327 ; counter:timeCount|c2[2] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.687      ; 0.544      ;
+; 0.335 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.727      ; 0.592      ;
+; 0.336 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.730      ; 0.596      ;
+; 0.341 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.704      ; 0.575      ;
+; 0.341 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.713      ; 0.584      ;
+; 0.344 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.761      ; 0.635      ;
+; 0.348 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.720      ; 0.598      ;
+; 0.352 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.719      ; 0.601      ;
+; 0.353 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.763      ; 0.646      ;
+; 0.355 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.720      ; 0.605      ;
+; 0.356 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.755      ; 0.641      ;
+; 0.358 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.758      ; 0.646      ;
+; 0.359 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.719      ; 0.608      ;
+; 0.362 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.715      ; 0.607      ;
+; 0.363 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.761      ; 0.654      ;
+; 0.363 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.586      ;
+; 0.364 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.587      ;
+; 0.365 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.588      ;
+; 0.366 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.704      ; 0.600      ;
+; 0.371 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.730      ; 0.631      ;
+; 0.372 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.595      ;
+; 0.373 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.730      ; 0.633      ;
+; 0.373 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.730      ; 0.633      ;
+; 0.375 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.691      ; 0.596      ;
+; 0.377 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.700      ; 0.607      ;
+; 0.378 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.727      ; 0.635      ;
+; 0.380 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.687      ; 0.597      ;
+; 0.381 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.719      ; 0.630      ;
+; 0.381 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.698      ; 0.609      ;
+; 0.383 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.713      ; 0.626      ;
+; 0.383 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.698      ; 0.611      ;
+; 0.384 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.755      ; 0.669      ;
+; 0.384 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.715      ; 0.629      ;
+; 0.385 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.719      ; 0.634      ;
+; 0.385 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.763      ; 0.678      ;
+; 0.386 ; counter:timeCount|c3[0] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.719      ; 0.635      ;
+; 0.387 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.713      ; 0.630      ;
+; 0.388 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.715      ; 0.633      ;
+; 0.390 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.763      ; 0.683      ;
+; 0.391 ; counter:timeCount|c0[0] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.729      ; 0.650      ;
+; 0.392 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.720      ; 0.642      ;
+; 0.392 ; counter:timeCount|c0[2] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.729      ; 0.651      ;
+; 0.393 ; counter:timeCount|c0[3] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.725      ; 0.648      ;
+; 0.394 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.727      ; 0.651      ;
+; 0.397 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.729      ; 0.656      ;
+; 0.401 ; counter:timeCount|c0[1] ; dec_to_seven_segment:dss0|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.725      ; 0.656      ;
+; 0.408 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.714      ; 0.652      ;
+; 0.409 ; counter:timeCount|c3[1] ; dec_to_seven_segment:dss3|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.719      ; 0.658      ;
+; 0.410 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.691      ; 0.631      ;
+; 0.410 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.633      ;
+; 0.412 ; counter:timeCount|c3[2] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.758      ; 0.700      ;
+; 0.412 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.635      ;
+; 0.413 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.636      ;
+; 0.413 ; counter:timeCount|c3[3] ; dec_to_seven_segment:dss3|out[0] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.758      ; 0.701      ;
+; 0.414 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.720      ; 0.664      ;
+; 0.416 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.687      ; 0.633      ;
+; 0.416 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.687      ; 0.633      ;
+; 0.417 ; counter:timeCount|c2[1] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.704      ; 0.651      ;
+; 0.417 ; counter:timeCount|c1[1] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.698      ; 0.645      ;
+; 0.418 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[5] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.720      ; 0.668      ;
+; 0.418 ; counter:timeCount|c1[0] ; dec_to_seven_segment:dss1|out[4] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.704      ; 0.652      ;
+; 0.421 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[2] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.698      ; 0.649      ;
+; 0.422 ; counter:timeCount|c1[3] ; dec_to_seven_segment:dss1|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.720      ; 0.672      ;
+; 0.422 ; counter:timeCount|c1[2] ; dec_to_seven_segment:dss1|out[3] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.698      ; 0.650      ;
+; 0.423 ; counter:timeCount|c2[0] ; dec_to_seven_segment:dss2|out[6] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.704      ; 0.657      ;
+; 0.423 ; counter:timeCount|c2[3] ; dec_to_seven_segment:dss2|out[1] ; hundred_hertz_clock:clockConv|clock_out ; button2     ; -0.500       ; 0.693      ; 0.646      ;
++-------+-------------------------+----------------------------------+-----------------------------------------+-------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'hundred_hertz_clock:clockConv|clock_out'                                                                                                                   ;
++-------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+; Slack ; From Node               ; To Node                 ; Launch Clock                            ; Latch Clock                             ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+; 0.188 ; counter:timeCount|c3[1] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; counter:timeCount|c2[1] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; counter:timeCount|c1[1] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; counter:timeCount|c0[1] ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; counter:timeCount|c0[2] ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; counter:timeCount|c0[3] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.307      ;
+; 0.195 ; counter:timeCount|c3[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; counter:timeCount|c2[0] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; counter:timeCount|c1[0] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; counter:timeCount|c0[0] ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.314      ;
+; 0.345 ; counter:timeCount|c3[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.464      ;
+; 0.366 ; counter:timeCount|c2[0] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.485      ;
+; 0.395 ; counter:timeCount|c0[2] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.514      ;
+; 0.411 ; counter:timeCount|c1[0] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.530      ;
+; 0.412 ; counter:timeCount|c0[0] ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.531      ;
+; 0.444 ; counter:timeCount|c0[2] ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.563      ;
+; 0.453 ; counter:timeCount|en    ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.572      ;
+; 0.457 ; counter:timeCount|en    ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.576      ;
+; 0.458 ; counter:timeCount|en    ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.577      ;
+; 0.505 ; counter:timeCount|c2[2] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.624      ;
+; 0.519 ; counter:timeCount|c1[2] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.638      ;
+; 0.548 ; counter:timeCount|c0[3] ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.667      ;
+; 0.562 ; counter:timeCount|c2[3] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.681      ;
+; 0.565 ; counter:timeCount|en    ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.684      ;
+; 0.571 ; counter:timeCount|c0[1] ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.690      ;
+; 0.571 ; counter:timeCount|c3[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.690      ;
+; 0.572 ; counter:timeCount|c2[2] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.691      ;
+; 0.575 ; counter:timeCount|c3[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.694      ;
+; 0.575 ; counter:timeCount|c3[3] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.694      ;
+; 0.578 ; counter:timeCount|c2[2] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.697      ;
+; 0.579 ; counter:timeCount|c2[2] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.698      ;
+; 0.586 ; counter:timeCount|c0[2] ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.705      ;
+; 0.587 ; counter:timeCount|c1[0] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.706      ;
+; 0.590 ; counter:timeCount|c1[0] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.709      ;
+; 0.592 ; counter:timeCount|c2[3] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.711      ;
+; 0.593 ; counter:timeCount|c2[3] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.712      ;
+; 0.595 ; counter:timeCount|en    ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 0.715      ;
+; 0.600 ; counter:timeCount|en    ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 0.720      ;
+; 0.604 ; counter:timeCount|c2[3] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.723      ;
+; 0.615 ; counter:timeCount|c2[0] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.734      ;
+; 0.616 ; counter:timeCount|c2[1] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.735      ;
+; 0.620 ; counter:timeCount|c0[0] ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.739      ;
+; 0.621 ; counter:timeCount|c1[2] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.740      ;
+; 0.631 ; counter:timeCount|c1[3] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.750      ;
+; 0.637 ; counter:timeCount|c3[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.756      ;
+; 0.643 ; counter:timeCount|en    ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 0.763      ;
+; 0.645 ; counter:timeCount|c3[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.764      ;
+; 0.646 ; counter:timeCount|en    ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 0.766      ;
+; 0.648 ; counter:timeCount|c3[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.767      ;
+; 0.648 ; counter:timeCount|c3[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.767      ;
+; 0.652 ; counter:timeCount|en    ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 0.772      ;
+; 0.658 ; counter:timeCount|en    ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 0.778      ;
+; 0.658 ; counter:timeCount|c1[3] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.777      ;
+; 0.661 ; counter:timeCount|c1[3] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.780      ;
+; 0.662 ; counter:timeCount|c1[3] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.781      ;
+; 0.663 ; counter:timeCount|c3[1] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.782      ;
+; 0.666 ; counter:timeCount|c3[1] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.785      ;
+; 0.670 ; counter:timeCount|c2[0] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.789      ;
+; 0.680 ; counter:timeCount|c0[1] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.799      ;
+; 0.686 ; counter:timeCount|c0[3] ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.805      ;
+; 0.687 ; counter:timeCount|c1[1] ; counter:timeCount|c1[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.806      ;
+; 0.693 ; counter:timeCount|c1[1] ; counter:timeCount|c1[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.812      ;
+; 0.701 ; counter:timeCount|en    ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 0.821      ;
+; 0.705 ; counter:timeCount|en    ; counter:timeCount|en    ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.824      ;
+; 0.721 ; counter:timeCount|c0[1] ; counter:timeCount|c0[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.840      ;
+; 0.726 ; counter:timeCount|c2[1] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.845      ;
+; 0.727 ; counter:timeCount|c2[1] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.846      ;
+; 0.729 ; counter:timeCount|c0[0] ; counter:timeCount|c0[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.848      ;
+; 0.740 ; counter:timeCount|c0[3] ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.859      ;
+; 0.747 ; counter:timeCount|c1[2] ; counter:timeCount|c1[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.866      ;
+; 0.751 ; counter:timeCount|c1[2] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.870      ;
+; 0.753 ; counter:timeCount|en    ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 0.873      ;
+; 0.755 ; counter:timeCount|en    ; counter:timeCount|c0[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 0.875      ;
+; 0.755 ; counter:timeCount|c1[1] ; counter:timeCount|c1[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.874      ;
+; 0.761 ; counter:timeCount|en    ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 0.881      ;
+; 0.777 ; counter:timeCount|en    ; counter:timeCount|c0[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 0.897      ;
+; 0.786 ; counter:timeCount|c3[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.905      ;
+; 0.791 ; counter:timeCount|c3[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.910      ;
+; 0.848 ; counter:timeCount|c3[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.967      ;
+; 0.872 ; counter:timeCount|c3[1] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 0.991      ;
+; 1.014 ; counter:timeCount|c1[0] ; counter:timeCount|c2[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.034      ; 1.132      ;
+; 1.014 ; counter:timeCount|c1[0] ; counter:timeCount|c2[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.034      ; 1.132      ;
+; 1.014 ; counter:timeCount|c1[0] ; counter:timeCount|c2[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.034      ; 1.132      ;
+; 1.014 ; counter:timeCount|c1[0] ; counter:timeCount|c2[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.034      ; 1.132      ;
+; 1.062 ; counter:timeCount|c0[0] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 1.181      ;
+; 1.062 ; counter:timeCount|c0[0] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 1.181      ;
+; 1.062 ; counter:timeCount|c0[0] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 1.181      ;
+; 1.062 ; counter:timeCount|c0[0] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 1.181      ;
+; 1.064 ; counter:timeCount|c0[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 1.183      ;
+; 1.064 ; counter:timeCount|c0[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 1.183      ;
+; 1.064 ; counter:timeCount|c0[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 1.183      ;
+; 1.064 ; counter:timeCount|c0[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.035      ; 1.183      ;
+; 1.067 ; counter:timeCount|en    ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 1.187      ;
+; 1.067 ; counter:timeCount|c2[2] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 1.187      ;
+; 1.067 ; counter:timeCount|c2[2] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 1.187      ;
+; 1.067 ; counter:timeCount|c2[2] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 1.187      ;
+; 1.067 ; counter:timeCount|c2[2] ; counter:timeCount|c3[1] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 1.187      ;
+; 1.083 ; counter:timeCount|c2[3] ; counter:timeCount|c3[0] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 1.203      ;
+; 1.083 ; counter:timeCount|c2[3] ; counter:timeCount|c3[3] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 1.203      ;
+; 1.083 ; counter:timeCount|c2[3] ; counter:timeCount|c3[2] ; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 0.000        ; 0.036      ; 1.203      ;
++-------+-------------------------+-------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'clk'                                                                          ;
++--------+--------------+----------------+------------------+-------+------------+-----------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock ; Clock Edge ; Target                                  ;
++--------+--------------+----------------+------------------+-------+------------+-----------------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; clk   ; Rise       ; clk                                     ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[0]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[10]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[11]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[12]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[13]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[14]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[15]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[16]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[17]   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[1]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[2]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[3]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[4]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[5]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[6]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[7]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[8]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[9]    ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; clk   ; Rise       ; hundred_hertz_clock:clockConv|start     ;
+; -0.085 ; 0.099        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; -0.085 ; 0.099        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|start     ;
+; -0.084 ; 0.100        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[0]    ;
+; -0.084 ; 0.100        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[1]    ;
+; -0.084 ; 0.100        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[7]    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[10]   ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[11]   ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[12]   ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[13]   ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[14]   ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[15]   ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[16]   ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[17]   ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[2]    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[3]    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[4]    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[5]    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[6]    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[8]    ;
+; -0.056 ; 0.128        ; 0.184          ; Low Pulse Width  ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[9]    ;
+; 0.095  ; 0.095        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|clock_out|clk                 ;
+; 0.095  ; 0.095        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|start|clk                     ;
+; 0.096  ; 0.096        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[0]|clk                    ;
+; 0.096  ; 0.096        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[1]|clk                    ;
+; 0.096  ; 0.096        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[7]|clk                    ;
+; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|o                             ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[2]|clk                    ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[3]|clk                    ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[4]|clk                    ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[5]|clk                    ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[6]|clk                    ;
+; 0.123  ; 0.123        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[8]|clk                    ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[10]|clk                   ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[11]|clk                   ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[12]|clk                   ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[13]|clk                   ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[14]|clk                   ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[15]|clk                   ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[16]|clk                   ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[17]|clk                   ;
+; 0.124  ; 0.124        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clockConv|ctr[9]|clk                    ;
+; 0.132  ; 0.132        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~inputclkctrl|inclk[0]               ;
+; 0.132  ; 0.132        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~inputclkctrl|outclk                 ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~input|i                             ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; clk   ; Rise       ; clk~input|i                             ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[10]   ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[11]   ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[12]   ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[13]   ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[14]   ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[15]   ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[16]   ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[17]   ;
+; 0.654  ; 0.870        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[9]    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[2]    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[3]    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[4]    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[5]    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[6]    ;
+; 0.655  ; 0.871        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[8]    ;
+; 0.682  ; 0.898        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; 0.682  ; 0.898        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[0]    ;
+; 0.682  ; 0.898        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[1]    ;
+; 0.682  ; 0.898        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|ctr[7]    ;
+; 0.682  ; 0.898        ; 0.216          ; High Pulse Width ; clk   ; Rise       ; hundred_hertz_clock:clockConv|start     ;
+; 0.867  ; 0.867        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~inputclkctrl|inclk[0]               ;
+; 0.867  ; 0.867        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clk~inputclkctrl|outclk                 ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[10]|clk                   ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[11]|clk                   ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[12]|clk                   ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[13]|clk                   ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[14]|clk                   ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[15]|clk                   ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[16]|clk                   ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[17]|clk                   ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[2]|clk                    ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[3]|clk                    ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[4]|clk                    ;
+; 0.876  ; 0.876        ; 0.000          ; High Pulse Width ; clk   ; Rise       ; clockConv|ctr[5]|clk                    ;
++--------+--------------+----------------+------------------+-------+------------+-----------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'button2'                                                                 ;
++--------+--------------+----------------+------------------+---------+------------+----------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                           ;
++--------+--------------+----------------+------------------+---------+------------+----------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; button2 ; Rise       ; button2                          ;
+; -0.016 ; -0.016       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[4] ;
+; -0.015 ; -0.015       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[1]|datad                ;
+; -0.015 ; -0.015       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[3]|datad                ;
+; -0.014 ; -0.014       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[2]|datad                ;
+; -0.014 ; -0.014       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[6]|datad                ;
+; -0.014 ; -0.014       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[3]|datad                ;
+; -0.014 ; -0.014       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[4]|datad                ;
+; -0.013 ; -0.013       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[4] ;
+; -0.013 ; -0.013       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[4]|datac                ;
+; -0.012 ; -0.012       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[5] ;
+; -0.012 ; -0.012       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[6] ;
+; -0.012 ; -0.012       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[2] ;
+; -0.012 ; -0.012       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[1]|datad                ;
+; -0.012 ; -0.012       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[5]|datad                ;
+; -0.011 ; -0.011       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[0] ;
+; -0.011 ; -0.011       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[6]|datad                ;
+; -0.010 ; -0.010       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[0] ;
+; -0.010 ; -0.010       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[1] ;
+; -0.010 ; -0.010       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[3] ;
+; -0.009 ; -0.009       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[2] ;
+; -0.009 ; -0.009       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[6] ;
+; -0.009 ; -0.009       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[2] ;
+; -0.009 ; -0.009       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[5] ;
+; -0.009 ; -0.009       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[3] ;
+; -0.009 ; -0.009       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[4] ;
+; -0.009 ; -0.009       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[5]|datac                ;
+; -0.009 ; -0.009       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[2]|datac                ;
+; -0.008 ; -0.008       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[1] ;
+; -0.008 ; -0.008       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[3] ;
+; -0.007 ; -0.007       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[0] ;
+; -0.007 ; -0.007       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[1] ;
+; -0.007 ; -0.007       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[2] ;
+; -0.007 ; -0.007       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[3] ;
+; -0.007 ; -0.007       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[1] ;
+; -0.007 ; -0.007       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[5] ;
+; -0.007 ; -0.007       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss0|out[0]|datac                ;
+; -0.006 ; -0.006       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[6] ;
+; -0.006 ; -0.006       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[6] ;
+; -0.005 ; -0.005       ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[0] ;
+; -0.005 ; -0.005       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[4]|dataa                ;
+; -0.004 ; -0.004       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[5]|dataa                ;
+; -0.003 ; -0.003       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[0]|dataa                ;
+; -0.003 ; -0.003       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[1]|dataa                ;
+; -0.003 ; -0.003       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[6]|dataa                ;
+; -0.002 ; -0.002       ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss3|out[0]|datac                ;
+; 0.000  ; 0.000        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[4] ;
+; 0.001  ; 0.001        ; 0.000          ; High Pulse Width ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[5] ;
+; 0.001  ; 0.001        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[2]|datab                ;
+; 0.001  ; 0.001        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[0]|dataa                ;
+; 0.001  ; 0.001        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[1]|dataa                ;
+; 0.001  ; 0.001        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[2]|dataa                ;
+; 0.001  ; 0.001        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[3]|dataa                ;
+; 0.002  ; 0.002        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss1|out[3]|datab                ;
+; 0.005  ; 0.005        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[4]|datab                ;
+; 0.005  ; 0.005        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[6]|datab                ;
+; 0.006  ; 0.006        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; dss2|out[5]|datab                ;
+; 0.118  ; 0.118        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; button2~input|o                  ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; button2~input|i                  ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; button2 ; Rise       ; button2~input|i                  ;
+; 0.882  ; 0.882        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; button2~input|o                  ;
+; 0.987  ; 0.987        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[4] ;
+; 0.987  ; 0.987        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[5] ;
+; 0.992  ; 0.992        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[4]|datab                ;
+; 0.992  ; 0.992        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[5]|datab                ;
+; 0.992  ; 0.992        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[6]|datab                ;
+; 0.993  ; 0.993        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[2] ;
+; 0.993  ; 0.993        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[3] ;
+; 0.994  ; 0.994        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[6] ;
+; 0.995  ; 0.995        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss1|out[2]|datab                ;
+; 0.995  ; 0.995        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss1|out[3]|datab                ;
+; 0.996  ; 0.996        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[0]|dataa                ;
+; 0.996  ; 0.996        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[2]|dataa                ;
+; 0.997  ; 0.997        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[0] ;
+; 0.997  ; 0.997        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[2] ;
+; 0.997  ; 0.997        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[1]|dataa                ;
+; 0.997  ; 0.997        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss2|out[3]|dataa                ;
+; 0.998  ; 0.998        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[1] ;
+; 0.998  ; 0.998        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[1] ;
+; 0.998  ; 0.998        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss2|out[3] ;
+; 0.999  ; 0.999        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[5] ;
+; 0.999  ; 0.999        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss1|out[6]|dataa                ;
+; 0.999  ; 0.999        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss3|out[0]|datac                ;
+; 1.000  ; 1.000        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss1|out[0]|dataa                ;
+; 1.000  ; 1.000        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss1|out[1]|dataa                ;
+; 1.001  ; 1.001        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[0] ;
+; 1.001  ; 1.001        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss1|out[5]|dataa                ;
+; 1.002  ; 1.002        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[0] ;
+; 1.002  ; 1.002        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss1|out[4]|dataa                ;
+; 1.003  ; 1.003        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[4] ;
+; 1.004  ; 1.004        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss1|out[6] ;
+; 1.004  ; 1.004        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[1] ;
+; 1.004  ; 1.004        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[6] ;
+; 1.004  ; 1.004        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[0]|datac                ;
+; 1.005  ; 1.005        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[5] ;
+; 1.006  ; 1.006        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[2] ;
+; 1.006  ; 1.006        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss3|out[3] ;
+; 1.006  ; 1.006        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss0|out[5]|datac                ;
+; 1.006  ; 1.006        ; 0.000          ; High Pulse Width ; button2 ; Rise       ; dss3|out[2]|datac                ;
+; 1.007  ; 1.007        ; 0.000          ; Low Pulse Width  ; button2 ; Fall       ; dec_to_seven_segment:dss0|out[0] ;
++--------+--------------+----------------+------------------+---------+------------+----------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'hundred_hertz_clock:clockConv|clock_out'                                                                     ;
++--------+--------------+----------------+------------------+-----------------------------------------+------------+--------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                   ; Clock Edge ; Target                               ;
++--------+--------------+----------------+------------------+-----------------------------------------+------------+--------------------------------------+
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[0]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[1]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[2]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[3]              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|en                 ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[0]              ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[1]              ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[2]              ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[3]              ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[0]              ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[1]              ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[2]              ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[3]              ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[0]              ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[1]              ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[2]              ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[3]              ;
+; 0.268  ; 0.452        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|en                 ;
+; 0.269  ; 0.453        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[0]              ;
+; 0.269  ; 0.453        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[1]              ;
+; 0.269  ; 0.453        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[2]              ;
+; 0.269  ; 0.453        ; 0.184          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[3]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[0]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[1]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[2]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c0[3]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[0]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[1]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[2]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c1[3]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[0]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[1]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[2]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c2[3]              ;
+; 0.327  ; 0.543        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|en                 ;
+; 0.328  ; 0.544        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[0]              ;
+; 0.328  ; 0.544        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[1]              ;
+; 0.328  ; 0.544        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[2]              ;
+; 0.328  ; 0.544        ; 0.216          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; counter:timeCount|c3[3]              ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[0]|clk                  ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[1]|clk                  ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[2]|clk                  ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[3]|clk                  ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[0]|clk                  ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[1]|clk                  ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[2]|clk                  ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[3]|clk                  ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[0]|clk                  ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[1]|clk                  ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[2]|clk                  ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[3]|clk                  ;
+; 0.448  ; 0.448        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|en|clk                     ;
+; 0.449  ; 0.449        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[0]|clk                  ;
+; 0.449  ; 0.449        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[1]|clk                  ;
+; 0.449  ; 0.449        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[2]|clk                  ;
+; 0.449  ; 0.449        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[3]|clk                  ;
+; 0.456  ; 0.456        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out~clkctrl|inclk[0] ;
+; 0.456  ; 0.456        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out~clkctrl|outclk   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out|q                ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out|q                ;
+; 0.542  ; 0.542        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out~clkctrl|inclk[0] ;
+; 0.542  ; 0.542        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; clockConv|clock_out~clkctrl|outclk   ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[0]|clk                  ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[1]|clk                  ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[2]|clk                  ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c0[3]|clk                  ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[0]|clk                  ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[1]|clk                  ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[2]|clk                  ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c1[3]|clk                  ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[0]|clk                  ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[1]|clk                  ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[2]|clk                  ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c2[3]|clk                  ;
+; 0.549  ; 0.549        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|en|clk                     ;
+; 0.550  ; 0.550        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[0]|clk                  ;
+; 0.550  ; 0.550        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[1]|clk                  ;
+; 0.550  ; 0.550        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[2]|clk                  ;
+; 0.550  ; 0.550        ; 0.000          ; High Pulse Width ; hundred_hertz_clock:clockConv|clock_out ; Rise       ; timeCount|c3[3]|clk                  ;
++--------+--------------+----------------+------------------+-----------------------------------------+------------+--------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                                ;
++-----------+-----------------------------------------+-------+-------+------------+-----------------------------------------+
+; Data Port ; Clock Port                              ; Rise  ; Fall  ; Clock Edge ; Clock Reference                         ;
++-----------+-----------------------------------------+-------+-------+------------+-----------------------------------------+
+; button1   ; clk                                     ; 1.907 ; 2.511 ; Rise       ; clk                                     ;
+; button0   ; hundred_hertz_clock:clockConv|clock_out ; 2.483 ; 3.062 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; button1   ; hundred_hertz_clock:clockConv|clock_out ; 2.183 ; 2.890 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
++-----------+-----------------------------------------+-------+-------+------------+-----------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                                   ;
++-----------+-----------------------------------------+--------+--------+------------+-----------------------------------------+
+; Data Port ; Clock Port                              ; Rise   ; Fall   ; Clock Edge ; Clock Reference                         ;
++-----------+-----------------------------------------+--------+--------+------------+-----------------------------------------+
+; button1   ; clk                                     ; -0.817 ; -1.429 ; Rise       ; clk                                     ;
+; button0   ; hundred_hertz_clock:clockConv|clock_out ; -1.397 ; -2.009 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; button1   ; hundred_hertz_clock:clockConv|clock_out ; -1.196 ; -1.844 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
++-----------+-----------------------------------------+--------+--------+------------+-----------------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; hex0[*]   ; button2    ; 3.805 ; 3.851 ; Fall       ; button2         ;
+;  hex0[0]  ; button2    ; 3.792 ; 3.831 ; Fall       ; button2         ;
+;  hex0[1]  ; button2    ; 3.805 ; 3.851 ; Fall       ; button2         ;
+;  hex0[2]  ; button2    ; 3.522 ; 3.534 ; Fall       ; button2         ;
+;  hex0[3]  ; button2    ; 3.528 ; 3.539 ; Fall       ; button2         ;
+;  hex0[4]  ; button2    ; 3.659 ; 3.678 ; Fall       ; button2         ;
+;  hex0[5]  ; button2    ; 3.540 ; 3.553 ; Fall       ; button2         ;
+;  hex0[6]  ; button2    ; 3.618 ; 3.639 ; Fall       ; button2         ;
+; hex1[*]   ; button2    ; 3.791 ; 3.847 ; Fall       ; button2         ;
+;  hex1[0]  ; button2    ; 3.654 ; 3.695 ; Fall       ; button2         ;
+;  hex1[1]  ; button2    ; 3.694 ; 3.734 ; Fall       ; button2         ;
+;  hex1[2]  ; button2    ; 3.660 ; 3.688 ; Fall       ; button2         ;
+;  hex1[3]  ; button2    ; 3.667 ; 3.699 ; Fall       ; button2         ;
+;  hex1[4]  ; button2    ; 3.791 ; 3.847 ; Fall       ; button2         ;
+;  hex1[5]  ; button2    ; 3.655 ; 3.685 ; Fall       ; button2         ;
+;  hex1[6]  ; button2    ; 3.659 ; 3.685 ; Fall       ; button2         ;
+; hex2[*]   ; button2    ; 3.836 ; 3.888 ; Fall       ; button2         ;
+;  hex2[0]  ; button2    ; 3.613 ; 3.641 ; Fall       ; button2         ;
+;  hex2[1]  ; button2    ; 3.608 ; 3.637 ; Fall       ; button2         ;
+;  hex2[2]  ; button2    ; 3.504 ; 3.520 ; Fall       ; button2         ;
+;  hex2[3]  ; button2    ; 3.624 ; 3.653 ; Fall       ; button2         ;
+;  hex2[4]  ; button2    ; 3.627 ; 3.655 ; Fall       ; button2         ;
+;  hex2[5]  ; button2    ; 3.640 ; 3.671 ; Fall       ; button2         ;
+;  hex2[6]  ; button2    ; 3.836 ; 3.888 ; Fall       ; button2         ;
+; hex3[*]   ; button2    ; 3.919 ; 3.980 ; Fall       ; button2         ;
+;  hex3[0]  ; button2    ; 3.779 ; 3.808 ; Fall       ; button2         ;
+;  hex3[1]  ; button2    ; 3.919 ; 3.980 ; Fall       ; button2         ;
+;  hex3[2]  ; button2    ; 3.778 ; 3.811 ; Fall       ; button2         ;
+;  hex3[3]  ; button2    ; 3.765 ; 3.790 ; Fall       ; button2         ;
+;  hex3[4]  ; button2    ; 3.856 ; 3.899 ; Fall       ; button2         ;
+;  hex3[5]  ; button2    ; 3.844 ; 3.892 ; Fall       ; button2         ;
+;  hex3[6]  ; button2    ; 3.823 ; 3.873 ; Fall       ; button2         ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; hex0[*]   ; button2    ; 3.463 ; 3.474 ; Fall       ; button2         ;
+;  hex0[0]  ; button2    ; 3.721 ; 3.758 ; Fall       ; button2         ;
+;  hex0[1]  ; button2    ; 3.734 ; 3.779 ; Fall       ; button2         ;
+;  hex0[2]  ; button2    ; 3.463 ; 3.474 ; Fall       ; button2         ;
+;  hex0[3]  ; button2    ; 3.469 ; 3.479 ; Fall       ; button2         ;
+;  hex0[4]  ; button2    ; 3.594 ; 3.612 ; Fall       ; button2         ;
+;  hex0[5]  ; button2    ; 3.479 ; 3.491 ; Fall       ; button2         ;
+;  hex0[6]  ; button2    ; 3.555 ; 3.574 ; Fall       ; button2         ;
+; hex1[*]   ; button2    ; 3.575 ; 3.603 ; Fall       ; button2         ;
+;  hex1[0]  ; button2    ; 3.575 ; 3.615 ; Fall       ; button2         ;
+;  hex1[1]  ; button2    ; 3.614 ; 3.651 ; Fall       ; button2         ;
+;  hex1[2]  ; button2    ; 3.577 ; 3.603 ; Fall       ; button2         ;
+;  hex1[3]  ; button2    ; 3.584 ; 3.615 ; Fall       ; button2         ;
+;  hex1[4]  ; button2    ; 3.707 ; 3.760 ; Fall       ; button2         ;
+;  hex1[5]  ; button2    ; 3.576 ; 3.604 ; Fall       ; button2         ;
+;  hex1[6]  ; button2    ; 3.584 ; 3.608 ; Fall       ; button2         ;
+; hex2[*]   ; button2    ; 3.431 ; 3.447 ; Fall       ; button2         ;
+;  hex2[0]  ; button2    ; 3.536 ; 3.562 ; Fall       ; button2         ;
+;  hex2[1]  ; button2    ; 3.533 ; 3.560 ; Fall       ; button2         ;
+;  hex2[2]  ; button2    ; 3.431 ; 3.447 ; Fall       ; button2         ;
+;  hex2[3]  ; button2    ; 3.547 ; 3.575 ; Fall       ; button2         ;
+;  hex2[4]  ; button2    ; 3.547 ; 3.574 ; Fall       ; button2         ;
+;  hex2[5]  ; button2    ; 3.561 ; 3.590 ; Fall       ; button2         ;
+;  hex2[6]  ; button2    ; 3.750 ; 3.799 ; Fall       ; button2         ;
+; hex3[*]   ; button2    ; 3.696 ; 3.720 ; Fall       ; button2         ;
+;  hex3[0]  ; button2    ; 3.709 ; 3.736 ; Fall       ; button2         ;
+;  hex3[1]  ; button2    ; 3.844 ; 3.902 ; Fall       ; button2         ;
+;  hex3[2]  ; button2    ; 3.710 ; 3.741 ; Fall       ; button2         ;
+;  hex3[3]  ; button2    ; 3.696 ; 3.720 ; Fall       ; button2         ;
+;  hex3[4]  ; button2    ; 3.784 ; 3.824 ; Fall       ; button2         ;
+;  hex3[5]  ; button2    ; 3.771 ; 3.818 ; Fall       ; button2         ;
+;  hex3[6]  ; button2    ; 3.751 ; 3.799 ; Fall       ; button2         ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                                    ;
++------------------------------------------+---------+--------+----------+---------+---------------------+
+; Clock                                    ; Setup   ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------------------------------+---------+--------+----------+---------+---------------------+
+; Worst-case Slack                         ; -2.274  ; -0.504 ; N/A      ; N/A     ; -3.000              ;
+;  button2                                 ; -1.727  ; 0.185  ; N/A      ; N/A     ; -3.000              ;
+;  clk                                     ; -2.274  ; -0.504 ; N/A      ; N/A     ; -3.000              ;
+;  hundred_hertz_clock:clockConv|clock_out ; -1.787  ; 0.188  ; N/A      ; N/A     ; -1.000              ;
+; Design-wide TNS                          ; -98.578 ; -0.504 ; 0.0      ; 0.0     ; -44.676             ;
+;  button2                                 ; -34.724 ; 0.000  ; N/A      ; N/A     ; -3.414              ;
+;  clk                                     ; -38.401 ; -0.504 ; N/A      ; N/A     ; -24.262             ;
+;  hundred_hertz_clock:clockConv|clock_out ; -25.453 ; 0.000  ; N/A      ; N/A     ; -17.000             ;
++------------------------------------------+---------+--------+----------+---------+---------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                                ;
++-----------+-----------------------------------------+-------+-------+------------+-----------------------------------------+
+; Data Port ; Clock Port                              ; Rise  ; Fall  ; Clock Edge ; Clock Reference                         ;
++-----------+-----------------------------------------+-------+-------+------------+-----------------------------------------+
+; button1   ; clk                                     ; 3.367 ; 3.857 ; Rise       ; clk                                     ;
+; button0   ; hundred_hertz_clock:clockConv|clock_out ; 4.454 ; 4.869 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; button1   ; hundred_hertz_clock:clockConv|clock_out ; 3.955 ; 4.458 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
++-----------+-----------------------------------------+-------+-------+------------+-----------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                                   ;
++-----------+-----------------------------------------+--------+--------+------------+-----------------------------------------+
+; Data Port ; Clock Port                              ; Rise   ; Fall   ; Clock Edge ; Clock Reference                         ;
++-----------+-----------------------------------------+--------+--------+------------+-----------------------------------------+
+; button1   ; clk                                     ; -0.817 ; -1.429 ; Rise       ; clk                                     ;
+; button0   ; hundred_hertz_clock:clockConv|clock_out ; -1.397 ; -2.009 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
+; button1   ; hundred_hertz_clock:clockConv|clock_out ; -1.196 ; -1.844 ; Rise       ; hundred_hertz_clock:clockConv|clock_out ;
++-----------+-----------------------------------------+--------+--------+------------+-----------------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; hex0[*]   ; button2    ; 5.900 ; 5.818 ; Fall       ; button2         ;
+;  hex0[0]  ; button2    ; 5.877 ; 5.812 ; Fall       ; button2         ;
+;  hex0[1]  ; button2    ; 5.900 ; 5.818 ; Fall       ; button2         ;
+;  hex0[2]  ; button2    ; 5.389 ; 5.322 ; Fall       ; button2         ;
+;  hex0[3]  ; button2    ; 5.379 ; 5.314 ; Fall       ; button2         ;
+;  hex0[4]  ; button2    ; 5.655 ; 5.589 ; Fall       ; button2         ;
+;  hex0[5]  ; button2    ; 5.427 ; 5.364 ; Fall       ; button2         ;
+;  hex0[6]  ; button2    ; 5.579 ; 5.511 ; Fall       ; button2         ;
+; hex1[*]   ; button2    ; 5.927 ; 5.863 ; Fall       ; button2         ;
+;  hex1[0]  ; button2    ; 5.663 ; 5.606 ; Fall       ; button2         ;
+;  hex1[1]  ; button2    ; 5.736 ; 5.676 ; Fall       ; button2         ;
+;  hex1[2]  ; button2    ; 5.659 ; 5.601 ; Fall       ; button2         ;
+;  hex1[3]  ; button2    ; 5.673 ; 5.603 ; Fall       ; button2         ;
+;  hex1[4]  ; button2    ; 5.927 ; 5.863 ; Fall       ; button2         ;
+;  hex1[5]  ; button2    ; 5.688 ; 5.621 ; Fall       ; button2         ;
+;  hex1[6]  ; button2    ; 5.697 ; 5.635 ; Fall       ; button2         ;
+; hex2[*]   ; button2    ; 6.018 ; 5.928 ; Fall       ; button2         ;
+;  hex2[0]  ; button2    ; 5.595 ; 5.525 ; Fall       ; button2         ;
+;  hex2[1]  ; button2    ; 5.535 ; 5.506 ; Fall       ; button2         ;
+;  hex2[2]  ; button2    ; 5.387 ; 5.330 ; Fall       ; button2         ;
+;  hex2[3]  ; button2    ; 5.615 ; 5.551 ; Fall       ; button2         ;
+;  hex2[4]  ; button2    ; 5.599 ; 5.534 ; Fall       ; button2         ;
+;  hex2[5]  ; button2    ; 5.640 ; 5.575 ; Fall       ; button2         ;
+;  hex2[6]  ; button2    ; 6.018 ; 5.928 ; Fall       ; button2         ;
+; hex3[*]   ; button2    ; 6.130 ; 6.027 ; Fall       ; button2         ;
+;  hex3[0]  ; button2    ; 5.862 ; 5.774 ; Fall       ; button2         ;
+;  hex3[1]  ; button2    ; 6.130 ; 6.027 ; Fall       ; button2         ;
+;  hex3[2]  ; button2    ; 5.852 ; 5.766 ; Fall       ; button2         ;
+;  hex3[3]  ; button2    ; 5.802 ; 5.717 ; Fall       ; button2         ;
+;  hex3[4]  ; button2    ; 5.969 ; 5.871 ; Fall       ; button2         ;
+;  hex3[5]  ; button2    ; 5.969 ; 5.868 ; Fall       ; button2         ;
+;  hex3[6]  ; button2    ; 5.942 ; 5.841 ; Fall       ; button2         ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; hex0[*]   ; button2    ; 3.463 ; 3.474 ; Fall       ; button2         ;
+;  hex0[0]  ; button2    ; 3.721 ; 3.758 ; Fall       ; button2         ;
+;  hex0[1]  ; button2    ; 3.734 ; 3.779 ; Fall       ; button2         ;
+;  hex0[2]  ; button2    ; 3.463 ; 3.474 ; Fall       ; button2         ;
+;  hex0[3]  ; button2    ; 3.469 ; 3.479 ; Fall       ; button2         ;
+;  hex0[4]  ; button2    ; 3.594 ; 3.612 ; Fall       ; button2         ;
+;  hex0[5]  ; button2    ; 3.479 ; 3.491 ; Fall       ; button2         ;
+;  hex0[6]  ; button2    ; 3.555 ; 3.574 ; Fall       ; button2         ;
+; hex1[*]   ; button2    ; 3.575 ; 3.603 ; Fall       ; button2         ;
+;  hex1[0]  ; button2    ; 3.575 ; 3.615 ; Fall       ; button2         ;
+;  hex1[1]  ; button2    ; 3.614 ; 3.651 ; Fall       ; button2         ;
+;  hex1[2]  ; button2    ; 3.577 ; 3.603 ; Fall       ; button2         ;
+;  hex1[3]  ; button2    ; 3.584 ; 3.615 ; Fall       ; button2         ;
+;  hex1[4]  ; button2    ; 3.707 ; 3.760 ; Fall       ; button2         ;
+;  hex1[5]  ; button2    ; 3.576 ; 3.604 ; Fall       ; button2         ;
+;  hex1[6]  ; button2    ; 3.584 ; 3.608 ; Fall       ; button2         ;
+; hex2[*]   ; button2    ; 3.431 ; 3.447 ; Fall       ; button2         ;
+;  hex2[0]  ; button2    ; 3.536 ; 3.562 ; Fall       ; button2         ;
+;  hex2[1]  ; button2    ; 3.533 ; 3.560 ; Fall       ; button2         ;
+;  hex2[2]  ; button2    ; 3.431 ; 3.447 ; Fall       ; button2         ;
+;  hex2[3]  ; button2    ; 3.547 ; 3.575 ; Fall       ; button2         ;
+;  hex2[4]  ; button2    ; 3.547 ; 3.574 ; Fall       ; button2         ;
+;  hex2[5]  ; button2    ; 3.561 ; 3.590 ; Fall       ; button2         ;
+;  hex2[6]  ; button2    ; 3.750 ; 3.799 ; Fall       ; button2         ;
+; hex3[*]   ; button2    ; 3.696 ; 3.720 ; Fall       ; button2         ;
+;  hex3[0]  ; button2    ; 3.709 ; 3.736 ; Fall       ; button2         ;
+;  hex3[1]  ; button2    ; 3.844 ; 3.902 ; Fall       ; button2         ;
+;  hex3[2]  ; button2    ; 3.710 ; 3.741 ; Fall       ; button2         ;
+;  hex3[3]  ; button2    ; 3.696 ; 3.720 ; Fall       ; button2         ;
+;  hex3[4]  ; button2    ; 3.784 ; 3.824 ; Fall       ; button2         ;
+;  hex3[5]  ; button2    ; 3.771 ; 3.818 ; Fall       ; button2         ;
+;  hex3[6]  ; button2    ; 3.751 ; 3.799 ; Fall       ; button2         ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; hex0[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex0[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex0[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex0[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex0[4]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex0[5]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex0[6]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex1[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex1[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex1[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex1[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex1[4]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex1[5]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex1[6]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex2[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex2[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex2[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex2[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex2[4]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex2[5]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex2[6]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex3[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex3[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex3[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex3[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex3[4]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex3[5]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; hex3[6]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; decimal_point ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; button2                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; button0                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; button1                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; clk                     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DATA0~          ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; hex0[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex0[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex0[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex0[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex0[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex0[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex0[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; decimal_point ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.68e-07 V                   ; 2.35 V              ; -0.0132 V           ; 0.2 V                                ; 0.027 V                              ; 5.26e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.68e-07 V                  ; 2.35 V             ; -0.0132 V          ; 0.2 V                               ; 0.027 V                             ; 5.26e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.36e-07 V                   ; 2.35 V              ; -0.00444 V          ; 0.18 V                               ; 0.019 V                              ; 7.23e-10 s                  ; 9.82e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 9.36e-07 V                  ; 2.35 V             ; -0.00444 V         ; 0.18 V                              ; 0.019 V                             ; 7.23e-10 s                 ; 9.82e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; hex0[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex0[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex0[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex0[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex0[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex0[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex0[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex1[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex2[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[4]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[5]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; hex3[6]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; decimal_point ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; ~ALTERA_DCLK~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.22e-08 V                   ; 2.72 V              ; -0.0747 V           ; 0.28 V                               ; 0.169 V                              ; 3.1e-10 s                   ; 3.01e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.22e-08 V                  ; 2.72 V             ; -0.0747 V          ; 0.28 V                              ; 0.169 V                             ; 3.1e-10 s                  ; 3.01e-10 s                 ; No                        ; Yes                       ;
+; ~ALTERA_nCEO~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.53e-08 V                   ; 2.7 V               ; -0.0212 V           ; 0.204 V                              ; 0.049 V                              ; 4.85e-10 s                  ; 6.73e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.53e-08 V                  ; 2.7 V              ; -0.0212 V          ; 0.204 V                             ; 0.049 V                             ; 4.85e-10 s                 ; 6.73e-10 s                 ; No                        ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                                               ;
++-----------------------------------------+-----------------------------------------+----------+----------+----------+----------+
+; From Clock                              ; To Clock                                ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------+-----------------------------------------+----------+----------+----------+----------+
+; hundred_hertz_clock:clockConv|clock_out ; button2                                 ; 0        ; 0        ; 112      ; 0        ;
+; clk                                     ; clk                                     ; 533      ; 0        ; 0        ; 0        ;
+; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; 1        ; 1        ; 0        ; 0        ;
+; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 229      ; 0        ; 0        ; 0        ;
++-----------------------------------------+-----------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                                                ;
++-----------------------------------------+-----------------------------------------+----------+----------+----------+----------+
+; From Clock                              ; To Clock                                ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------+-----------------------------------------+----------+----------+----------+----------+
+; hundred_hertz_clock:clockConv|clock_out ; button2                                 ; 0        ; 0        ; 112      ; 0        ;
+; clk                                     ; clk                                     ; 533      ; 0        ; 0        ; 0        ;
+; hundred_hertz_clock:clockConv|clock_out ; clk                                     ; 1        ; 1        ; 0        ; 0        ;
+; hundred_hertz_clock:clockConv|clock_out ; hundred_hertz_clock:clockConv|clock_out ; 229      ; 0        ; 0        ; 0        ;
++-----------------------------------------+-----------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 2     ; 2    ;
+; Unconstrained Input Port Paths  ; 54    ; 54   ;
+; Unconstrained Output Ports      ; 28    ; 28   ;
+; Unconstrained Output Port Paths ; 28    ; 28   ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Wed Mar 02 15:24:45 2016
+Info: Command: quartus_sta stopclock -c stopclock
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Warning (335093): TimeQuest Timing Analyzer is analyzing 28 combinational loops as latches.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'stopclock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name clk clk
+    Info (332105): create_clock -period 1.000 -name hundred_hertz_clock:clockConv|clock_out hundred_hertz_clock:clockConv|clock_out
+    Info (332105): create_clock -period 1.000 -name button2 button2
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -2.274
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.274             -38.401 clk 
+    Info (332119):    -1.787             -25.453 hundred_hertz_clock:clockConv|clock_out 
+    Info (332119):    -1.727             -34.724 button2 
+Info (332146): Worst-case hold slack is -0.504
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.504              -0.504 clk 
+    Info (332119):     0.359               0.000 hundred_hertz_clock:clockConv|clock_out 
+    Info (332119):     0.615               0.000 button2 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -23.000 clk 
+    Info (332119):    -3.000              -3.000 button2 
+    Info (332119):    -1.000             -17.000 hundred_hertz_clock:clockConv|clock_out 
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.965
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.965             -33.034 clk 
+    Info (332119):    -1.522             -21.435 hundred_hertz_clock:clockConv|clock_out 
+    Info (332119):    -1.393             -27.476 button2 
+Info (332146): Worst-case hold slack is -0.471
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.471              -0.471 clk 
+    Info (332119):     0.312               0.000 hundred_hertz_clock:clockConv|clock_out 
+    Info (332119):     0.519               0.000 button2 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -23.000 clk 
+    Info (332119):    -3.000              -3.000 button2 
+    Info (332119):    -1.000             -17.000 hundred_hertz_clock:clockConv|clock_out 
+Info: Analyzing Fast 1200mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.818
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.818             -12.731 clk 
+    Info (332119):    -0.550              -6.614 hundred_hertz_clock:clockConv|clock_out 
+    Info (332119):    -0.418              -4.063 button2 
+Info (332146): Worst-case hold slack is -0.319
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.319              -0.319 clk 
+    Info (332119):     0.185               0.000 button2 
+    Info (332119):     0.188               0.000 hundred_hertz_clock:clockConv|clock_out 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -24.262 clk 
+    Info (332119):    -3.000              -3.414 button2 
+    Info (332119):    -1.000             -17.000 hundred_hertz_clock:clockConv|clock_out 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 502 megabytes
+    Info: Processing ended: Wed Mar 02 15:24:47 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:03
+
+
diff --git a/stopClockVerilog/output_files/stopclock.sta.summary b/stopClockVerilog/output_files/stopclock.sta.summary
new file mode 100644
index 0000000..7108200
--- /dev/null
+++ b/stopClockVerilog/output_files/stopclock.sta.summary
@@ -0,0 +1,113 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'clk'
+Slack : -2.274
+TNS   : -38.401
+
+Type  : Slow 1200mV 85C Model Setup 'hundred_hertz_clock:clockConv|clock_out'
+Slack : -1.787
+TNS   : -25.453
+
+Type  : Slow 1200mV 85C Model Setup 'button2'
+Slack : -1.727
+TNS   : -34.724
+
+Type  : Slow 1200mV 85C Model Hold 'clk'
+Slack : -0.504
+TNS   : -0.504
+
+Type  : Slow 1200mV 85C Model Hold 'hundred_hertz_clock:clockConv|clock_out'
+Slack : 0.359
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'button2'
+Slack : 0.615
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'clk'
+Slack : -3.000
+TNS   : -23.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'button2'
+Slack : -3.000
+TNS   : -3.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'hundred_hertz_clock:clockConv|clock_out'
+Slack : -1.000
+TNS   : -17.000
+
+Type  : Slow 1200mV 0C Model Setup 'clk'
+Slack : -1.965
+TNS   : -33.034
+
+Type  : Slow 1200mV 0C Model Setup 'hundred_hertz_clock:clockConv|clock_out'
+Slack : -1.522
+TNS   : -21.435
+
+Type  : Slow 1200mV 0C Model Setup 'button2'
+Slack : -1.393
+TNS   : -27.476
+
+Type  : Slow 1200mV 0C Model Hold 'clk'
+Slack : -0.471
+TNS   : -0.471
+
+Type  : Slow 1200mV 0C Model Hold 'hundred_hertz_clock:clockConv|clock_out'
+Slack : 0.312
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'button2'
+Slack : 0.519
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'clk'
+Slack : -3.000
+TNS   : -23.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'button2'
+Slack : -3.000
+TNS   : -3.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'hundred_hertz_clock:clockConv|clock_out'
+Slack : -1.000
+TNS   : -17.000
+
+Type  : Fast 1200mV 0C Model Setup 'clk'
+Slack : -0.818
+TNS   : -12.731
+
+Type  : Fast 1200mV 0C Model Setup 'hundred_hertz_clock:clockConv|clock_out'
+Slack : -0.550
+TNS   : -6.614
+
+Type  : Fast 1200mV 0C Model Setup 'button2'
+Slack : -0.418
+TNS   : -4.063
+
+Type  : Fast 1200mV 0C Model Hold 'clk'
+Slack : -0.319
+TNS   : -0.319
+
+Type  : Fast 1200mV 0C Model Hold 'button2'
+Slack : 0.185
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'hundred_hertz_clock:clockConv|clock_out'
+Slack : 0.188
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'clk'
+Slack : -3.000
+TNS   : -24.262
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'button2'
+Slack : -3.000
+TNS   : -3.414
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'hundred_hertz_clock:clockConv|clock_out'
+Slack : -1.000
+TNS   : -17.000
+
+------------------------------------------------------------
diff --git a/stopClockVerilog/simulation/modelsim/stopclock.sft b/stopClockVerilog/simulation/modelsim/stopclock.sft
new file mode 100644
index 0000000..c6a3418
--- /dev/null
+++ b/stopClockVerilog/simulation/modelsim/stopclock.sft
@@ -0,0 +1,6 @@
+set tool_name "ModelSim-Altera (VHDL)"
+set corner_file_list {
+	{{"Slow -6 1.2V 85 Model"} {stopclock_6_1200mv_85c_slow.vho stopclock_6_1200mv_85c_vhd_slow.sdo}}
+	{{"Slow -6 1.2V 0 Model"} {stopclock_6_1200mv_0c_slow.vho stopclock_6_1200mv_0c_vhd_slow.sdo}}
+	{{"Fast -M 1.2V 0 Model"} {stopclock_min_1200mv_0c_fast.vho stopclock_min_1200mv_0c_vhd_fast.sdo}}
+}
diff --git a/stopClockVerilog/simulation/modelsim/stopclock.vho b/stopClockVerilog/simulation/modelsim/stopclock.vho
new file mode 100644
index 0000000..766487c
--- /dev/null
+++ b/stopClockVerilog/simulation/modelsim/stopclock.vho
@@ -0,0 +1,3227 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "03/02/2016 15:24:50"
+
+-- 
+-- Device: Altera EP3C16U484C6 Package UFBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	stopclock IS
+    PORT (
+	clk : IN std_logic;
+	button0 : IN std_logic;
+	button1 : IN std_logic;
+	button2 : IN std_logic;
+	hex0 : BUFFER std_logic_vector(6 DOWNTO 0);
+	hex1 : BUFFER std_logic_vector(6 DOWNTO 0);
+	hex2 : BUFFER std_logic_vector(6 DOWNTO 0);
+	hex3 : BUFFER std_logic_vector(6 DOWNTO 0);
+	decimal_point : BUFFER std_logic
+	);
+END stopclock;
+
+-- Design Ports Information
+-- hex0[0]	=>  Location: PIN_E11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[1]	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[2]	=>  Location: PIN_H12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[3]	=>  Location: PIN_H13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[4]	=>  Location: PIN_G12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[5]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[6]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[0]	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[1]	=>  Location: PIN_B13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[2]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[3]	=>  Location: PIN_A14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[4]	=>  Location: PIN_B14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[5]	=>  Location: PIN_E14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[6]	=>  Location: PIN_A15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[0]	=>  Location: PIN_D15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[1]	=>  Location: PIN_A16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[2]	=>  Location: PIN_B16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[3]	=>  Location: PIN_E15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[4]	=>  Location: PIN_A17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[5]	=>  Location: PIN_B17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[6]	=>  Location: PIN_F14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[0]	=>  Location: PIN_B18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[1]	=>  Location: PIN_F15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[2]	=>  Location: PIN_A19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[3]	=>  Location: PIN_B19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[4]	=>  Location: PIN_C19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[5]	=>  Location: PIN_D19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[6]	=>  Location: PIN_G15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- decimal_point	=>  Location: PIN_A18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- button2	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- button0	=>  Location: PIN_H2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- button1	=>  Location: PIN_G3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- clk	=>  Location: PIN_G21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF stopclock IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_clk : std_logic;
+SIGNAL ww_button0 : std_logic;
+SIGNAL ww_button1 : std_logic;
+SIGNAL ww_button2 : std_logic;
+SIGNAL ww_hex0 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_hex1 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_hex2 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_hex3 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_decimal_point : std_logic;
+SIGNAL \clockConv|clock_out~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \hex0[0]~output_o\ : std_logic;
+SIGNAL \hex0[1]~output_o\ : std_logic;
+SIGNAL \hex0[2]~output_o\ : std_logic;
+SIGNAL \hex0[3]~output_o\ : std_logic;
+SIGNAL \hex0[4]~output_o\ : std_logic;
+SIGNAL \hex0[5]~output_o\ : std_logic;
+SIGNAL \hex0[6]~output_o\ : std_logic;
+SIGNAL \hex1[0]~output_o\ : std_logic;
+SIGNAL \hex1[1]~output_o\ : std_logic;
+SIGNAL \hex1[2]~output_o\ : std_logic;
+SIGNAL \hex1[3]~output_o\ : std_logic;
+SIGNAL \hex1[4]~output_o\ : std_logic;
+SIGNAL \hex1[5]~output_o\ : std_logic;
+SIGNAL \hex1[6]~output_o\ : std_logic;
+SIGNAL \hex2[0]~output_o\ : std_logic;
+SIGNAL \hex2[1]~output_o\ : std_logic;
+SIGNAL \hex2[2]~output_o\ : std_logic;
+SIGNAL \hex2[3]~output_o\ : std_logic;
+SIGNAL \hex2[4]~output_o\ : std_logic;
+SIGNAL \hex2[5]~output_o\ : std_logic;
+SIGNAL \hex2[6]~output_o\ : std_logic;
+SIGNAL \hex3[0]~output_o\ : std_logic;
+SIGNAL \hex3[1]~output_o\ : std_logic;
+SIGNAL \hex3[2]~output_o\ : std_logic;
+SIGNAL \hex3[3]~output_o\ : std_logic;
+SIGNAL \hex3[4]~output_o\ : std_logic;
+SIGNAL \hex3[5]~output_o\ : std_logic;
+SIGNAL \hex3[6]~output_o\ : std_logic;
+SIGNAL \decimal_point~output_o\ : std_logic;
+SIGNAL \button2~input_o\ : std_logic;
+SIGNAL \clk~input_o\ : std_logic;
+SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
+SIGNAL \button1~input_o\ : std_logic;
+SIGNAL \clockConv|start~0_combout\ : std_logic;
+SIGNAL \clockConv|start~q\ : std_logic;
+SIGNAL \clockConv|ctr[0]~18_combout\ : std_logic;
+SIGNAL \clockConv|ctr[0]~19\ : std_logic;
+SIGNAL \clockConv|ctr[1]~20_combout\ : std_logic;
+SIGNAL \clockConv|ctr[1]~21\ : std_logic;
+SIGNAL \clockConv|ctr[2]~22_combout\ : std_logic;
+SIGNAL \clockConv|ctr[2]~23\ : std_logic;
+SIGNAL \clockConv|ctr[3]~24_combout\ : std_logic;
+SIGNAL \clockConv|ctr[3]~25\ : std_logic;
+SIGNAL \clockConv|ctr[4]~26_combout\ : std_logic;
+SIGNAL \clockConv|ctr[4]~27\ : std_logic;
+SIGNAL \clockConv|ctr[5]~28_combout\ : std_logic;
+SIGNAL \clockConv|ctr[5]~29\ : std_logic;
+SIGNAL \clockConv|ctr[6]~30_combout\ : std_logic;
+SIGNAL \clockConv|ctr[6]~31\ : std_logic;
+SIGNAL \clockConv|ctr[7]~32_combout\ : std_logic;
+SIGNAL \clockConv|ctr[7]~33\ : std_logic;
+SIGNAL \clockConv|ctr[8]~34_combout\ : std_logic;
+SIGNAL \clockConv|ctr[8]~35\ : std_logic;
+SIGNAL \clockConv|ctr[9]~36_combout\ : std_logic;
+SIGNAL \clockConv|ctr[9]~37\ : std_logic;
+SIGNAL \clockConv|ctr[10]~38_combout\ : std_logic;
+SIGNAL \clockConv|ctr[10]~39\ : std_logic;
+SIGNAL \clockConv|ctr[11]~40_combout\ : std_logic;
+SIGNAL \clockConv|ctr[11]~41\ : std_logic;
+SIGNAL \clockConv|ctr[12]~42_combout\ : std_logic;
+SIGNAL \clockConv|ctr[12]~43\ : std_logic;
+SIGNAL \clockConv|ctr[13]~44_combout\ : std_logic;
+SIGNAL \clockConv|ctr[13]~45\ : std_logic;
+SIGNAL \clockConv|ctr[14]~46_combout\ : std_logic;
+SIGNAL \clockConv|ctr[14]~47\ : std_logic;
+SIGNAL \clockConv|ctr[15]~48_combout\ : std_logic;
+SIGNAL \clockConv|ctr[15]~49\ : std_logic;
+SIGNAL \clockConv|ctr[16]~50_combout\ : std_logic;
+SIGNAL \clockConv|ctr[16]~51\ : std_logic;
+SIGNAL \clockConv|ctr[17]~52_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~0_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~3_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~1_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~2_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~4_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~5_combout\ : std_logic;
+SIGNAL \clockConv|clock_out~0_combout\ : std_logic;
+SIGNAL \clockConv|clock_out~feeder_combout\ : std_logic;
+SIGNAL \clockConv|clock_out~q\ : std_logic;
+SIGNAL \clockConv|clock_out~clkctrl_outclk\ : std_logic;
+SIGNAL \button0~input_o\ : std_logic;
+SIGNAL \timeCount|en~q\ : std_logic;
+SIGNAL \timeCount|always0~0_combout\ : std_logic;
+SIGNAL \timeCount|c0~0_combout\ : std_logic;
+SIGNAL \timeCount|c0~1_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~0_combout\ : std_logic;
+SIGNAL \timeCount|Add3~0_combout\ : std_logic;
+SIGNAL \timeCount|c0~2_combout\ : std_logic;
+SIGNAL \timeCount|c0[3]~3_combout\ : std_logic;
+SIGNAL \timeCount|c0~4_combout\ : std_logic;
+SIGNAL \dss0|out~0_combout\ : std_logic;
+SIGNAL \dss0|out~1_combout\ : std_logic;
+SIGNAL \dss0|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr0~0_combout\ : std_logic;
+SIGNAL \timeCount|c1~1_combout\ : std_logic;
+SIGNAL \timeCount|Add2~0_combout\ : std_logic;
+SIGNAL \timeCount|c1~2_combout\ : std_logic;
+SIGNAL \timeCount|Add2~1_combout\ : std_logic;
+SIGNAL \timeCount|c1~3_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~1_combout\ : std_logic;
+SIGNAL \timeCount|c1~0_combout\ : std_logic;
+SIGNAL \dss1|out~0_combout\ : std_logic;
+SIGNAL \dss1|out~1_combout\ : std_logic;
+SIGNAL \dss1|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr0~0_combout\ : std_logic;
+SIGNAL \timeCount|c2~3_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~4_combout\ : std_logic;
+SIGNAL \timeCount|c2~5_combout\ : std_logic;
+SIGNAL \timeCount|Add1~0_combout\ : std_logic;
+SIGNAL \timeCount|c2~6_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~2_combout\ : std_logic;
+SIGNAL \timeCount|Add1~1_combout\ : std_logic;
+SIGNAL \timeCount|c2~7_combout\ : std_logic;
+SIGNAL \dss2|out~0_combout\ : std_logic;
+SIGNAL \dss2|out~1_combout\ : std_logic;
+SIGNAL \dss2|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr0~0_combout\ : std_logic;
+SIGNAL \timeCount|Add0~0_combout\ : std_logic;
+SIGNAL \timeCount|c3~4_combout\ : std_logic;
+SIGNAL \timeCount|c3[1]~2_combout\ : std_logic;
+SIGNAL \timeCount|c3[1]~0_combout\ : std_logic;
+SIGNAL \timeCount|c3~1_combout\ : std_logic;
+SIGNAL \timeCount|c3~3_combout\ : std_logic;
+SIGNAL \timeCount|Add0~1_combout\ : std_logic;
+SIGNAL \timeCount|c3~5_combout\ : std_logic;
+SIGNAL \dss3|out~0_combout\ : std_logic;
+SIGNAL \dss3|out~1_combout\ : std_logic;
+SIGNAL \dss3|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr0~0_combout\ : std_logic;
+SIGNAL \dss1|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \dss2|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \dss3|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \clockConv|ctr\ : std_logic_vector(17 DOWNTO 0);
+SIGNAL \timeCount|c3\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \timeCount|c2\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \timeCount|c1\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \timeCount|c0\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \dss0|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \timeCount|ALT_INV_c0[3]~3_combout\ : std_logic;
+SIGNAL \clockConv|ALT_INV_LessThan0~5_combout\ : std_logic;
+
+BEGIN
+
+ww_clk <= clk;
+ww_button0 <= button0;
+ww_button1 <= button1;
+ww_button2 <= button2;
+hex0 <= ww_hex0;
+hex1 <= ww_hex1;
+hex2 <= ww_hex2;
+hex3 <= ww_hex3;
+decimal_point <= ww_decimal_point;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\clockConv|clock_out~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clockConv|clock_out~q\);
+
+\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);
+\timeCount|ALT_INV_c0[3]~3_combout\ <= NOT \timeCount|c0[3]~3_combout\;
+\clockConv|ALT_INV_LessThan0~5_combout\ <= NOT \clockConv|LessThan0~5_combout\;
+
+-- Location: IOOBUF_X21_Y29_N23
+\hex0[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(0),
+	devoe => ww_devoe,
+	o => \hex0[0]~output_o\);
+
+-- Location: IOOBUF_X21_Y29_N30
+\hex0[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(1),
+	devoe => ww_devoe,
+	o => \hex0[1]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N2
+\hex0[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(2),
+	devoe => ww_devoe,
+	o => \hex0[2]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N30
+\hex0[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(3),
+	devoe => ww_devoe,
+	o => \hex0[3]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N9
+\hex0[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(4),
+	devoe => ww_devoe,
+	o => \hex0[4]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N23
+\hex0[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(5),
+	devoe => ww_devoe,
+	o => \hex0[5]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N16
+\hex0[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(6),
+	devoe => ww_devoe,
+	o => \hex0[6]~output_o\);
+
+-- Location: IOOBUF_X21_Y29_N2
+\hex1[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(0),
+	devoe => ww_devoe,
+	o => \hex1[0]~output_o\);
+
+-- Location: IOOBUF_X21_Y29_N9
+\hex1[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(1),
+	devoe => ww_devoe,
+	o => \hex1[1]~output_o\);
+
+-- Location: IOOBUF_X23_Y29_N2
+\hex1[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(2),
+	devoe => ww_devoe,
+	o => \hex1[2]~output_o\);
+
+-- Location: IOOBUF_X23_Y29_N23
+\hex1[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(3),
+	devoe => ww_devoe,
+	o => \hex1[3]~output_o\);
+
+-- Location: IOOBUF_X23_Y29_N30
+\hex1[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(4),
+	devoe => ww_devoe,
+	o => \hex1[4]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N16
+\hex1[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(5),
+	devoe => ww_devoe,
+	o => \hex1[5]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N23
+\hex1[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(6),
+	devoe => ww_devoe,
+	o => \hex1[6]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N30
+\hex2[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(0),
+	devoe => ww_devoe,
+	o => \hex2[0]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N30
+\hex2[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(1),
+	devoe => ww_devoe,
+	o => \hex2[1]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N2
+\hex2[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(2),
+	devoe => ww_devoe,
+	o => \hex2[2]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N2
+\hex2[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(3),
+	devoe => ww_devoe,
+	o => \hex2[3]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N16
+\hex2[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(4),
+	devoe => ww_devoe,
+	o => \hex2[4]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N23
+\hex2[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(5),
+	devoe => ww_devoe,
+	o => \hex2[5]~output_o\);
+
+-- Location: IOOBUF_X37_Y29_N2
+\hex2[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(6),
+	devoe => ww_devoe,
+	o => \hex2[6]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N23
+\hex3[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(0),
+	devoe => ww_devoe,
+	o => \hex3[0]~output_o\);
+
+-- Location: IOOBUF_X39_Y29_N16
+\hex3[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(1),
+	devoe => ww_devoe,
+	o => \hex3[1]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N9
+\hex3[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(2),
+	devoe => ww_devoe,
+	o => \hex3[2]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N2
+\hex3[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(3),
+	devoe => ww_devoe,
+	o => \hex3[3]~output_o\);
+
+-- Location: IOOBUF_X37_Y29_N23
+\hex3[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(4),
+	devoe => ww_devoe,
+	o => \hex3[4]~output_o\);
+
+-- Location: IOOBUF_X37_Y29_N30
+\hex3[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(5),
+	devoe => ww_devoe,
+	o => \hex3[5]~output_o\);
+
+-- Location: IOOBUF_X39_Y29_N30
+\hex3[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(6),
+	devoe => ww_devoe,
+	o => \hex3[6]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N16
+\decimal_point~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => GND,
+	devoe => ww_devoe,
+	o => \decimal_point~output_o\);
+
+-- Location: IOIBUF_X0_Y23_N1
+\button2~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_button2,
+	o => \button2~input_o\);
+
+-- Location: IOIBUF_X41_Y15_N1
+\clk~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_clk,
+	o => \clk~input_o\);
+
+-- Location: CLKCTRL_G9
+\clk~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \clk~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \clk~inputclkctrl_outclk\);
+
+-- Location: IOIBUF_X0_Y23_N15
+\button1~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_button1,
+	o => \button1~input_o\);
+
+-- Location: LCCOMB_X19_Y27_N26
+\clockConv|start~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|start~0_combout\ = (\clockConv|start~q\) # (!\button1~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001111110011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button1~input_o\,
+	datac => \clockConv|start~q\,
+	combout => \clockConv|start~0_combout\);
+
+-- Location: FF_X19_Y27_N27
+\clockConv|start\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|start~q\);
+
+-- Location: LCCOMB_X19_Y28_N14
+\clockConv|ctr[0]~18\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[0]~18_combout\ = \clockConv|ctr\(0) $ (VCC)
+-- \clockConv|ctr[0]~19\ = CARRY(\clockConv|ctr\(0))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011001111001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(0),
+	datad => VCC,
+	combout => \clockConv|ctr[0]~18_combout\,
+	cout => \clockConv|ctr[0]~19\);
+
+-- Location: FF_X19_Y28_N15
+\clockConv|ctr[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[0]~18_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(0));
+
+-- Location: LCCOMB_X19_Y28_N16
+\clockConv|ctr[1]~20\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[1]~20_combout\ = (\clockConv|ctr\(1) & (!\clockConv|ctr[0]~19\)) # (!\clockConv|ctr\(1) & ((\clockConv|ctr[0]~19\) # (GND)))
+-- \clockConv|ctr[1]~21\ = CARRY((!\clockConv|ctr[0]~19\) # (!\clockConv|ctr\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(1),
+	datad => VCC,
+	cin => \clockConv|ctr[0]~19\,
+	combout => \clockConv|ctr[1]~20_combout\,
+	cout => \clockConv|ctr[1]~21\);
+
+-- Location: FF_X19_Y28_N17
+\clockConv|ctr[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[1]~20_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(1));
+
+-- Location: LCCOMB_X19_Y28_N18
+\clockConv|ctr[2]~22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[2]~22_combout\ = (\clockConv|ctr\(2) & (\clockConv|ctr[1]~21\ $ (GND))) # (!\clockConv|ctr\(2) & (!\clockConv|ctr[1]~21\ & VCC))
+-- \clockConv|ctr[2]~23\ = CARRY((\clockConv|ctr\(2) & !\clockConv|ctr[1]~21\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(2),
+	datad => VCC,
+	cin => \clockConv|ctr[1]~21\,
+	combout => \clockConv|ctr[2]~22_combout\,
+	cout => \clockConv|ctr[2]~23\);
+
+-- Location: FF_X19_Y28_N19
+\clockConv|ctr[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[2]~22_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(2));
+
+-- Location: LCCOMB_X19_Y28_N20
+\clockConv|ctr[3]~24\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[3]~24_combout\ = (\clockConv|ctr\(3) & (!\clockConv|ctr[2]~23\)) # (!\clockConv|ctr\(3) & ((\clockConv|ctr[2]~23\) # (GND)))
+-- \clockConv|ctr[3]~25\ = CARRY((!\clockConv|ctr[2]~23\) # (!\clockConv|ctr\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(3),
+	datad => VCC,
+	cin => \clockConv|ctr[2]~23\,
+	combout => \clockConv|ctr[3]~24_combout\,
+	cout => \clockConv|ctr[3]~25\);
+
+-- Location: FF_X19_Y28_N21
+\clockConv|ctr[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[3]~24_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(3));
+
+-- Location: LCCOMB_X19_Y28_N22
+\clockConv|ctr[4]~26\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[4]~26_combout\ = (\clockConv|ctr\(4) & (\clockConv|ctr[3]~25\ $ (GND))) # (!\clockConv|ctr\(4) & (!\clockConv|ctr[3]~25\ & VCC))
+-- \clockConv|ctr[4]~27\ = CARRY((\clockConv|ctr\(4) & !\clockConv|ctr[3]~25\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(4),
+	datad => VCC,
+	cin => \clockConv|ctr[3]~25\,
+	combout => \clockConv|ctr[4]~26_combout\,
+	cout => \clockConv|ctr[4]~27\);
+
+-- Location: FF_X19_Y28_N23
+\clockConv|ctr[4]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[4]~26_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(4));
+
+-- Location: LCCOMB_X19_Y28_N24
+\clockConv|ctr[5]~28\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[5]~28_combout\ = (\clockConv|ctr\(5) & (!\clockConv|ctr[4]~27\)) # (!\clockConv|ctr\(5) & ((\clockConv|ctr[4]~27\) # (GND)))
+-- \clockConv|ctr[5]~29\ = CARRY((!\clockConv|ctr[4]~27\) # (!\clockConv|ctr\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(5),
+	datad => VCC,
+	cin => \clockConv|ctr[4]~27\,
+	combout => \clockConv|ctr[5]~28_combout\,
+	cout => \clockConv|ctr[5]~29\);
+
+-- Location: FF_X19_Y28_N25
+\clockConv|ctr[5]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[5]~28_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(5));
+
+-- Location: LCCOMB_X19_Y28_N26
+\clockConv|ctr[6]~30\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[6]~30_combout\ = (\clockConv|ctr\(6) & (\clockConv|ctr[5]~29\ $ (GND))) # (!\clockConv|ctr\(6) & (!\clockConv|ctr[5]~29\ & VCC))
+-- \clockConv|ctr[6]~31\ = CARRY((\clockConv|ctr\(6) & !\clockConv|ctr[5]~29\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(6),
+	datad => VCC,
+	cin => \clockConv|ctr[5]~29\,
+	combout => \clockConv|ctr[6]~30_combout\,
+	cout => \clockConv|ctr[6]~31\);
+
+-- Location: FF_X19_Y28_N27
+\clockConv|ctr[6]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[6]~30_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(6));
+
+-- Location: LCCOMB_X19_Y28_N28
+\clockConv|ctr[7]~32\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[7]~32_combout\ = (\clockConv|ctr\(7) & (!\clockConv|ctr[6]~31\)) # (!\clockConv|ctr\(7) & ((\clockConv|ctr[6]~31\) # (GND)))
+-- \clockConv|ctr[7]~33\ = CARRY((!\clockConv|ctr[6]~31\) # (!\clockConv|ctr\(7)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(7),
+	datad => VCC,
+	cin => \clockConv|ctr[6]~31\,
+	combout => \clockConv|ctr[7]~32_combout\,
+	cout => \clockConv|ctr[7]~33\);
+
+-- Location: FF_X19_Y28_N29
+\clockConv|ctr[7]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[7]~32_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(7));
+
+-- Location: LCCOMB_X19_Y28_N30
+\clockConv|ctr[8]~34\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[8]~34_combout\ = (\clockConv|ctr\(8) & (\clockConv|ctr[7]~33\ $ (GND))) # (!\clockConv|ctr\(8) & (!\clockConv|ctr[7]~33\ & VCC))
+-- \clockConv|ctr[8]~35\ = CARRY((\clockConv|ctr\(8) & !\clockConv|ctr[7]~33\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(8),
+	datad => VCC,
+	cin => \clockConv|ctr[7]~33\,
+	combout => \clockConv|ctr[8]~34_combout\,
+	cout => \clockConv|ctr[8]~35\);
+
+-- Location: FF_X19_Y28_N31
+\clockConv|ctr[8]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[8]~34_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(8));
+
+-- Location: LCCOMB_X19_Y27_N0
+\clockConv|ctr[9]~36\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[9]~36_combout\ = (\clockConv|ctr\(9) & (!\clockConv|ctr[8]~35\)) # (!\clockConv|ctr\(9) & ((\clockConv|ctr[8]~35\) # (GND)))
+-- \clockConv|ctr[9]~37\ = CARRY((!\clockConv|ctr[8]~35\) # (!\clockConv|ctr\(9)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(9),
+	datad => VCC,
+	cin => \clockConv|ctr[8]~35\,
+	combout => \clockConv|ctr[9]~36_combout\,
+	cout => \clockConv|ctr[9]~37\);
+
+-- Location: FF_X19_Y27_N1
+\clockConv|ctr[9]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[9]~36_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(9));
+
+-- Location: LCCOMB_X19_Y27_N2
+\clockConv|ctr[10]~38\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[10]~38_combout\ = (\clockConv|ctr\(10) & (\clockConv|ctr[9]~37\ $ (GND))) # (!\clockConv|ctr\(10) & (!\clockConv|ctr[9]~37\ & VCC))
+-- \clockConv|ctr[10]~39\ = CARRY((\clockConv|ctr\(10) & !\clockConv|ctr[9]~37\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(10),
+	datad => VCC,
+	cin => \clockConv|ctr[9]~37\,
+	combout => \clockConv|ctr[10]~38_combout\,
+	cout => \clockConv|ctr[10]~39\);
+
+-- Location: FF_X19_Y27_N3
+\clockConv|ctr[10]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[10]~38_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(10));
+
+-- Location: LCCOMB_X19_Y27_N4
+\clockConv|ctr[11]~40\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[11]~40_combout\ = (\clockConv|ctr\(11) & (!\clockConv|ctr[10]~39\)) # (!\clockConv|ctr\(11) & ((\clockConv|ctr[10]~39\) # (GND)))
+-- \clockConv|ctr[11]~41\ = CARRY((!\clockConv|ctr[10]~39\) # (!\clockConv|ctr\(11)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(11),
+	datad => VCC,
+	cin => \clockConv|ctr[10]~39\,
+	combout => \clockConv|ctr[11]~40_combout\,
+	cout => \clockConv|ctr[11]~41\);
+
+-- Location: FF_X19_Y27_N5
+\clockConv|ctr[11]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[11]~40_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(11));
+
+-- Location: LCCOMB_X19_Y27_N6
+\clockConv|ctr[12]~42\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[12]~42_combout\ = (\clockConv|ctr\(12) & (\clockConv|ctr[11]~41\ $ (GND))) # (!\clockConv|ctr\(12) & (!\clockConv|ctr[11]~41\ & VCC))
+-- \clockConv|ctr[12]~43\ = CARRY((\clockConv|ctr\(12) & !\clockConv|ctr[11]~41\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(12),
+	datad => VCC,
+	cin => \clockConv|ctr[11]~41\,
+	combout => \clockConv|ctr[12]~42_combout\,
+	cout => \clockConv|ctr[12]~43\);
+
+-- Location: FF_X19_Y27_N7
+\clockConv|ctr[12]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[12]~42_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(12));
+
+-- Location: LCCOMB_X19_Y27_N8
+\clockConv|ctr[13]~44\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[13]~44_combout\ = (\clockConv|ctr\(13) & (!\clockConv|ctr[12]~43\)) # (!\clockConv|ctr\(13) & ((\clockConv|ctr[12]~43\) # (GND)))
+-- \clockConv|ctr[13]~45\ = CARRY((!\clockConv|ctr[12]~43\) # (!\clockConv|ctr\(13)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(13),
+	datad => VCC,
+	cin => \clockConv|ctr[12]~43\,
+	combout => \clockConv|ctr[13]~44_combout\,
+	cout => \clockConv|ctr[13]~45\);
+
+-- Location: FF_X19_Y27_N9
+\clockConv|ctr[13]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[13]~44_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(13));
+
+-- Location: LCCOMB_X19_Y27_N10
+\clockConv|ctr[14]~46\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[14]~46_combout\ = (\clockConv|ctr\(14) & (\clockConv|ctr[13]~45\ $ (GND))) # (!\clockConv|ctr\(14) & (!\clockConv|ctr[13]~45\ & VCC))
+-- \clockConv|ctr[14]~47\ = CARRY((\clockConv|ctr\(14) & !\clockConv|ctr[13]~45\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(14),
+	datad => VCC,
+	cin => \clockConv|ctr[13]~45\,
+	combout => \clockConv|ctr[14]~46_combout\,
+	cout => \clockConv|ctr[14]~47\);
+
+-- Location: FF_X19_Y27_N11
+\clockConv|ctr[14]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[14]~46_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(14));
+
+-- Location: LCCOMB_X19_Y27_N12
+\clockConv|ctr[15]~48\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[15]~48_combout\ = (\clockConv|ctr\(15) & (!\clockConv|ctr[14]~47\)) # (!\clockConv|ctr\(15) & ((\clockConv|ctr[14]~47\) # (GND)))
+-- \clockConv|ctr[15]~49\ = CARRY((!\clockConv|ctr[14]~47\) # (!\clockConv|ctr\(15)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(15),
+	datad => VCC,
+	cin => \clockConv|ctr[14]~47\,
+	combout => \clockConv|ctr[15]~48_combout\,
+	cout => \clockConv|ctr[15]~49\);
+
+-- Location: FF_X19_Y27_N13
+\clockConv|ctr[15]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[15]~48_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(15));
+
+-- Location: LCCOMB_X19_Y27_N14
+\clockConv|ctr[16]~50\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[16]~50_combout\ = (\clockConv|ctr\(16) & (\clockConv|ctr[15]~49\ $ (GND))) # (!\clockConv|ctr\(16) & (!\clockConv|ctr[15]~49\ & VCC))
+-- \clockConv|ctr[16]~51\ = CARRY((\clockConv|ctr\(16) & !\clockConv|ctr[15]~49\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(16),
+	datad => VCC,
+	cin => \clockConv|ctr[15]~49\,
+	combout => \clockConv|ctr[16]~50_combout\,
+	cout => \clockConv|ctr[16]~51\);
+
+-- Location: FF_X19_Y27_N15
+\clockConv|ctr[16]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[16]~50_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(16));
+
+-- Location: LCCOMB_X19_Y27_N16
+\clockConv|ctr[17]~52\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[17]~52_combout\ = \clockConv|ctr[16]~51\ $ (\clockConv|ctr\(17))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111111110000",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datad => \clockConv|ctr\(17),
+	cin => \clockConv|ctr[16]~51\,
+	combout => \clockConv|ctr[17]~52_combout\);
+
+-- Location: FF_X19_Y27_N17
+\clockConv|ctr[17]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[17]~52_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(17));
+
+-- Location: LCCOMB_X19_Y27_N18
+\clockConv|LessThan0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~0_combout\ = (\clockConv|ctr\(14) & (\clockConv|ctr\(17) & (\clockConv|ctr\(16) & \clockConv|ctr\(15))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(14),
+	datab => \clockConv|ctr\(17),
+	datac => \clockConv|ctr\(16),
+	datad => \clockConv|ctr\(15),
+	combout => \clockConv|LessThan0~0_combout\);
+
+-- Location: LCCOMB_X19_Y28_N12
+\clockConv|LessThan0~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~3_combout\ = (!\clockConv|ctr\(6) & (!\clockConv|ctr\(4) & !\clockConv|ctr\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(6),
+	datac => \clockConv|ctr\(4),
+	datad => \clockConv|ctr\(5),
+	combout => \clockConv|LessThan0~3_combout\);
+
+-- Location: LCCOMB_X19_Y28_N8
+\clockConv|LessThan0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~1_combout\ = (!\clockConv|ctr\(8) & (!\clockConv|ctr\(9) & (!\clockConv|ctr\(10) & !\clockConv|ctr\(11))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(8),
+	datab => \clockConv|ctr\(9),
+	datac => \clockConv|ctr\(10),
+	datad => \clockConv|ctr\(11),
+	combout => \clockConv|LessThan0~1_combout\);
+
+-- Location: LCCOMB_X19_Y28_N10
+\clockConv|LessThan0~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~2_combout\ = (((!\clockConv|ctr\(1)) # (!\clockConv|ctr\(0))) # (!\clockConv|ctr\(2))) # (!\clockConv|ctr\(3))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111111111111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(3),
+	datab => \clockConv|ctr\(2),
+	datac => \clockConv|ctr\(0),
+	datad => \clockConv|ctr\(1),
+	combout => \clockConv|LessThan0~2_combout\);
+
+-- Location: LCCOMB_X19_Y28_N2
+\clockConv|LessThan0~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~4_combout\ = (\clockConv|LessThan0~1_combout\ & (((\clockConv|LessThan0~3_combout\ & \clockConv|LessThan0~2_combout\)) # (!\clockConv|ctr\(7))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1011000000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|LessThan0~3_combout\,
+	datab => \clockConv|ctr\(7),
+	datac => \clockConv|LessThan0~1_combout\,
+	datad => \clockConv|LessThan0~2_combout\,
+	combout => \clockConv|LessThan0~4_combout\);
+
+-- Location: LCCOMB_X19_Y27_N24
+\clockConv|LessThan0~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~5_combout\ = ((!\clockConv|ctr\(13) & ((\clockConv|LessThan0~4_combout\) # (!\clockConv|ctr\(12))))) # (!\clockConv|LessThan0~0_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011111100011111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(12),
+	datab => \clockConv|ctr\(13),
+	datac => \clockConv|LessThan0~0_combout\,
+	datad => \clockConv|LessThan0~4_combout\,
+	combout => \clockConv|LessThan0~5_combout\);
+
+-- Location: LCCOMB_X19_Y27_N28
+\clockConv|clock_out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|clock_out~0_combout\ = \clockConv|clock_out~q\ $ (((!\clockConv|LessThan0~5_combout\ & ((\clockConv|start~q\) # (!\button1~input_o\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000001001011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|start~q\,
+	datab => \button1~input_o\,
+	datac => \clockConv|clock_out~q\,
+	datad => \clockConv|LessThan0~5_combout\,
+	combout => \clockConv|clock_out~0_combout\);
+
+-- Location: LCCOMB_X19_Y27_N22
+\clockConv|clock_out~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|clock_out~feeder_combout\ = \clockConv|clock_out~0_combout\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \clockConv|clock_out~0_combout\,
+	combout => \clockConv|clock_out~feeder_combout\);
+
+-- Location: FF_X19_Y27_N23
+\clockConv|clock_out\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|clock_out~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|clock_out~q\);
+
+-- Location: CLKCTRL_G14
+\clockConv|clock_out~clkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \clockConv|clock_out~clkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \clockConv|clock_out~clkctrl_outclk\);
+
+-- Location: IOIBUF_X0_Y21_N8
+\button0~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_button0,
+	o => \button0~input_o\);
+
+-- Location: FF_X28_Y27_N27
+\timeCount|en\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	asdata => \timeCount|always0~0_combout\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|en~q\);
+
+-- Location: LCCOMB_X28_Y27_N0
+\timeCount|always0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|always0~0_combout\ = ((\timeCount|en~q\ & \button1~input_o\)) # (!\button0~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001100110011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button0~input_o\,
+	datac => \timeCount|en~q\,
+	datad => \button1~input_o\,
+	combout => \timeCount|always0~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N4
+\timeCount|c0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~0_combout\ = (!\timeCount|c2[0]~0_combout\ & (!\timeCount|c0\(0) & !\timeCount|always0~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|c2[0]~0_combout\,
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c0~0_combout\);
+
+-- Location: FF_X28_Y28_N5
+\timeCount|c0[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(0));
+
+-- Location: LCCOMB_X28_Y28_N6
+\timeCount|c0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~1_combout\ = (!\timeCount|always0~0_combout\ & (!\timeCount|c2[0]~0_combout\ & (\timeCount|c0\(0) $ (\timeCount|c0\(1)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000010010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(0),
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c0\(1),
+	datad => \timeCount|c2[0]~0_combout\,
+	combout => \timeCount|c0~1_combout\);
+
+-- Location: FF_X28_Y28_N7
+\timeCount|c0[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~1_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(1));
+
+-- Location: LCCOMB_X28_Y28_N0
+\timeCount|c2[0]~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~0_combout\ = (!\timeCount|c0\(1) & (\timeCount|c0\(3) & (\timeCount|c0\(0) & !\timeCount|c0\(2))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \timeCount|c2[0]~0_combout\);
+
+-- Location: LCCOMB_X29_Y28_N18
+\timeCount|Add3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add3~0_combout\ = (\timeCount|c0\(0) & \timeCount|c0\(1))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|c0\(0),
+	datac => \timeCount|c0\(1),
+	combout => \timeCount|Add3~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N24
+\timeCount|c0~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~2_combout\ = (!\timeCount|c2[0]~0_combout\ & (!\timeCount|always0~0_combout\ & (\timeCount|c0\(2) $ (\timeCount|Add3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~0_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c0\(2),
+	datad => \timeCount|Add3~0_combout\,
+	combout => \timeCount|c0~2_combout\);
+
+-- Location: FF_X28_Y28_N25
+\timeCount|c0[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(2));
+
+-- Location: LCCOMB_X28_Y27_N22
+\timeCount|c0[3]~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0[3]~3_combout\ = (\button0~input_o\ & (!\timeCount|c2[0]~0_combout\ & ((!\timeCount|en~q\) # (!\button1~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button1~input_o\,
+	datab => \button0~input_o\,
+	datac => \timeCount|en~q\,
+	datad => \timeCount|c2[0]~0_combout\,
+	combout => \timeCount|c0[3]~3_combout\);
+
+-- Location: LCCOMB_X28_Y28_N2
+\timeCount|c0~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~4_combout\ = (\timeCount|c0[3]~3_combout\ & (\timeCount|c0\(3) $ (((\timeCount|c0\(2) & \timeCount|Add3~0_combout\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(2),
+	datab => \timeCount|Add3~0_combout\,
+	datac => \timeCount|c0\(3),
+	datad => \timeCount|c0[3]~3_combout\,
+	combout => \timeCount|c0~4_combout\);
+
+-- Location: FF_X28_Y28_N3
+\timeCount|c0[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(3));
+
+-- Location: LCCOMB_X29_Y28_N12
+\dss0|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out~0_combout\ = (!\timeCount|c0\(3) & (!\timeCount|c0\(1) & (\timeCount|c0\(0) $ (\timeCount|c0\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(3),
+	datab => \timeCount|c0\(1),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|out~0_combout\);
+
+-- Location: LCCOMB_X29_Y28_N8
+\dss0|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(0) = (\button2~input_o\ & ((\dss0|out~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(0),
+	datac => \button2~input_o\,
+	datad => \dss0|out~0_combout\,
+	combout => \dss0|out\(0));
+
+-- Location: LCCOMB_X28_Y28_N20
+\dss0|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out~1_combout\ = (!\timeCount|c0\(3) & (\timeCount|c0\(2) & (\timeCount|c0\(1) $ (\timeCount|c0\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001001000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|out~1_combout\);
+
+-- Location: LCCOMB_X28_Y28_N30
+\dss0|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(1) = (\button2~input_o\ & (\dss0|out~1_combout\)) # (!\button2~input_o\ & ((\dss0|out\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out~1_combout\,
+	datac => \dss0|out\(1),
+	datad => \button2~input_o\,
+	combout => \dss0|out\(1));
+
+-- Location: LCCOMB_X28_Y28_N14
+\dss0|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr4~0_combout\ = (\timeCount|c0\(2) & (((\timeCount|c0\(3))))) # (!\timeCount|c0\(2) & (\timeCount|c0\(1) & ((\timeCount|c0\(3)) # (!\timeCount|c0\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000010100010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(0),
+	datac => \timeCount|c0\(3),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N16
+\dss0|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(2) = (\button2~input_o\ & ((\dss0|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(2),
+	datac => \dss0|WideOr4~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss0|out\(2));
+
+-- Location: LCCOMB_X28_Y28_N8
+\dss0|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr3~0_combout\ = (!\timeCount|c0\(3) & ((\timeCount|c0\(1) & (\timeCount|c0\(0) & \timeCount|c0\(2))) # (!\timeCount|c0\(1) & (\timeCount|c0\(0) $ (\timeCount|c0\(2))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000010010100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(0),
+	datac => \timeCount|c0\(2),
+	datad => \timeCount|c0\(3),
+	combout => \dss0|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N18
+\dss0|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(3) = (\button2~input_o\ & ((\dss0|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(3),
+	datac => \dss0|WideOr3~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss0|out\(3));
+
+-- Location: LCCOMB_X28_Y28_N10
+\dss0|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr2~0_combout\ = (\timeCount|c0\(1) & (!\timeCount|c0\(3) & (\timeCount|c0\(0)))) # (!\timeCount|c0\(1) & ((\timeCount|c0\(2) & (!\timeCount|c0\(3))) # (!\timeCount|c0\(2) & ((\timeCount|c0\(0))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011000101110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N28
+\dss0|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(4) = (\button2~input_o\ & ((\dss0|WideOr2~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(4)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(4),
+	datac => \button2~input_o\,
+	datad => \dss0|WideOr2~0_combout\,
+	combout => \dss0|out\(4));
+
+-- Location: LCCOMB_X28_Y28_N12
+\dss0|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr1~0_combout\ = (!\timeCount|c0\(3) & ((\timeCount|c0\(1) & ((\timeCount|c0\(0)) # (!\timeCount|c0\(2)))) # (!\timeCount|c0\(1) & (!\timeCount|c0\(2) & \timeCount|c0\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000101100000010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(2),
+	datac => \timeCount|c0\(3),
+	datad => \timeCount|c0\(0),
+	combout => \dss0|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X29_Y28_N10
+\dss0|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(5) = (\button2~input_o\ & ((\dss0|WideOr1~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101000001010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss0|out\(5),
+	datac => \button2~input_o\,
+	datad => \dss0|WideOr1~0_combout\,
+	combout => \dss0|out\(5));
+
+-- Location: LCCOMB_X28_Y28_N26
+\dss0|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr0~0_combout\ = (\timeCount|c0\(3)) # ((\timeCount|c0\(1) & ((!\timeCount|c0\(2)) # (!\timeCount|c0\(0)))) # (!\timeCount|c0\(1) & ((\timeCount|c0\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1101111111101110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N22
+\dss0|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(6) = (\button2~input_o\ & ((!\dss0|WideOr0~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(6)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111110101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss0|out\(6),
+	datac => \dss0|WideOr0~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss0|out\(6));
+
+-- Location: LCCOMB_X27_Y27_N22
+\timeCount|c1~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~1_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & (\timeCount|c1\(1) $ (\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \timeCount|c1~1_combout\);
+
+-- Location: FF_X27_Y27_N23
+\timeCount|c1[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~1_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(1));
+
+-- Location: LCCOMB_X26_Y27_N22
+\timeCount|Add2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add2~0_combout\ = \timeCount|c1\(2) $ (((\timeCount|c1\(0) & \timeCount|c1\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110101001101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(2),
+	datab => \timeCount|c1\(0),
+	datac => \timeCount|c1\(1),
+	combout => \timeCount|Add2~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N4
+\timeCount|c1~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~2_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|Add2~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|Add2~0_combout\,
+	combout => \timeCount|c1~2_combout\);
+
+-- Location: FF_X27_Y27_N5
+\timeCount|c1[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~2_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(2));
+
+-- Location: LCCOMB_X26_Y27_N24
+\timeCount|Add2~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add2~1_combout\ = \timeCount|c1\(3) $ (((\timeCount|c1\(0) & (\timeCount|c1\(1) & \timeCount|c1\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110110011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(0),
+	datab => \timeCount|c1\(3),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(2),
+	combout => \timeCount|Add2~1_combout\);
+
+-- Location: LCCOMB_X27_Y27_N26
+\timeCount|c1~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~3_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|Add2~1_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|Add2~1_combout\,
+	combout => \timeCount|c1~3_combout\);
+
+-- Location: FF_X27_Y27_N27
+\timeCount|c1[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~3_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(3));
+
+-- Location: LCCOMB_X27_Y27_N20
+\timeCount|c2[0]~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~1_combout\ = (!\timeCount|c1\(1) & (!\timeCount|c1\(2) & (\timeCount|c1\(3) & \timeCount|c1\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(1),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(3),
+	datad => \timeCount|c1\(0),
+	combout => \timeCount|c2[0]~1_combout\);
+
+-- Location: LCCOMB_X27_Y27_N0
+\timeCount|c1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~0_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & !\timeCount|c1\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c1\(0),
+	combout => \timeCount|c1~0_combout\);
+
+-- Location: FF_X27_Y27_N1
+\timeCount|c1[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~0_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(0));
+
+-- Location: LCCOMB_X27_Y27_N12
+\dss1|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out~0_combout\ = (!\timeCount|c1\(1) & (!\timeCount|c1\(3) & (\timeCount|c1\(0) $ (\timeCount|c1\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(0),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(3),
+	combout => \dss1|out~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N6
+\dss1|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(0) = (\button2~input_o\ & ((\dss1|out~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|out\(0),
+	datad => \dss1|out~0_combout\,
+	combout => \dss1|out\(0));
+
+-- Location: LCCOMB_X27_Y27_N30
+\dss1|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out~1_combout\ = (!\timeCount|c1\(3) & (\timeCount|c1\(2) & (\timeCount|c1\(1) $ (\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010001000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|out~1_combout\);
+
+-- Location: LCCOMB_X27_Y27_N28
+\dss1|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(1) = (\button2~input_o\ & (\dss1|out~1_combout\)) # (!\button2~input_o\ & ((\dss1|out\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111010110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|out~1_combout\,
+	datad => \dss1|out\(1),
+	combout => \dss1|out\(1));
+
+-- Location: LCCOMB_X26_Y27_N28
+\dss1|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr4~0_combout\ = (\timeCount|c1\(2) & (((\timeCount|c1\(3))))) # (!\timeCount|c1\(2) & (\timeCount|c1\(1) & ((\timeCount|c1\(3)) # (!\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110111000000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(2),
+	datab => \timeCount|c1\(1),
+	datac => \timeCount|c1\(0),
+	datad => \timeCount|c1\(3),
+	combout => \dss1|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X26_Y27_N30
+\dss1|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(2) = (\button2~input_o\ & ((\dss1|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss1|out\(2),
+	datad => \dss1|WideOr4~0_combout\,
+	combout => \dss1|out\(2));
+
+-- Location: LCCOMB_X27_Y27_N16
+\dss1|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr3~0_combout\ = (!\timeCount|c1\(3) & ((\timeCount|c1\(2) & (\timeCount|c1\(1) $ (!\timeCount|c1\(0)))) # (!\timeCount|c1\(2) & (!\timeCount|c1\(1) & \timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100000100000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X26_Y27_N8
+\dss1|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(3) = (\button2~input_o\ & ((\dss1|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss1|out\(3),
+	datad => \dss1|WideOr3~0_combout\,
+	combout => \dss1|out\(3));
+
+-- Location: LCCOMB_X27_Y27_N10
+\dss1|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr2~0_combout\ = (\timeCount|c1\(1) & (\timeCount|c1\(0) & ((!\timeCount|c1\(3))))) # (!\timeCount|c1\(1) & ((\timeCount|c1\(2) & ((!\timeCount|c1\(3)))) # (!\timeCount|c1\(2) & (\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000001010101110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(0),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(3),
+	combout => \dss1|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N2
+\dss1|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(4) = (\button2~input_o\ & ((\dss1|WideOr2~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(4)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|out\(4),
+	datad => \dss1|WideOr2~0_combout\,
+	combout => \dss1|out\(4));
+
+-- Location: LCCOMB_X27_Y27_N8
+\dss1|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr1~0_combout\ = (!\timeCount|c1\(3) & ((\timeCount|c1\(2) & (\timeCount|c1\(1) & \timeCount|c1\(0))) # (!\timeCount|c1\(2) & ((\timeCount|c1\(1)) # (\timeCount|c1\(0))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N24
+\dss1|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(5) = (\button2~input_o\ & (\dss1|WideOr1~0_combout\)) # (!\button2~input_o\ & ((\dss1|out\(5))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111010110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|WideOr1~0_combout\,
+	datad => \dss1|out\(5),
+	combout => \dss1|out\(5));
+
+-- Location: LCCOMB_X27_Y27_N14
+\dss1|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr0~0_combout\ = (\timeCount|c1\(3)) # ((\timeCount|c1\(2) & ((!\timeCount|c1\(0)) # (!\timeCount|c1\(1)))) # (!\timeCount|c1\(2) & (\timeCount|c1\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1011111011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N18
+\dss1|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(6) = (\button2~input_o\ & (!\dss1|WideOr0~0_combout\)) # (!\button2~input_o\ & ((\dss1|out\(6))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111100001010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|WideOr0~0_combout\,
+	datad => \dss1|out\(6),
+	combout => \dss1|out\(6));
+
+-- Location: LCCOMB_X28_Y27_N16
+\timeCount|c2~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~3_combout\ = (!\timeCount|c2[0]~2_combout\ & (!\timeCount|c2\(0) & !\timeCount|always0~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c2~3_combout\);
+
+-- Location: LCCOMB_X28_Y27_N18
+\timeCount|c2[0]~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~4_combout\ = (\timeCount|always0~0_combout\) # ((\timeCount|c2[0]~1_combout\ & \timeCount|c2[0]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|c2[0]~0_combout\,
+	combout => \timeCount|c2[0]~4_combout\);
+
+-- Location: FF_X28_Y27_N17
+\timeCount|c2[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~3_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(0));
+
+-- Location: LCCOMB_X28_Y27_N6
+\timeCount|c2~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~5_combout\ = (!\timeCount|c2[0]~2_combout\ & (!\timeCount|always0~0_combout\ & (\timeCount|c2\(0) $ (\timeCount|c2\(1)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000010100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(1),
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c2~5_combout\);
+
+-- Location: FF_X28_Y27_N7
+\timeCount|c2[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~5_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(1));
+
+-- Location: LCCOMB_X28_Y27_N26
+\timeCount|Add1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add1~0_combout\ = \timeCount|c2\(2) $ (((\timeCount|c2\(1) & \timeCount|c2\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111011110001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \timeCount|Add1~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N28
+\timeCount|c2~6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~6_combout\ = (!\timeCount|c2[0]~2_combout\ & (\timeCount|Add1~0_combout\ & !\timeCount|always0~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datac => \timeCount|Add1~0_combout\,
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c2~6_combout\);
+
+-- Location: FF_X28_Y27_N29
+\timeCount|c2[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~6_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(2));
+
+-- Location: LCCOMB_X28_Y27_N12
+\timeCount|c2[0]~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~2_combout\ = (!\timeCount|c2\(1) & (\timeCount|c2\(0) & (\timeCount|c2\(3) & !\timeCount|c2\(2))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \timeCount|c2[0]~2_combout\);
+
+-- Location: LCCOMB_X28_Y27_N20
+\timeCount|Add1~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add1~1_combout\ = \timeCount|c2\(3) $ (((\timeCount|c2\(1) & (\timeCount|c2\(0) & \timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \timeCount|Add1~1_combout\);
+
+-- Location: LCCOMB_X28_Y27_N14
+\timeCount|c2~7\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~7_combout\ = (!\timeCount|c2[0]~2_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|Add1~1_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001000000010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|Add1~1_combout\,
+	combout => \timeCount|c2~7_combout\);
+
+-- Location: FF_X28_Y27_N15
+\timeCount|c2[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~7_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(3));
+
+-- Location: LCCOMB_X29_Y27_N24
+\dss2|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out~0_combout\ = (!\timeCount|c2\(3) & (!\timeCount|c2\(1) & (\timeCount|c2\(0) $ (\timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|out~0_combout\);
+
+-- Location: LCCOMB_X29_Y27_N8
+\dss2|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(0) = (\button2~input_o\ & ((\dss2|out~0_combout\))) # (!\button2~input_o\ & (\dss2|out\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(0),
+	datad => \dss2|out~0_combout\,
+	combout => \dss2|out\(0));
+
+-- Location: LCCOMB_X29_Y27_N18
+\dss2|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out~1_combout\ = (!\timeCount|c2\(3) & (\timeCount|c2\(2) & (\timeCount|c2\(1) $ (\timeCount|c2\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001010000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|out~1_combout\);
+
+-- Location: LCCOMB_X29_Y27_N30
+\dss2|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(1) = (\button2~input_o\ & ((\dss2|out~1_combout\))) # (!\button2~input_o\ & (\dss2|out\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(1),
+	datad => \dss2|out~1_combout\,
+	combout => \dss2|out\(1));
+
+-- Location: LCCOMB_X29_Y27_N28
+\dss2|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr4~0_combout\ = (\timeCount|c2\(2) & (\timeCount|c2\(3))) # (!\timeCount|c2\(2) & (\timeCount|c2\(1) & ((\timeCount|c2\(3)) # (!\timeCount|c2\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101010001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X29_Y27_N4
+\dss2|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(2) = (\button2~input_o\ & ((\dss2|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss2|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(2),
+	datad => \dss2|WideOr4~0_combout\,
+	combout => \dss2|out\(2));
+
+-- Location: LCCOMB_X29_Y27_N6
+\dss2|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr3~0_combout\ = (!\timeCount|c2\(3) & ((\timeCount|c2\(1) & (\timeCount|c2\(0) & \timeCount|c2\(2))) # (!\timeCount|c2\(1) & (\timeCount|c2\(0) $ (\timeCount|c2\(2))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X29_Y27_N26
+\dss2|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(3) = (\button2~input_o\ & ((\dss2|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss2|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(3),
+	datad => \dss2|WideOr3~0_combout\,
+	combout => \dss2|out\(3));
+
+-- Location: LCCOMB_X28_Y27_N4
+\dss2|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr2~0_combout\ = (\timeCount|c2\(1) & (\timeCount|c2\(0) & (!\timeCount|c2\(3)))) # (!\timeCount|c2\(1) & ((\timeCount|c2\(2) & ((!\timeCount|c2\(3)))) # (!\timeCount|c2\(2) & (\timeCount|c2\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110101001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N2
+\dss2|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(4) = (\button2~input_o\ & (\dss2|WideOr2~0_combout\)) # (!\button2~input_o\ & ((\dss2|out\(4))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss2|WideOr2~0_combout\,
+	datad => \dss2|out\(4),
+	combout => \dss2|out\(4));
+
+-- Location: LCCOMB_X28_Y27_N30
+\dss2|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr1~0_combout\ = (!\timeCount|c2\(3) & ((\timeCount|c2\(1) & ((\timeCount|c2\(0)) # (!\timeCount|c2\(2)))) # (!\timeCount|c2\(1) & (\timeCount|c2\(0) & !\timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100000001110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N24
+\dss2|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(5) = (\button2~input_o\ & (\dss2|WideOr1~0_combout\)) # (!\button2~input_o\ & ((\dss2|out\(5))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss2|WideOr1~0_combout\,
+	datad => \dss2|out\(5),
+	combout => \dss2|out\(5));
+
+-- Location: LCCOMB_X28_Y27_N8
+\dss2|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr0~0_combout\ = (\timeCount|c2\(3)) # ((\timeCount|c2\(1) & ((!\timeCount|c2\(2)) # (!\timeCount|c2\(0)))) # (!\timeCount|c2\(1) & ((\timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011111111010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N10
+\dss2|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(6) = (\button2~input_o\ & (!\dss2|WideOr0~0_combout\)) # (!\button2~input_o\ & ((\dss2|out\(6))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011111100001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss2|WideOr0~0_combout\,
+	datad => \dss2|out\(6),
+	combout => \dss2|out\(6));
+
+-- Location: LCCOMB_X26_Y28_N8
+\timeCount|Add0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add0~0_combout\ = \timeCount|c3\(2) $ (((\timeCount|c3\(1) & \timeCount|c3\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(2),
+	combout => \timeCount|Add0~0_combout\);
+
+-- Location: LCCOMB_X26_Y28_N6
+\timeCount|c3~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~4_combout\ = (!\timeCount|always0~0_combout\ & (\timeCount|Add0~0_combout\ & \timeCount|c3[1]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datac => \timeCount|Add0~0_combout\,
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~4_combout\);
+
+-- Location: LCCOMB_X27_Y28_N28
+\timeCount|c3[1]~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3[1]~2_combout\ = (\timeCount|always0~0_combout\) # ((\timeCount|c2[0]~1_combout\ & (\timeCount|c2[0]~0_combout\ & \timeCount|c2[0]~2_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datab => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|c2[0]~0_combout\,
+	datad => \timeCount|c2[0]~2_combout\,
+	combout => \timeCount|c3[1]~2_combout\);
+
+-- Location: FF_X27_Y28_N17
+\timeCount|c3[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	asdata => \timeCount|c3~4_combout\,
+	sload => VCC,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(2));
+
+-- Location: LCCOMB_X26_Y28_N10
+\timeCount|c3[1]~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3[1]~0_combout\ = (\timeCount|c3\(1)) # ((\timeCount|c3\(2)) # ((!\timeCount|c3\(3)) # (!\timeCount|c3\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110111111111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(3),
+	combout => \timeCount|c3[1]~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N0
+\timeCount|c3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~1_combout\ = (!\timeCount|always0~0_combout\ & (!\timeCount|c3\(0) & \timeCount|c3[1]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~1_combout\);
+
+-- Location: FF_X27_Y28_N1
+\timeCount|c3[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c3~1_combout\,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(0));
+
+-- Location: LCCOMB_X27_Y28_N30
+\timeCount|c3~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~3_combout\ = (!\timeCount|always0~0_combout\ & (\timeCount|c3[1]~0_combout\ & (\timeCount|c3\(0) $ (\timeCount|c3\(1)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001010000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(1),
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~3_combout\);
+
+-- Location: FF_X27_Y28_N31
+\timeCount|c3[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c3~3_combout\,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(1));
+
+-- Location: LCCOMB_X26_Y28_N24
+\timeCount|Add0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add0~1_combout\ = \timeCount|c3\(3) $ (((\timeCount|c3\(1) & (\timeCount|c3\(2) & \timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111111110000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(3),
+	combout => \timeCount|Add0~1_combout\);
+
+-- Location: LCCOMB_X27_Y28_N26
+\timeCount|c3~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~5_combout\ = (\timeCount|Add0~1_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|c3[1]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|Add0~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~5_combout\);
+
+-- Location: FF_X27_Y28_N27
+\timeCount|c3[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c3~5_combout\,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(3));
+
+-- Location: LCCOMB_X27_Y28_N24
+\dss3|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out~0_combout\ = (!\timeCount|c3\(3) & (!\timeCount|c3\(1) & (\timeCount|c3\(2) $ (\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(3),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(1),
+	datad => \timeCount|c3\(0),
+	combout => \dss3|out~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N10
+\dss3|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(0) = (\button2~input_o\ & (\dss3|out~0_combout\)) # (!\button2~input_o\ & ((\dss3|out\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100111111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out~0_combout\,
+	datac => \button2~input_o\,
+	datad => \dss3|out\(0),
+	combout => \dss3|out\(0));
+
+-- Location: LCCOMB_X27_Y28_N2
+\dss3|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out~1_combout\ = (\timeCount|c3\(2) & (!\timeCount|c3\(3) & (\timeCount|c3\(1) $ (\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010000001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(0),
+	combout => \dss3|out~1_combout\);
+
+-- Location: LCCOMB_X27_Y28_N16
+\dss3|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(1) = (\button2~input_o\ & ((\dss3|out~1_combout\))) # (!\button2~input_o\ & (\dss3|out\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110010101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss3|out\(1),
+	datab => \dss3|out~1_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(1));
+
+-- Location: LCCOMB_X26_Y28_N12
+\dss3|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr4~0_combout\ = (\timeCount|c3\(2) & (((\timeCount|c3\(3))))) # (!\timeCount|c3\(2) & (\timeCount|c3\(1) & ((\timeCount|c3\(3)) # (!\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110010001010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(3),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X26_Y28_N18
+\dss3|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(2) = (\button2~input_o\ & ((\dss3|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out\(2),
+	datac => \button2~input_o\,
+	datad => \dss3|WideOr4~0_combout\,
+	combout => \dss3|out\(2));
+
+-- Location: LCCOMB_X27_Y28_N8
+\dss3|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr3~0_combout\ = (!\timeCount|c3\(3) & ((\timeCount|c3\(1) & (\timeCount|c3\(0) & \timeCount|c3\(2))) # (!\timeCount|c3\(1) & (\timeCount|c3\(0) $ (\timeCount|c3\(2))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100100000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N20
+\dss3|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(3) = (\button2~input_o\ & ((\dss3|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out\(3),
+	datac => \dss3|WideOr3~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(3));
+
+-- Location: LCCOMB_X27_Y28_N22
+\dss3|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr2~0_combout\ = (\timeCount|c3\(1) & (\timeCount|c3\(0) & (!\timeCount|c3\(3)))) # (!\timeCount|c3\(1) & ((\timeCount|c3\(2) & ((!\timeCount|c3\(3)))) # (!\timeCount|c3\(2) & (\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110101001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N18
+\dss3|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(4) = (\button2~input_o\ & ((\dss3|WideOr2~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(4)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out\(4),
+	datac => \dss3|WideOr2~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(4));
+
+-- Location: LCCOMB_X27_Y28_N4
+\dss3|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr1~0_combout\ = (!\timeCount|c3\(3) & ((\timeCount|c3\(1) & ((\timeCount|c3\(0)) # (!\timeCount|c3\(2)))) # (!\timeCount|c3\(1) & (\timeCount|c3\(0) & !\timeCount|c3\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100000001110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N12
+\dss3|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(5) = (\button2~input_o\ & ((\dss3|WideOr1~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000010101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss3|out\(5),
+	datac => \dss3|WideOr1~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(5));
+
+-- Location: LCCOMB_X27_Y28_N14
+\dss3|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr0~0_combout\ = (\timeCount|c3\(3)) # ((\timeCount|c3\(1) & ((!\timeCount|c3\(0)) # (!\timeCount|c3\(2)))) # (!\timeCount|c3\(1) & (\timeCount|c3\(2))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(0),
+	combout => \dss3|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N6
+\dss3|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(6) = (\button2~input_o\ & ((!\dss3|WideOr0~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(6)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111110101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss3|out\(6),
+	datac => \dss3|WideOr0~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(6));
+
+ww_hex0(0) <= \hex0[0]~output_o\;
+
+ww_hex0(1) <= \hex0[1]~output_o\;
+
+ww_hex0(2) <= \hex0[2]~output_o\;
+
+ww_hex0(3) <= \hex0[3]~output_o\;
+
+ww_hex0(4) <= \hex0[4]~output_o\;
+
+ww_hex0(5) <= \hex0[5]~output_o\;
+
+ww_hex0(6) <= \hex0[6]~output_o\;
+
+ww_hex1(0) <= \hex1[0]~output_o\;
+
+ww_hex1(1) <= \hex1[1]~output_o\;
+
+ww_hex1(2) <= \hex1[2]~output_o\;
+
+ww_hex1(3) <= \hex1[3]~output_o\;
+
+ww_hex1(4) <= \hex1[4]~output_o\;
+
+ww_hex1(5) <= \hex1[5]~output_o\;
+
+ww_hex1(6) <= \hex1[6]~output_o\;
+
+ww_hex2(0) <= \hex2[0]~output_o\;
+
+ww_hex2(1) <= \hex2[1]~output_o\;
+
+ww_hex2(2) <= \hex2[2]~output_o\;
+
+ww_hex2(3) <= \hex2[3]~output_o\;
+
+ww_hex2(4) <= \hex2[4]~output_o\;
+
+ww_hex2(5) <= \hex2[5]~output_o\;
+
+ww_hex2(6) <= \hex2[6]~output_o\;
+
+ww_hex3(0) <= \hex3[0]~output_o\;
+
+ww_hex3(1) <= \hex3[1]~output_o\;
+
+ww_hex3(2) <= \hex3[2]~output_o\;
+
+ww_hex3(3) <= \hex3[3]~output_o\;
+
+ww_hex3(4) <= \hex3[4]~output_o\;
+
+ww_hex3(5) <= \hex3[5]~output_o\;
+
+ww_hex3(6) <= \hex3[6]~output_o\;
+
+ww_decimal_point <= \decimal_point~output_o\;
+END structure;
+
+
diff --git a/stopClockVerilog/simulation/modelsim/stopclock_6_1200mv_0c_slow.vho b/stopClockVerilog/simulation/modelsim/stopclock_6_1200mv_0c_slow.vho
new file mode 100644
index 0000000..766487c
--- /dev/null
+++ b/stopClockVerilog/simulation/modelsim/stopclock_6_1200mv_0c_slow.vho
@@ -0,0 +1,3227 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "03/02/2016 15:24:50"
+
+-- 
+-- Device: Altera EP3C16U484C6 Package UFBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	stopclock IS
+    PORT (
+	clk : IN std_logic;
+	button0 : IN std_logic;
+	button1 : IN std_logic;
+	button2 : IN std_logic;
+	hex0 : BUFFER std_logic_vector(6 DOWNTO 0);
+	hex1 : BUFFER std_logic_vector(6 DOWNTO 0);
+	hex2 : BUFFER std_logic_vector(6 DOWNTO 0);
+	hex3 : BUFFER std_logic_vector(6 DOWNTO 0);
+	decimal_point : BUFFER std_logic
+	);
+END stopclock;
+
+-- Design Ports Information
+-- hex0[0]	=>  Location: PIN_E11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[1]	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[2]	=>  Location: PIN_H12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[3]	=>  Location: PIN_H13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[4]	=>  Location: PIN_G12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[5]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[6]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[0]	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[1]	=>  Location: PIN_B13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[2]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[3]	=>  Location: PIN_A14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[4]	=>  Location: PIN_B14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[5]	=>  Location: PIN_E14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[6]	=>  Location: PIN_A15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[0]	=>  Location: PIN_D15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[1]	=>  Location: PIN_A16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[2]	=>  Location: PIN_B16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[3]	=>  Location: PIN_E15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[4]	=>  Location: PIN_A17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[5]	=>  Location: PIN_B17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[6]	=>  Location: PIN_F14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[0]	=>  Location: PIN_B18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[1]	=>  Location: PIN_F15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[2]	=>  Location: PIN_A19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[3]	=>  Location: PIN_B19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[4]	=>  Location: PIN_C19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[5]	=>  Location: PIN_D19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[6]	=>  Location: PIN_G15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- decimal_point	=>  Location: PIN_A18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- button2	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- button0	=>  Location: PIN_H2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- button1	=>  Location: PIN_G3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- clk	=>  Location: PIN_G21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF stopclock IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_clk : std_logic;
+SIGNAL ww_button0 : std_logic;
+SIGNAL ww_button1 : std_logic;
+SIGNAL ww_button2 : std_logic;
+SIGNAL ww_hex0 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_hex1 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_hex2 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_hex3 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_decimal_point : std_logic;
+SIGNAL \clockConv|clock_out~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \hex0[0]~output_o\ : std_logic;
+SIGNAL \hex0[1]~output_o\ : std_logic;
+SIGNAL \hex0[2]~output_o\ : std_logic;
+SIGNAL \hex0[3]~output_o\ : std_logic;
+SIGNAL \hex0[4]~output_o\ : std_logic;
+SIGNAL \hex0[5]~output_o\ : std_logic;
+SIGNAL \hex0[6]~output_o\ : std_logic;
+SIGNAL \hex1[0]~output_o\ : std_logic;
+SIGNAL \hex1[1]~output_o\ : std_logic;
+SIGNAL \hex1[2]~output_o\ : std_logic;
+SIGNAL \hex1[3]~output_o\ : std_logic;
+SIGNAL \hex1[4]~output_o\ : std_logic;
+SIGNAL \hex1[5]~output_o\ : std_logic;
+SIGNAL \hex1[6]~output_o\ : std_logic;
+SIGNAL \hex2[0]~output_o\ : std_logic;
+SIGNAL \hex2[1]~output_o\ : std_logic;
+SIGNAL \hex2[2]~output_o\ : std_logic;
+SIGNAL \hex2[3]~output_o\ : std_logic;
+SIGNAL \hex2[4]~output_o\ : std_logic;
+SIGNAL \hex2[5]~output_o\ : std_logic;
+SIGNAL \hex2[6]~output_o\ : std_logic;
+SIGNAL \hex3[0]~output_o\ : std_logic;
+SIGNAL \hex3[1]~output_o\ : std_logic;
+SIGNAL \hex3[2]~output_o\ : std_logic;
+SIGNAL \hex3[3]~output_o\ : std_logic;
+SIGNAL \hex3[4]~output_o\ : std_logic;
+SIGNAL \hex3[5]~output_o\ : std_logic;
+SIGNAL \hex3[6]~output_o\ : std_logic;
+SIGNAL \decimal_point~output_o\ : std_logic;
+SIGNAL \button2~input_o\ : std_logic;
+SIGNAL \clk~input_o\ : std_logic;
+SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
+SIGNAL \button1~input_o\ : std_logic;
+SIGNAL \clockConv|start~0_combout\ : std_logic;
+SIGNAL \clockConv|start~q\ : std_logic;
+SIGNAL \clockConv|ctr[0]~18_combout\ : std_logic;
+SIGNAL \clockConv|ctr[0]~19\ : std_logic;
+SIGNAL \clockConv|ctr[1]~20_combout\ : std_logic;
+SIGNAL \clockConv|ctr[1]~21\ : std_logic;
+SIGNAL \clockConv|ctr[2]~22_combout\ : std_logic;
+SIGNAL \clockConv|ctr[2]~23\ : std_logic;
+SIGNAL \clockConv|ctr[3]~24_combout\ : std_logic;
+SIGNAL \clockConv|ctr[3]~25\ : std_logic;
+SIGNAL \clockConv|ctr[4]~26_combout\ : std_logic;
+SIGNAL \clockConv|ctr[4]~27\ : std_logic;
+SIGNAL \clockConv|ctr[5]~28_combout\ : std_logic;
+SIGNAL \clockConv|ctr[5]~29\ : std_logic;
+SIGNAL \clockConv|ctr[6]~30_combout\ : std_logic;
+SIGNAL \clockConv|ctr[6]~31\ : std_logic;
+SIGNAL \clockConv|ctr[7]~32_combout\ : std_logic;
+SIGNAL \clockConv|ctr[7]~33\ : std_logic;
+SIGNAL \clockConv|ctr[8]~34_combout\ : std_logic;
+SIGNAL \clockConv|ctr[8]~35\ : std_logic;
+SIGNAL \clockConv|ctr[9]~36_combout\ : std_logic;
+SIGNAL \clockConv|ctr[9]~37\ : std_logic;
+SIGNAL \clockConv|ctr[10]~38_combout\ : std_logic;
+SIGNAL \clockConv|ctr[10]~39\ : std_logic;
+SIGNAL \clockConv|ctr[11]~40_combout\ : std_logic;
+SIGNAL \clockConv|ctr[11]~41\ : std_logic;
+SIGNAL \clockConv|ctr[12]~42_combout\ : std_logic;
+SIGNAL \clockConv|ctr[12]~43\ : std_logic;
+SIGNAL \clockConv|ctr[13]~44_combout\ : std_logic;
+SIGNAL \clockConv|ctr[13]~45\ : std_logic;
+SIGNAL \clockConv|ctr[14]~46_combout\ : std_logic;
+SIGNAL \clockConv|ctr[14]~47\ : std_logic;
+SIGNAL \clockConv|ctr[15]~48_combout\ : std_logic;
+SIGNAL \clockConv|ctr[15]~49\ : std_logic;
+SIGNAL \clockConv|ctr[16]~50_combout\ : std_logic;
+SIGNAL \clockConv|ctr[16]~51\ : std_logic;
+SIGNAL \clockConv|ctr[17]~52_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~0_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~3_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~1_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~2_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~4_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~5_combout\ : std_logic;
+SIGNAL \clockConv|clock_out~0_combout\ : std_logic;
+SIGNAL \clockConv|clock_out~feeder_combout\ : std_logic;
+SIGNAL \clockConv|clock_out~q\ : std_logic;
+SIGNAL \clockConv|clock_out~clkctrl_outclk\ : std_logic;
+SIGNAL \button0~input_o\ : std_logic;
+SIGNAL \timeCount|en~q\ : std_logic;
+SIGNAL \timeCount|always0~0_combout\ : std_logic;
+SIGNAL \timeCount|c0~0_combout\ : std_logic;
+SIGNAL \timeCount|c0~1_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~0_combout\ : std_logic;
+SIGNAL \timeCount|Add3~0_combout\ : std_logic;
+SIGNAL \timeCount|c0~2_combout\ : std_logic;
+SIGNAL \timeCount|c0[3]~3_combout\ : std_logic;
+SIGNAL \timeCount|c0~4_combout\ : std_logic;
+SIGNAL \dss0|out~0_combout\ : std_logic;
+SIGNAL \dss0|out~1_combout\ : std_logic;
+SIGNAL \dss0|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr0~0_combout\ : std_logic;
+SIGNAL \timeCount|c1~1_combout\ : std_logic;
+SIGNAL \timeCount|Add2~0_combout\ : std_logic;
+SIGNAL \timeCount|c1~2_combout\ : std_logic;
+SIGNAL \timeCount|Add2~1_combout\ : std_logic;
+SIGNAL \timeCount|c1~3_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~1_combout\ : std_logic;
+SIGNAL \timeCount|c1~0_combout\ : std_logic;
+SIGNAL \dss1|out~0_combout\ : std_logic;
+SIGNAL \dss1|out~1_combout\ : std_logic;
+SIGNAL \dss1|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr0~0_combout\ : std_logic;
+SIGNAL \timeCount|c2~3_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~4_combout\ : std_logic;
+SIGNAL \timeCount|c2~5_combout\ : std_logic;
+SIGNAL \timeCount|Add1~0_combout\ : std_logic;
+SIGNAL \timeCount|c2~6_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~2_combout\ : std_logic;
+SIGNAL \timeCount|Add1~1_combout\ : std_logic;
+SIGNAL \timeCount|c2~7_combout\ : std_logic;
+SIGNAL \dss2|out~0_combout\ : std_logic;
+SIGNAL \dss2|out~1_combout\ : std_logic;
+SIGNAL \dss2|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr0~0_combout\ : std_logic;
+SIGNAL \timeCount|Add0~0_combout\ : std_logic;
+SIGNAL \timeCount|c3~4_combout\ : std_logic;
+SIGNAL \timeCount|c3[1]~2_combout\ : std_logic;
+SIGNAL \timeCount|c3[1]~0_combout\ : std_logic;
+SIGNAL \timeCount|c3~1_combout\ : std_logic;
+SIGNAL \timeCount|c3~3_combout\ : std_logic;
+SIGNAL \timeCount|Add0~1_combout\ : std_logic;
+SIGNAL \timeCount|c3~5_combout\ : std_logic;
+SIGNAL \dss3|out~0_combout\ : std_logic;
+SIGNAL \dss3|out~1_combout\ : std_logic;
+SIGNAL \dss3|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr0~0_combout\ : std_logic;
+SIGNAL \dss1|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \dss2|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \dss3|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \clockConv|ctr\ : std_logic_vector(17 DOWNTO 0);
+SIGNAL \timeCount|c3\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \timeCount|c2\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \timeCount|c1\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \timeCount|c0\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \dss0|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \timeCount|ALT_INV_c0[3]~3_combout\ : std_logic;
+SIGNAL \clockConv|ALT_INV_LessThan0~5_combout\ : std_logic;
+
+BEGIN
+
+ww_clk <= clk;
+ww_button0 <= button0;
+ww_button1 <= button1;
+ww_button2 <= button2;
+hex0 <= ww_hex0;
+hex1 <= ww_hex1;
+hex2 <= ww_hex2;
+hex3 <= ww_hex3;
+decimal_point <= ww_decimal_point;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\clockConv|clock_out~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clockConv|clock_out~q\);
+
+\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);
+\timeCount|ALT_INV_c0[3]~3_combout\ <= NOT \timeCount|c0[3]~3_combout\;
+\clockConv|ALT_INV_LessThan0~5_combout\ <= NOT \clockConv|LessThan0~5_combout\;
+
+-- Location: IOOBUF_X21_Y29_N23
+\hex0[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(0),
+	devoe => ww_devoe,
+	o => \hex0[0]~output_o\);
+
+-- Location: IOOBUF_X21_Y29_N30
+\hex0[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(1),
+	devoe => ww_devoe,
+	o => \hex0[1]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N2
+\hex0[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(2),
+	devoe => ww_devoe,
+	o => \hex0[2]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N30
+\hex0[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(3),
+	devoe => ww_devoe,
+	o => \hex0[3]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N9
+\hex0[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(4),
+	devoe => ww_devoe,
+	o => \hex0[4]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N23
+\hex0[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(5),
+	devoe => ww_devoe,
+	o => \hex0[5]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N16
+\hex0[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(6),
+	devoe => ww_devoe,
+	o => \hex0[6]~output_o\);
+
+-- Location: IOOBUF_X21_Y29_N2
+\hex1[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(0),
+	devoe => ww_devoe,
+	o => \hex1[0]~output_o\);
+
+-- Location: IOOBUF_X21_Y29_N9
+\hex1[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(1),
+	devoe => ww_devoe,
+	o => \hex1[1]~output_o\);
+
+-- Location: IOOBUF_X23_Y29_N2
+\hex1[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(2),
+	devoe => ww_devoe,
+	o => \hex1[2]~output_o\);
+
+-- Location: IOOBUF_X23_Y29_N23
+\hex1[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(3),
+	devoe => ww_devoe,
+	o => \hex1[3]~output_o\);
+
+-- Location: IOOBUF_X23_Y29_N30
+\hex1[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(4),
+	devoe => ww_devoe,
+	o => \hex1[4]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N16
+\hex1[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(5),
+	devoe => ww_devoe,
+	o => \hex1[5]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N23
+\hex1[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(6),
+	devoe => ww_devoe,
+	o => \hex1[6]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N30
+\hex2[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(0),
+	devoe => ww_devoe,
+	o => \hex2[0]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N30
+\hex2[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(1),
+	devoe => ww_devoe,
+	o => \hex2[1]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N2
+\hex2[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(2),
+	devoe => ww_devoe,
+	o => \hex2[2]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N2
+\hex2[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(3),
+	devoe => ww_devoe,
+	o => \hex2[3]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N16
+\hex2[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(4),
+	devoe => ww_devoe,
+	o => \hex2[4]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N23
+\hex2[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(5),
+	devoe => ww_devoe,
+	o => \hex2[5]~output_o\);
+
+-- Location: IOOBUF_X37_Y29_N2
+\hex2[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(6),
+	devoe => ww_devoe,
+	o => \hex2[6]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N23
+\hex3[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(0),
+	devoe => ww_devoe,
+	o => \hex3[0]~output_o\);
+
+-- Location: IOOBUF_X39_Y29_N16
+\hex3[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(1),
+	devoe => ww_devoe,
+	o => \hex3[1]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N9
+\hex3[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(2),
+	devoe => ww_devoe,
+	o => \hex3[2]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N2
+\hex3[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(3),
+	devoe => ww_devoe,
+	o => \hex3[3]~output_o\);
+
+-- Location: IOOBUF_X37_Y29_N23
+\hex3[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(4),
+	devoe => ww_devoe,
+	o => \hex3[4]~output_o\);
+
+-- Location: IOOBUF_X37_Y29_N30
+\hex3[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(5),
+	devoe => ww_devoe,
+	o => \hex3[5]~output_o\);
+
+-- Location: IOOBUF_X39_Y29_N30
+\hex3[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(6),
+	devoe => ww_devoe,
+	o => \hex3[6]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N16
+\decimal_point~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => GND,
+	devoe => ww_devoe,
+	o => \decimal_point~output_o\);
+
+-- Location: IOIBUF_X0_Y23_N1
+\button2~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_button2,
+	o => \button2~input_o\);
+
+-- Location: IOIBUF_X41_Y15_N1
+\clk~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_clk,
+	o => \clk~input_o\);
+
+-- Location: CLKCTRL_G9
+\clk~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \clk~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \clk~inputclkctrl_outclk\);
+
+-- Location: IOIBUF_X0_Y23_N15
+\button1~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_button1,
+	o => \button1~input_o\);
+
+-- Location: LCCOMB_X19_Y27_N26
+\clockConv|start~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|start~0_combout\ = (\clockConv|start~q\) # (!\button1~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001111110011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button1~input_o\,
+	datac => \clockConv|start~q\,
+	combout => \clockConv|start~0_combout\);
+
+-- Location: FF_X19_Y27_N27
+\clockConv|start\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|start~q\);
+
+-- Location: LCCOMB_X19_Y28_N14
+\clockConv|ctr[0]~18\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[0]~18_combout\ = \clockConv|ctr\(0) $ (VCC)
+-- \clockConv|ctr[0]~19\ = CARRY(\clockConv|ctr\(0))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011001111001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(0),
+	datad => VCC,
+	combout => \clockConv|ctr[0]~18_combout\,
+	cout => \clockConv|ctr[0]~19\);
+
+-- Location: FF_X19_Y28_N15
+\clockConv|ctr[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[0]~18_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(0));
+
+-- Location: LCCOMB_X19_Y28_N16
+\clockConv|ctr[1]~20\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[1]~20_combout\ = (\clockConv|ctr\(1) & (!\clockConv|ctr[0]~19\)) # (!\clockConv|ctr\(1) & ((\clockConv|ctr[0]~19\) # (GND)))
+-- \clockConv|ctr[1]~21\ = CARRY((!\clockConv|ctr[0]~19\) # (!\clockConv|ctr\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(1),
+	datad => VCC,
+	cin => \clockConv|ctr[0]~19\,
+	combout => \clockConv|ctr[1]~20_combout\,
+	cout => \clockConv|ctr[1]~21\);
+
+-- Location: FF_X19_Y28_N17
+\clockConv|ctr[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[1]~20_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(1));
+
+-- Location: LCCOMB_X19_Y28_N18
+\clockConv|ctr[2]~22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[2]~22_combout\ = (\clockConv|ctr\(2) & (\clockConv|ctr[1]~21\ $ (GND))) # (!\clockConv|ctr\(2) & (!\clockConv|ctr[1]~21\ & VCC))
+-- \clockConv|ctr[2]~23\ = CARRY((\clockConv|ctr\(2) & !\clockConv|ctr[1]~21\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(2),
+	datad => VCC,
+	cin => \clockConv|ctr[1]~21\,
+	combout => \clockConv|ctr[2]~22_combout\,
+	cout => \clockConv|ctr[2]~23\);
+
+-- Location: FF_X19_Y28_N19
+\clockConv|ctr[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[2]~22_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(2));
+
+-- Location: LCCOMB_X19_Y28_N20
+\clockConv|ctr[3]~24\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[3]~24_combout\ = (\clockConv|ctr\(3) & (!\clockConv|ctr[2]~23\)) # (!\clockConv|ctr\(3) & ((\clockConv|ctr[2]~23\) # (GND)))
+-- \clockConv|ctr[3]~25\ = CARRY((!\clockConv|ctr[2]~23\) # (!\clockConv|ctr\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(3),
+	datad => VCC,
+	cin => \clockConv|ctr[2]~23\,
+	combout => \clockConv|ctr[3]~24_combout\,
+	cout => \clockConv|ctr[3]~25\);
+
+-- Location: FF_X19_Y28_N21
+\clockConv|ctr[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[3]~24_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(3));
+
+-- Location: LCCOMB_X19_Y28_N22
+\clockConv|ctr[4]~26\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[4]~26_combout\ = (\clockConv|ctr\(4) & (\clockConv|ctr[3]~25\ $ (GND))) # (!\clockConv|ctr\(4) & (!\clockConv|ctr[3]~25\ & VCC))
+-- \clockConv|ctr[4]~27\ = CARRY((\clockConv|ctr\(4) & !\clockConv|ctr[3]~25\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(4),
+	datad => VCC,
+	cin => \clockConv|ctr[3]~25\,
+	combout => \clockConv|ctr[4]~26_combout\,
+	cout => \clockConv|ctr[4]~27\);
+
+-- Location: FF_X19_Y28_N23
+\clockConv|ctr[4]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[4]~26_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(4));
+
+-- Location: LCCOMB_X19_Y28_N24
+\clockConv|ctr[5]~28\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[5]~28_combout\ = (\clockConv|ctr\(5) & (!\clockConv|ctr[4]~27\)) # (!\clockConv|ctr\(5) & ((\clockConv|ctr[4]~27\) # (GND)))
+-- \clockConv|ctr[5]~29\ = CARRY((!\clockConv|ctr[4]~27\) # (!\clockConv|ctr\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(5),
+	datad => VCC,
+	cin => \clockConv|ctr[4]~27\,
+	combout => \clockConv|ctr[5]~28_combout\,
+	cout => \clockConv|ctr[5]~29\);
+
+-- Location: FF_X19_Y28_N25
+\clockConv|ctr[5]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[5]~28_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(5));
+
+-- Location: LCCOMB_X19_Y28_N26
+\clockConv|ctr[6]~30\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[6]~30_combout\ = (\clockConv|ctr\(6) & (\clockConv|ctr[5]~29\ $ (GND))) # (!\clockConv|ctr\(6) & (!\clockConv|ctr[5]~29\ & VCC))
+-- \clockConv|ctr[6]~31\ = CARRY((\clockConv|ctr\(6) & !\clockConv|ctr[5]~29\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(6),
+	datad => VCC,
+	cin => \clockConv|ctr[5]~29\,
+	combout => \clockConv|ctr[6]~30_combout\,
+	cout => \clockConv|ctr[6]~31\);
+
+-- Location: FF_X19_Y28_N27
+\clockConv|ctr[6]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[6]~30_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(6));
+
+-- Location: LCCOMB_X19_Y28_N28
+\clockConv|ctr[7]~32\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[7]~32_combout\ = (\clockConv|ctr\(7) & (!\clockConv|ctr[6]~31\)) # (!\clockConv|ctr\(7) & ((\clockConv|ctr[6]~31\) # (GND)))
+-- \clockConv|ctr[7]~33\ = CARRY((!\clockConv|ctr[6]~31\) # (!\clockConv|ctr\(7)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(7),
+	datad => VCC,
+	cin => \clockConv|ctr[6]~31\,
+	combout => \clockConv|ctr[7]~32_combout\,
+	cout => \clockConv|ctr[7]~33\);
+
+-- Location: FF_X19_Y28_N29
+\clockConv|ctr[7]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[7]~32_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(7));
+
+-- Location: LCCOMB_X19_Y28_N30
+\clockConv|ctr[8]~34\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[8]~34_combout\ = (\clockConv|ctr\(8) & (\clockConv|ctr[7]~33\ $ (GND))) # (!\clockConv|ctr\(8) & (!\clockConv|ctr[7]~33\ & VCC))
+-- \clockConv|ctr[8]~35\ = CARRY((\clockConv|ctr\(8) & !\clockConv|ctr[7]~33\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(8),
+	datad => VCC,
+	cin => \clockConv|ctr[7]~33\,
+	combout => \clockConv|ctr[8]~34_combout\,
+	cout => \clockConv|ctr[8]~35\);
+
+-- Location: FF_X19_Y28_N31
+\clockConv|ctr[8]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[8]~34_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(8));
+
+-- Location: LCCOMB_X19_Y27_N0
+\clockConv|ctr[9]~36\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[9]~36_combout\ = (\clockConv|ctr\(9) & (!\clockConv|ctr[8]~35\)) # (!\clockConv|ctr\(9) & ((\clockConv|ctr[8]~35\) # (GND)))
+-- \clockConv|ctr[9]~37\ = CARRY((!\clockConv|ctr[8]~35\) # (!\clockConv|ctr\(9)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(9),
+	datad => VCC,
+	cin => \clockConv|ctr[8]~35\,
+	combout => \clockConv|ctr[9]~36_combout\,
+	cout => \clockConv|ctr[9]~37\);
+
+-- Location: FF_X19_Y27_N1
+\clockConv|ctr[9]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[9]~36_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(9));
+
+-- Location: LCCOMB_X19_Y27_N2
+\clockConv|ctr[10]~38\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[10]~38_combout\ = (\clockConv|ctr\(10) & (\clockConv|ctr[9]~37\ $ (GND))) # (!\clockConv|ctr\(10) & (!\clockConv|ctr[9]~37\ & VCC))
+-- \clockConv|ctr[10]~39\ = CARRY((\clockConv|ctr\(10) & !\clockConv|ctr[9]~37\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(10),
+	datad => VCC,
+	cin => \clockConv|ctr[9]~37\,
+	combout => \clockConv|ctr[10]~38_combout\,
+	cout => \clockConv|ctr[10]~39\);
+
+-- Location: FF_X19_Y27_N3
+\clockConv|ctr[10]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[10]~38_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(10));
+
+-- Location: LCCOMB_X19_Y27_N4
+\clockConv|ctr[11]~40\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[11]~40_combout\ = (\clockConv|ctr\(11) & (!\clockConv|ctr[10]~39\)) # (!\clockConv|ctr\(11) & ((\clockConv|ctr[10]~39\) # (GND)))
+-- \clockConv|ctr[11]~41\ = CARRY((!\clockConv|ctr[10]~39\) # (!\clockConv|ctr\(11)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(11),
+	datad => VCC,
+	cin => \clockConv|ctr[10]~39\,
+	combout => \clockConv|ctr[11]~40_combout\,
+	cout => \clockConv|ctr[11]~41\);
+
+-- Location: FF_X19_Y27_N5
+\clockConv|ctr[11]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[11]~40_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(11));
+
+-- Location: LCCOMB_X19_Y27_N6
+\clockConv|ctr[12]~42\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[12]~42_combout\ = (\clockConv|ctr\(12) & (\clockConv|ctr[11]~41\ $ (GND))) # (!\clockConv|ctr\(12) & (!\clockConv|ctr[11]~41\ & VCC))
+-- \clockConv|ctr[12]~43\ = CARRY((\clockConv|ctr\(12) & !\clockConv|ctr[11]~41\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(12),
+	datad => VCC,
+	cin => \clockConv|ctr[11]~41\,
+	combout => \clockConv|ctr[12]~42_combout\,
+	cout => \clockConv|ctr[12]~43\);
+
+-- Location: FF_X19_Y27_N7
+\clockConv|ctr[12]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[12]~42_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(12));
+
+-- Location: LCCOMB_X19_Y27_N8
+\clockConv|ctr[13]~44\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[13]~44_combout\ = (\clockConv|ctr\(13) & (!\clockConv|ctr[12]~43\)) # (!\clockConv|ctr\(13) & ((\clockConv|ctr[12]~43\) # (GND)))
+-- \clockConv|ctr[13]~45\ = CARRY((!\clockConv|ctr[12]~43\) # (!\clockConv|ctr\(13)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(13),
+	datad => VCC,
+	cin => \clockConv|ctr[12]~43\,
+	combout => \clockConv|ctr[13]~44_combout\,
+	cout => \clockConv|ctr[13]~45\);
+
+-- Location: FF_X19_Y27_N9
+\clockConv|ctr[13]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[13]~44_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(13));
+
+-- Location: LCCOMB_X19_Y27_N10
+\clockConv|ctr[14]~46\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[14]~46_combout\ = (\clockConv|ctr\(14) & (\clockConv|ctr[13]~45\ $ (GND))) # (!\clockConv|ctr\(14) & (!\clockConv|ctr[13]~45\ & VCC))
+-- \clockConv|ctr[14]~47\ = CARRY((\clockConv|ctr\(14) & !\clockConv|ctr[13]~45\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(14),
+	datad => VCC,
+	cin => \clockConv|ctr[13]~45\,
+	combout => \clockConv|ctr[14]~46_combout\,
+	cout => \clockConv|ctr[14]~47\);
+
+-- Location: FF_X19_Y27_N11
+\clockConv|ctr[14]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[14]~46_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(14));
+
+-- Location: LCCOMB_X19_Y27_N12
+\clockConv|ctr[15]~48\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[15]~48_combout\ = (\clockConv|ctr\(15) & (!\clockConv|ctr[14]~47\)) # (!\clockConv|ctr\(15) & ((\clockConv|ctr[14]~47\) # (GND)))
+-- \clockConv|ctr[15]~49\ = CARRY((!\clockConv|ctr[14]~47\) # (!\clockConv|ctr\(15)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(15),
+	datad => VCC,
+	cin => \clockConv|ctr[14]~47\,
+	combout => \clockConv|ctr[15]~48_combout\,
+	cout => \clockConv|ctr[15]~49\);
+
+-- Location: FF_X19_Y27_N13
+\clockConv|ctr[15]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[15]~48_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(15));
+
+-- Location: LCCOMB_X19_Y27_N14
+\clockConv|ctr[16]~50\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[16]~50_combout\ = (\clockConv|ctr\(16) & (\clockConv|ctr[15]~49\ $ (GND))) # (!\clockConv|ctr\(16) & (!\clockConv|ctr[15]~49\ & VCC))
+-- \clockConv|ctr[16]~51\ = CARRY((\clockConv|ctr\(16) & !\clockConv|ctr[15]~49\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(16),
+	datad => VCC,
+	cin => \clockConv|ctr[15]~49\,
+	combout => \clockConv|ctr[16]~50_combout\,
+	cout => \clockConv|ctr[16]~51\);
+
+-- Location: FF_X19_Y27_N15
+\clockConv|ctr[16]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[16]~50_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(16));
+
+-- Location: LCCOMB_X19_Y27_N16
+\clockConv|ctr[17]~52\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[17]~52_combout\ = \clockConv|ctr[16]~51\ $ (\clockConv|ctr\(17))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111111110000",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datad => \clockConv|ctr\(17),
+	cin => \clockConv|ctr[16]~51\,
+	combout => \clockConv|ctr[17]~52_combout\);
+
+-- Location: FF_X19_Y27_N17
+\clockConv|ctr[17]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[17]~52_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(17));
+
+-- Location: LCCOMB_X19_Y27_N18
+\clockConv|LessThan0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~0_combout\ = (\clockConv|ctr\(14) & (\clockConv|ctr\(17) & (\clockConv|ctr\(16) & \clockConv|ctr\(15))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(14),
+	datab => \clockConv|ctr\(17),
+	datac => \clockConv|ctr\(16),
+	datad => \clockConv|ctr\(15),
+	combout => \clockConv|LessThan0~0_combout\);
+
+-- Location: LCCOMB_X19_Y28_N12
+\clockConv|LessThan0~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~3_combout\ = (!\clockConv|ctr\(6) & (!\clockConv|ctr\(4) & !\clockConv|ctr\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(6),
+	datac => \clockConv|ctr\(4),
+	datad => \clockConv|ctr\(5),
+	combout => \clockConv|LessThan0~3_combout\);
+
+-- Location: LCCOMB_X19_Y28_N8
+\clockConv|LessThan0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~1_combout\ = (!\clockConv|ctr\(8) & (!\clockConv|ctr\(9) & (!\clockConv|ctr\(10) & !\clockConv|ctr\(11))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(8),
+	datab => \clockConv|ctr\(9),
+	datac => \clockConv|ctr\(10),
+	datad => \clockConv|ctr\(11),
+	combout => \clockConv|LessThan0~1_combout\);
+
+-- Location: LCCOMB_X19_Y28_N10
+\clockConv|LessThan0~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~2_combout\ = (((!\clockConv|ctr\(1)) # (!\clockConv|ctr\(0))) # (!\clockConv|ctr\(2))) # (!\clockConv|ctr\(3))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111111111111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(3),
+	datab => \clockConv|ctr\(2),
+	datac => \clockConv|ctr\(0),
+	datad => \clockConv|ctr\(1),
+	combout => \clockConv|LessThan0~2_combout\);
+
+-- Location: LCCOMB_X19_Y28_N2
+\clockConv|LessThan0~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~4_combout\ = (\clockConv|LessThan0~1_combout\ & (((\clockConv|LessThan0~3_combout\ & \clockConv|LessThan0~2_combout\)) # (!\clockConv|ctr\(7))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1011000000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|LessThan0~3_combout\,
+	datab => \clockConv|ctr\(7),
+	datac => \clockConv|LessThan0~1_combout\,
+	datad => \clockConv|LessThan0~2_combout\,
+	combout => \clockConv|LessThan0~4_combout\);
+
+-- Location: LCCOMB_X19_Y27_N24
+\clockConv|LessThan0~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~5_combout\ = ((!\clockConv|ctr\(13) & ((\clockConv|LessThan0~4_combout\) # (!\clockConv|ctr\(12))))) # (!\clockConv|LessThan0~0_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011111100011111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(12),
+	datab => \clockConv|ctr\(13),
+	datac => \clockConv|LessThan0~0_combout\,
+	datad => \clockConv|LessThan0~4_combout\,
+	combout => \clockConv|LessThan0~5_combout\);
+
+-- Location: LCCOMB_X19_Y27_N28
+\clockConv|clock_out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|clock_out~0_combout\ = \clockConv|clock_out~q\ $ (((!\clockConv|LessThan0~5_combout\ & ((\clockConv|start~q\) # (!\button1~input_o\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000001001011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|start~q\,
+	datab => \button1~input_o\,
+	datac => \clockConv|clock_out~q\,
+	datad => \clockConv|LessThan0~5_combout\,
+	combout => \clockConv|clock_out~0_combout\);
+
+-- Location: LCCOMB_X19_Y27_N22
+\clockConv|clock_out~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|clock_out~feeder_combout\ = \clockConv|clock_out~0_combout\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \clockConv|clock_out~0_combout\,
+	combout => \clockConv|clock_out~feeder_combout\);
+
+-- Location: FF_X19_Y27_N23
+\clockConv|clock_out\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|clock_out~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|clock_out~q\);
+
+-- Location: CLKCTRL_G14
+\clockConv|clock_out~clkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \clockConv|clock_out~clkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \clockConv|clock_out~clkctrl_outclk\);
+
+-- Location: IOIBUF_X0_Y21_N8
+\button0~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_button0,
+	o => \button0~input_o\);
+
+-- Location: FF_X28_Y27_N27
+\timeCount|en\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	asdata => \timeCount|always0~0_combout\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|en~q\);
+
+-- Location: LCCOMB_X28_Y27_N0
+\timeCount|always0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|always0~0_combout\ = ((\timeCount|en~q\ & \button1~input_o\)) # (!\button0~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001100110011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button0~input_o\,
+	datac => \timeCount|en~q\,
+	datad => \button1~input_o\,
+	combout => \timeCount|always0~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N4
+\timeCount|c0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~0_combout\ = (!\timeCount|c2[0]~0_combout\ & (!\timeCount|c0\(0) & !\timeCount|always0~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|c2[0]~0_combout\,
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c0~0_combout\);
+
+-- Location: FF_X28_Y28_N5
+\timeCount|c0[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(0));
+
+-- Location: LCCOMB_X28_Y28_N6
+\timeCount|c0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~1_combout\ = (!\timeCount|always0~0_combout\ & (!\timeCount|c2[0]~0_combout\ & (\timeCount|c0\(0) $ (\timeCount|c0\(1)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000010010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(0),
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c0\(1),
+	datad => \timeCount|c2[0]~0_combout\,
+	combout => \timeCount|c0~1_combout\);
+
+-- Location: FF_X28_Y28_N7
+\timeCount|c0[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~1_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(1));
+
+-- Location: LCCOMB_X28_Y28_N0
+\timeCount|c2[0]~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~0_combout\ = (!\timeCount|c0\(1) & (\timeCount|c0\(3) & (\timeCount|c0\(0) & !\timeCount|c0\(2))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \timeCount|c2[0]~0_combout\);
+
+-- Location: LCCOMB_X29_Y28_N18
+\timeCount|Add3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add3~0_combout\ = (\timeCount|c0\(0) & \timeCount|c0\(1))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|c0\(0),
+	datac => \timeCount|c0\(1),
+	combout => \timeCount|Add3~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N24
+\timeCount|c0~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~2_combout\ = (!\timeCount|c2[0]~0_combout\ & (!\timeCount|always0~0_combout\ & (\timeCount|c0\(2) $ (\timeCount|Add3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~0_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c0\(2),
+	datad => \timeCount|Add3~0_combout\,
+	combout => \timeCount|c0~2_combout\);
+
+-- Location: FF_X28_Y28_N25
+\timeCount|c0[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(2));
+
+-- Location: LCCOMB_X28_Y27_N22
+\timeCount|c0[3]~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0[3]~3_combout\ = (\button0~input_o\ & (!\timeCount|c2[0]~0_combout\ & ((!\timeCount|en~q\) # (!\button1~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button1~input_o\,
+	datab => \button0~input_o\,
+	datac => \timeCount|en~q\,
+	datad => \timeCount|c2[0]~0_combout\,
+	combout => \timeCount|c0[3]~3_combout\);
+
+-- Location: LCCOMB_X28_Y28_N2
+\timeCount|c0~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~4_combout\ = (\timeCount|c0[3]~3_combout\ & (\timeCount|c0\(3) $ (((\timeCount|c0\(2) & \timeCount|Add3~0_combout\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(2),
+	datab => \timeCount|Add3~0_combout\,
+	datac => \timeCount|c0\(3),
+	datad => \timeCount|c0[3]~3_combout\,
+	combout => \timeCount|c0~4_combout\);
+
+-- Location: FF_X28_Y28_N3
+\timeCount|c0[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(3));
+
+-- Location: LCCOMB_X29_Y28_N12
+\dss0|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out~0_combout\ = (!\timeCount|c0\(3) & (!\timeCount|c0\(1) & (\timeCount|c0\(0) $ (\timeCount|c0\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(3),
+	datab => \timeCount|c0\(1),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|out~0_combout\);
+
+-- Location: LCCOMB_X29_Y28_N8
+\dss0|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(0) = (\button2~input_o\ & ((\dss0|out~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(0),
+	datac => \button2~input_o\,
+	datad => \dss0|out~0_combout\,
+	combout => \dss0|out\(0));
+
+-- Location: LCCOMB_X28_Y28_N20
+\dss0|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out~1_combout\ = (!\timeCount|c0\(3) & (\timeCount|c0\(2) & (\timeCount|c0\(1) $ (\timeCount|c0\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001001000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|out~1_combout\);
+
+-- Location: LCCOMB_X28_Y28_N30
+\dss0|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(1) = (\button2~input_o\ & (\dss0|out~1_combout\)) # (!\button2~input_o\ & ((\dss0|out\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out~1_combout\,
+	datac => \dss0|out\(1),
+	datad => \button2~input_o\,
+	combout => \dss0|out\(1));
+
+-- Location: LCCOMB_X28_Y28_N14
+\dss0|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr4~0_combout\ = (\timeCount|c0\(2) & (((\timeCount|c0\(3))))) # (!\timeCount|c0\(2) & (\timeCount|c0\(1) & ((\timeCount|c0\(3)) # (!\timeCount|c0\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000010100010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(0),
+	datac => \timeCount|c0\(3),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N16
+\dss0|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(2) = (\button2~input_o\ & ((\dss0|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(2),
+	datac => \dss0|WideOr4~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss0|out\(2));
+
+-- Location: LCCOMB_X28_Y28_N8
+\dss0|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr3~0_combout\ = (!\timeCount|c0\(3) & ((\timeCount|c0\(1) & (\timeCount|c0\(0) & \timeCount|c0\(2))) # (!\timeCount|c0\(1) & (\timeCount|c0\(0) $ (\timeCount|c0\(2))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000010010100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(0),
+	datac => \timeCount|c0\(2),
+	datad => \timeCount|c0\(3),
+	combout => \dss0|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N18
+\dss0|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(3) = (\button2~input_o\ & ((\dss0|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(3),
+	datac => \dss0|WideOr3~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss0|out\(3));
+
+-- Location: LCCOMB_X28_Y28_N10
+\dss0|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr2~0_combout\ = (\timeCount|c0\(1) & (!\timeCount|c0\(3) & (\timeCount|c0\(0)))) # (!\timeCount|c0\(1) & ((\timeCount|c0\(2) & (!\timeCount|c0\(3))) # (!\timeCount|c0\(2) & ((\timeCount|c0\(0))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011000101110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N28
+\dss0|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(4) = (\button2~input_o\ & ((\dss0|WideOr2~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(4)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(4),
+	datac => \button2~input_o\,
+	datad => \dss0|WideOr2~0_combout\,
+	combout => \dss0|out\(4));
+
+-- Location: LCCOMB_X28_Y28_N12
+\dss0|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr1~0_combout\ = (!\timeCount|c0\(3) & ((\timeCount|c0\(1) & ((\timeCount|c0\(0)) # (!\timeCount|c0\(2)))) # (!\timeCount|c0\(1) & (!\timeCount|c0\(2) & \timeCount|c0\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000101100000010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(2),
+	datac => \timeCount|c0\(3),
+	datad => \timeCount|c0\(0),
+	combout => \dss0|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X29_Y28_N10
+\dss0|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(5) = (\button2~input_o\ & ((\dss0|WideOr1~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101000001010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss0|out\(5),
+	datac => \button2~input_o\,
+	datad => \dss0|WideOr1~0_combout\,
+	combout => \dss0|out\(5));
+
+-- Location: LCCOMB_X28_Y28_N26
+\dss0|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr0~0_combout\ = (\timeCount|c0\(3)) # ((\timeCount|c0\(1) & ((!\timeCount|c0\(2)) # (!\timeCount|c0\(0)))) # (!\timeCount|c0\(1) & ((\timeCount|c0\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1101111111101110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N22
+\dss0|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(6) = (\button2~input_o\ & ((!\dss0|WideOr0~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(6)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111110101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss0|out\(6),
+	datac => \dss0|WideOr0~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss0|out\(6));
+
+-- Location: LCCOMB_X27_Y27_N22
+\timeCount|c1~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~1_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & (\timeCount|c1\(1) $ (\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \timeCount|c1~1_combout\);
+
+-- Location: FF_X27_Y27_N23
+\timeCount|c1[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~1_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(1));
+
+-- Location: LCCOMB_X26_Y27_N22
+\timeCount|Add2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add2~0_combout\ = \timeCount|c1\(2) $ (((\timeCount|c1\(0) & \timeCount|c1\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110101001101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(2),
+	datab => \timeCount|c1\(0),
+	datac => \timeCount|c1\(1),
+	combout => \timeCount|Add2~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N4
+\timeCount|c1~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~2_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|Add2~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|Add2~0_combout\,
+	combout => \timeCount|c1~2_combout\);
+
+-- Location: FF_X27_Y27_N5
+\timeCount|c1[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~2_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(2));
+
+-- Location: LCCOMB_X26_Y27_N24
+\timeCount|Add2~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add2~1_combout\ = \timeCount|c1\(3) $ (((\timeCount|c1\(0) & (\timeCount|c1\(1) & \timeCount|c1\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110110011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(0),
+	datab => \timeCount|c1\(3),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(2),
+	combout => \timeCount|Add2~1_combout\);
+
+-- Location: LCCOMB_X27_Y27_N26
+\timeCount|c1~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~3_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|Add2~1_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|Add2~1_combout\,
+	combout => \timeCount|c1~3_combout\);
+
+-- Location: FF_X27_Y27_N27
+\timeCount|c1[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~3_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(3));
+
+-- Location: LCCOMB_X27_Y27_N20
+\timeCount|c2[0]~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~1_combout\ = (!\timeCount|c1\(1) & (!\timeCount|c1\(2) & (\timeCount|c1\(3) & \timeCount|c1\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(1),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(3),
+	datad => \timeCount|c1\(0),
+	combout => \timeCount|c2[0]~1_combout\);
+
+-- Location: LCCOMB_X27_Y27_N0
+\timeCount|c1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~0_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & !\timeCount|c1\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c1\(0),
+	combout => \timeCount|c1~0_combout\);
+
+-- Location: FF_X27_Y27_N1
+\timeCount|c1[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~0_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(0));
+
+-- Location: LCCOMB_X27_Y27_N12
+\dss1|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out~0_combout\ = (!\timeCount|c1\(1) & (!\timeCount|c1\(3) & (\timeCount|c1\(0) $ (\timeCount|c1\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(0),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(3),
+	combout => \dss1|out~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N6
+\dss1|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(0) = (\button2~input_o\ & ((\dss1|out~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|out\(0),
+	datad => \dss1|out~0_combout\,
+	combout => \dss1|out\(0));
+
+-- Location: LCCOMB_X27_Y27_N30
+\dss1|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out~1_combout\ = (!\timeCount|c1\(3) & (\timeCount|c1\(2) & (\timeCount|c1\(1) $ (\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010001000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|out~1_combout\);
+
+-- Location: LCCOMB_X27_Y27_N28
+\dss1|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(1) = (\button2~input_o\ & (\dss1|out~1_combout\)) # (!\button2~input_o\ & ((\dss1|out\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111010110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|out~1_combout\,
+	datad => \dss1|out\(1),
+	combout => \dss1|out\(1));
+
+-- Location: LCCOMB_X26_Y27_N28
+\dss1|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr4~0_combout\ = (\timeCount|c1\(2) & (((\timeCount|c1\(3))))) # (!\timeCount|c1\(2) & (\timeCount|c1\(1) & ((\timeCount|c1\(3)) # (!\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110111000000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(2),
+	datab => \timeCount|c1\(1),
+	datac => \timeCount|c1\(0),
+	datad => \timeCount|c1\(3),
+	combout => \dss1|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X26_Y27_N30
+\dss1|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(2) = (\button2~input_o\ & ((\dss1|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss1|out\(2),
+	datad => \dss1|WideOr4~0_combout\,
+	combout => \dss1|out\(2));
+
+-- Location: LCCOMB_X27_Y27_N16
+\dss1|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr3~0_combout\ = (!\timeCount|c1\(3) & ((\timeCount|c1\(2) & (\timeCount|c1\(1) $ (!\timeCount|c1\(0)))) # (!\timeCount|c1\(2) & (!\timeCount|c1\(1) & \timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100000100000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X26_Y27_N8
+\dss1|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(3) = (\button2~input_o\ & ((\dss1|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss1|out\(3),
+	datad => \dss1|WideOr3~0_combout\,
+	combout => \dss1|out\(3));
+
+-- Location: LCCOMB_X27_Y27_N10
+\dss1|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr2~0_combout\ = (\timeCount|c1\(1) & (\timeCount|c1\(0) & ((!\timeCount|c1\(3))))) # (!\timeCount|c1\(1) & ((\timeCount|c1\(2) & ((!\timeCount|c1\(3)))) # (!\timeCount|c1\(2) & (\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000001010101110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(0),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(3),
+	combout => \dss1|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N2
+\dss1|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(4) = (\button2~input_o\ & ((\dss1|WideOr2~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(4)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|out\(4),
+	datad => \dss1|WideOr2~0_combout\,
+	combout => \dss1|out\(4));
+
+-- Location: LCCOMB_X27_Y27_N8
+\dss1|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr1~0_combout\ = (!\timeCount|c1\(3) & ((\timeCount|c1\(2) & (\timeCount|c1\(1) & \timeCount|c1\(0))) # (!\timeCount|c1\(2) & ((\timeCount|c1\(1)) # (\timeCount|c1\(0))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N24
+\dss1|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(5) = (\button2~input_o\ & (\dss1|WideOr1~0_combout\)) # (!\button2~input_o\ & ((\dss1|out\(5))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111010110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|WideOr1~0_combout\,
+	datad => \dss1|out\(5),
+	combout => \dss1|out\(5));
+
+-- Location: LCCOMB_X27_Y27_N14
+\dss1|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr0~0_combout\ = (\timeCount|c1\(3)) # ((\timeCount|c1\(2) & ((!\timeCount|c1\(0)) # (!\timeCount|c1\(1)))) # (!\timeCount|c1\(2) & (\timeCount|c1\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1011111011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N18
+\dss1|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(6) = (\button2~input_o\ & (!\dss1|WideOr0~0_combout\)) # (!\button2~input_o\ & ((\dss1|out\(6))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111100001010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|WideOr0~0_combout\,
+	datad => \dss1|out\(6),
+	combout => \dss1|out\(6));
+
+-- Location: LCCOMB_X28_Y27_N16
+\timeCount|c2~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~3_combout\ = (!\timeCount|c2[0]~2_combout\ & (!\timeCount|c2\(0) & !\timeCount|always0~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c2~3_combout\);
+
+-- Location: LCCOMB_X28_Y27_N18
+\timeCount|c2[0]~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~4_combout\ = (\timeCount|always0~0_combout\) # ((\timeCount|c2[0]~1_combout\ & \timeCount|c2[0]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|c2[0]~0_combout\,
+	combout => \timeCount|c2[0]~4_combout\);
+
+-- Location: FF_X28_Y27_N17
+\timeCount|c2[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~3_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(0));
+
+-- Location: LCCOMB_X28_Y27_N6
+\timeCount|c2~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~5_combout\ = (!\timeCount|c2[0]~2_combout\ & (!\timeCount|always0~0_combout\ & (\timeCount|c2\(0) $ (\timeCount|c2\(1)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000010100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(1),
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c2~5_combout\);
+
+-- Location: FF_X28_Y27_N7
+\timeCount|c2[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~5_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(1));
+
+-- Location: LCCOMB_X28_Y27_N26
+\timeCount|Add1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add1~0_combout\ = \timeCount|c2\(2) $ (((\timeCount|c2\(1) & \timeCount|c2\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111011110001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \timeCount|Add1~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N28
+\timeCount|c2~6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~6_combout\ = (!\timeCount|c2[0]~2_combout\ & (\timeCount|Add1~0_combout\ & !\timeCount|always0~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datac => \timeCount|Add1~0_combout\,
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c2~6_combout\);
+
+-- Location: FF_X28_Y27_N29
+\timeCount|c2[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~6_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(2));
+
+-- Location: LCCOMB_X28_Y27_N12
+\timeCount|c2[0]~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~2_combout\ = (!\timeCount|c2\(1) & (\timeCount|c2\(0) & (\timeCount|c2\(3) & !\timeCount|c2\(2))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \timeCount|c2[0]~2_combout\);
+
+-- Location: LCCOMB_X28_Y27_N20
+\timeCount|Add1~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add1~1_combout\ = \timeCount|c2\(3) $ (((\timeCount|c2\(1) & (\timeCount|c2\(0) & \timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \timeCount|Add1~1_combout\);
+
+-- Location: LCCOMB_X28_Y27_N14
+\timeCount|c2~7\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~7_combout\ = (!\timeCount|c2[0]~2_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|Add1~1_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001000000010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|Add1~1_combout\,
+	combout => \timeCount|c2~7_combout\);
+
+-- Location: FF_X28_Y27_N15
+\timeCount|c2[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~7_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(3));
+
+-- Location: LCCOMB_X29_Y27_N24
+\dss2|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out~0_combout\ = (!\timeCount|c2\(3) & (!\timeCount|c2\(1) & (\timeCount|c2\(0) $ (\timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|out~0_combout\);
+
+-- Location: LCCOMB_X29_Y27_N8
+\dss2|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(0) = (\button2~input_o\ & ((\dss2|out~0_combout\))) # (!\button2~input_o\ & (\dss2|out\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(0),
+	datad => \dss2|out~0_combout\,
+	combout => \dss2|out\(0));
+
+-- Location: LCCOMB_X29_Y27_N18
+\dss2|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out~1_combout\ = (!\timeCount|c2\(3) & (\timeCount|c2\(2) & (\timeCount|c2\(1) $ (\timeCount|c2\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001010000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|out~1_combout\);
+
+-- Location: LCCOMB_X29_Y27_N30
+\dss2|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(1) = (\button2~input_o\ & ((\dss2|out~1_combout\))) # (!\button2~input_o\ & (\dss2|out\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(1),
+	datad => \dss2|out~1_combout\,
+	combout => \dss2|out\(1));
+
+-- Location: LCCOMB_X29_Y27_N28
+\dss2|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr4~0_combout\ = (\timeCount|c2\(2) & (\timeCount|c2\(3))) # (!\timeCount|c2\(2) & (\timeCount|c2\(1) & ((\timeCount|c2\(3)) # (!\timeCount|c2\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101010001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X29_Y27_N4
+\dss2|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(2) = (\button2~input_o\ & ((\dss2|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss2|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(2),
+	datad => \dss2|WideOr4~0_combout\,
+	combout => \dss2|out\(2));
+
+-- Location: LCCOMB_X29_Y27_N6
+\dss2|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr3~0_combout\ = (!\timeCount|c2\(3) & ((\timeCount|c2\(1) & (\timeCount|c2\(0) & \timeCount|c2\(2))) # (!\timeCount|c2\(1) & (\timeCount|c2\(0) $ (\timeCount|c2\(2))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X29_Y27_N26
+\dss2|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(3) = (\button2~input_o\ & ((\dss2|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss2|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(3),
+	datad => \dss2|WideOr3~0_combout\,
+	combout => \dss2|out\(3));
+
+-- Location: LCCOMB_X28_Y27_N4
+\dss2|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr2~0_combout\ = (\timeCount|c2\(1) & (\timeCount|c2\(0) & (!\timeCount|c2\(3)))) # (!\timeCount|c2\(1) & ((\timeCount|c2\(2) & ((!\timeCount|c2\(3)))) # (!\timeCount|c2\(2) & (\timeCount|c2\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110101001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N2
+\dss2|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(4) = (\button2~input_o\ & (\dss2|WideOr2~0_combout\)) # (!\button2~input_o\ & ((\dss2|out\(4))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss2|WideOr2~0_combout\,
+	datad => \dss2|out\(4),
+	combout => \dss2|out\(4));
+
+-- Location: LCCOMB_X28_Y27_N30
+\dss2|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr1~0_combout\ = (!\timeCount|c2\(3) & ((\timeCount|c2\(1) & ((\timeCount|c2\(0)) # (!\timeCount|c2\(2)))) # (!\timeCount|c2\(1) & (\timeCount|c2\(0) & !\timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100000001110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N24
+\dss2|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(5) = (\button2~input_o\ & (\dss2|WideOr1~0_combout\)) # (!\button2~input_o\ & ((\dss2|out\(5))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss2|WideOr1~0_combout\,
+	datad => \dss2|out\(5),
+	combout => \dss2|out\(5));
+
+-- Location: LCCOMB_X28_Y27_N8
+\dss2|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr0~0_combout\ = (\timeCount|c2\(3)) # ((\timeCount|c2\(1) & ((!\timeCount|c2\(2)) # (!\timeCount|c2\(0)))) # (!\timeCount|c2\(1) & ((\timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011111111010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N10
+\dss2|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(6) = (\button2~input_o\ & (!\dss2|WideOr0~0_combout\)) # (!\button2~input_o\ & ((\dss2|out\(6))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011111100001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss2|WideOr0~0_combout\,
+	datad => \dss2|out\(6),
+	combout => \dss2|out\(6));
+
+-- Location: LCCOMB_X26_Y28_N8
+\timeCount|Add0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add0~0_combout\ = \timeCount|c3\(2) $ (((\timeCount|c3\(1) & \timeCount|c3\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(2),
+	combout => \timeCount|Add0~0_combout\);
+
+-- Location: LCCOMB_X26_Y28_N6
+\timeCount|c3~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~4_combout\ = (!\timeCount|always0~0_combout\ & (\timeCount|Add0~0_combout\ & \timeCount|c3[1]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datac => \timeCount|Add0~0_combout\,
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~4_combout\);
+
+-- Location: LCCOMB_X27_Y28_N28
+\timeCount|c3[1]~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3[1]~2_combout\ = (\timeCount|always0~0_combout\) # ((\timeCount|c2[0]~1_combout\ & (\timeCount|c2[0]~0_combout\ & \timeCount|c2[0]~2_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datab => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|c2[0]~0_combout\,
+	datad => \timeCount|c2[0]~2_combout\,
+	combout => \timeCount|c3[1]~2_combout\);
+
+-- Location: FF_X27_Y28_N17
+\timeCount|c3[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	asdata => \timeCount|c3~4_combout\,
+	sload => VCC,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(2));
+
+-- Location: LCCOMB_X26_Y28_N10
+\timeCount|c3[1]~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3[1]~0_combout\ = (\timeCount|c3\(1)) # ((\timeCount|c3\(2)) # ((!\timeCount|c3\(3)) # (!\timeCount|c3\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110111111111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(3),
+	combout => \timeCount|c3[1]~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N0
+\timeCount|c3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~1_combout\ = (!\timeCount|always0~0_combout\ & (!\timeCount|c3\(0) & \timeCount|c3[1]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~1_combout\);
+
+-- Location: FF_X27_Y28_N1
+\timeCount|c3[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c3~1_combout\,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(0));
+
+-- Location: LCCOMB_X27_Y28_N30
+\timeCount|c3~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~3_combout\ = (!\timeCount|always0~0_combout\ & (\timeCount|c3[1]~0_combout\ & (\timeCount|c3\(0) $ (\timeCount|c3\(1)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001010000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(1),
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~3_combout\);
+
+-- Location: FF_X27_Y28_N31
+\timeCount|c3[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c3~3_combout\,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(1));
+
+-- Location: LCCOMB_X26_Y28_N24
+\timeCount|Add0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add0~1_combout\ = \timeCount|c3\(3) $ (((\timeCount|c3\(1) & (\timeCount|c3\(2) & \timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111111110000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(3),
+	combout => \timeCount|Add0~1_combout\);
+
+-- Location: LCCOMB_X27_Y28_N26
+\timeCount|c3~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~5_combout\ = (\timeCount|Add0~1_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|c3[1]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|Add0~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~5_combout\);
+
+-- Location: FF_X27_Y28_N27
+\timeCount|c3[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c3~5_combout\,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(3));
+
+-- Location: LCCOMB_X27_Y28_N24
+\dss3|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out~0_combout\ = (!\timeCount|c3\(3) & (!\timeCount|c3\(1) & (\timeCount|c3\(2) $ (\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(3),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(1),
+	datad => \timeCount|c3\(0),
+	combout => \dss3|out~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N10
+\dss3|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(0) = (\button2~input_o\ & (\dss3|out~0_combout\)) # (!\button2~input_o\ & ((\dss3|out\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100111111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out~0_combout\,
+	datac => \button2~input_o\,
+	datad => \dss3|out\(0),
+	combout => \dss3|out\(0));
+
+-- Location: LCCOMB_X27_Y28_N2
+\dss3|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out~1_combout\ = (\timeCount|c3\(2) & (!\timeCount|c3\(3) & (\timeCount|c3\(1) $ (\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010000001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(0),
+	combout => \dss3|out~1_combout\);
+
+-- Location: LCCOMB_X27_Y28_N16
+\dss3|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(1) = (\button2~input_o\ & ((\dss3|out~1_combout\))) # (!\button2~input_o\ & (\dss3|out\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110010101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss3|out\(1),
+	datab => \dss3|out~1_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(1));
+
+-- Location: LCCOMB_X26_Y28_N12
+\dss3|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr4~0_combout\ = (\timeCount|c3\(2) & (((\timeCount|c3\(3))))) # (!\timeCount|c3\(2) & (\timeCount|c3\(1) & ((\timeCount|c3\(3)) # (!\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110010001010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(3),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X26_Y28_N18
+\dss3|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(2) = (\button2~input_o\ & ((\dss3|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out\(2),
+	datac => \button2~input_o\,
+	datad => \dss3|WideOr4~0_combout\,
+	combout => \dss3|out\(2));
+
+-- Location: LCCOMB_X27_Y28_N8
+\dss3|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr3~0_combout\ = (!\timeCount|c3\(3) & ((\timeCount|c3\(1) & (\timeCount|c3\(0) & \timeCount|c3\(2))) # (!\timeCount|c3\(1) & (\timeCount|c3\(0) $ (\timeCount|c3\(2))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100100000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N20
+\dss3|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(3) = (\button2~input_o\ & ((\dss3|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out\(3),
+	datac => \dss3|WideOr3~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(3));
+
+-- Location: LCCOMB_X27_Y28_N22
+\dss3|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr2~0_combout\ = (\timeCount|c3\(1) & (\timeCount|c3\(0) & (!\timeCount|c3\(3)))) # (!\timeCount|c3\(1) & ((\timeCount|c3\(2) & ((!\timeCount|c3\(3)))) # (!\timeCount|c3\(2) & (\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110101001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N18
+\dss3|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(4) = (\button2~input_o\ & ((\dss3|WideOr2~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(4)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out\(4),
+	datac => \dss3|WideOr2~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(4));
+
+-- Location: LCCOMB_X27_Y28_N4
+\dss3|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr1~0_combout\ = (!\timeCount|c3\(3) & ((\timeCount|c3\(1) & ((\timeCount|c3\(0)) # (!\timeCount|c3\(2)))) # (!\timeCount|c3\(1) & (\timeCount|c3\(0) & !\timeCount|c3\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100000001110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N12
+\dss3|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(5) = (\button2~input_o\ & ((\dss3|WideOr1~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000010101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss3|out\(5),
+	datac => \dss3|WideOr1~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(5));
+
+-- Location: LCCOMB_X27_Y28_N14
+\dss3|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr0~0_combout\ = (\timeCount|c3\(3)) # ((\timeCount|c3\(1) & ((!\timeCount|c3\(0)) # (!\timeCount|c3\(2)))) # (!\timeCount|c3\(1) & (\timeCount|c3\(2))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(0),
+	combout => \dss3|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N6
+\dss3|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(6) = (\button2~input_o\ & ((!\dss3|WideOr0~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(6)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111110101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss3|out\(6),
+	datac => \dss3|WideOr0~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(6));
+
+ww_hex0(0) <= \hex0[0]~output_o\;
+
+ww_hex0(1) <= \hex0[1]~output_o\;
+
+ww_hex0(2) <= \hex0[2]~output_o\;
+
+ww_hex0(3) <= \hex0[3]~output_o\;
+
+ww_hex0(4) <= \hex0[4]~output_o\;
+
+ww_hex0(5) <= \hex0[5]~output_o\;
+
+ww_hex0(6) <= \hex0[6]~output_o\;
+
+ww_hex1(0) <= \hex1[0]~output_o\;
+
+ww_hex1(1) <= \hex1[1]~output_o\;
+
+ww_hex1(2) <= \hex1[2]~output_o\;
+
+ww_hex1(3) <= \hex1[3]~output_o\;
+
+ww_hex1(4) <= \hex1[4]~output_o\;
+
+ww_hex1(5) <= \hex1[5]~output_o\;
+
+ww_hex1(6) <= \hex1[6]~output_o\;
+
+ww_hex2(0) <= \hex2[0]~output_o\;
+
+ww_hex2(1) <= \hex2[1]~output_o\;
+
+ww_hex2(2) <= \hex2[2]~output_o\;
+
+ww_hex2(3) <= \hex2[3]~output_o\;
+
+ww_hex2(4) <= \hex2[4]~output_o\;
+
+ww_hex2(5) <= \hex2[5]~output_o\;
+
+ww_hex2(6) <= \hex2[6]~output_o\;
+
+ww_hex3(0) <= \hex3[0]~output_o\;
+
+ww_hex3(1) <= \hex3[1]~output_o\;
+
+ww_hex3(2) <= \hex3[2]~output_o\;
+
+ww_hex3(3) <= \hex3[3]~output_o\;
+
+ww_hex3(4) <= \hex3[4]~output_o\;
+
+ww_hex3(5) <= \hex3[5]~output_o\;
+
+ww_hex3(6) <= \hex3[6]~output_o\;
+
+ww_decimal_point <= \decimal_point~output_o\;
+END structure;
+
+
diff --git a/stopClockVerilog/simulation/modelsim/stopclock_6_1200mv_0c_vhd_slow.sdo b/stopClockVerilog/simulation/modelsim/stopclock_6_1200mv_0c_vhd_slow.sdo
new file mode 100644
index 0000000..b3b515e
--- /dev/null
+++ b/stopClockVerilog/simulation/modelsim/stopclock_6_1200mv_0c_vhd_slow.sdo
@@ -0,0 +1,2657 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16U484C6 Package UFBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16U484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "stopclock")
+  (DATE "03/02/2016 15:24:50")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (877:877:877) (820:820:820))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (946:946:946) (879:879:879))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (469:469:469) (436:436:436))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (449:449:449) (419:419:419))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (652:652:652) (610:610:610))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (448:448:448) (420:420:420))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (642:642:642) (601:601:601))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (724:724:724) (691:691:691))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (753:753:753) (718:718:718))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (734:734:734) (714:714:714))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (736:736:736) (694:694:694))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (966:966:966) (918:918:918))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (709:709:709) (671:671:671))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (681:681:681) (646:646:646))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (681:681:681) (652:652:652))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (605:605:605) (608:608:608))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (466:466:466) (445:445:445))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (699:699:699) (668:668:668))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (678:678:678) (646:646:646))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (715:715:715) (679:679:679))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1043:1043:1043) (966:966:966))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (836:836:836) (775:775:775))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1190:1190:1190) (1099:1099:1099))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (813:813:813) (761:761:761))
+        (IOPATH i o (2080:2080:2080) (2029:2029:2029))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (870:870:870) (800:800:800))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1026:1026:1026) (954:954:954))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1025:1025:1025) (943:943:943))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1025:1025:1025) (950:950:950))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\button2\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\clk\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (745:745:745) (906:906:906))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\clk\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (140:140:140) (130:130:130))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\button1\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|start\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2964:2964:2964) (3186:3186:3186))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|start\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1666:1666:1666))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[0\]\~18\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (228:228:228) (300:300:300))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1642:1642:1642) (1665:1665:1665))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (958:958:958) (1017:1017:1017))
+        (PORT ena (1068:1068:1068) (1039:1039:1039))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[1\]\~20\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (229:229:229) (300:300:300))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1642:1642:1642) (1665:1665:1665))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (958:958:958) (1017:1017:1017))
+        (PORT ena (1068:1068:1068) (1039:1039:1039))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[2\]\~22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (227:227:227) (301:301:301))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1312:1312:1312) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (958:958:958) (1017:1017:1017))
+        (PORT ena (1093:1093:1093) (1068:1068:1068))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[3\]\~24\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (240:240:240) (310:310:310))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1312:1312:1312) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (958:958:958) (1017:1017:1017))
+        (PORT ena (1093:1093:1093) (1068:1068:1068))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[4\]\~26\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (229:229:229) (303:303:303))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1312:1312:1312) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (958:958:958) (1017:1017:1017))
+        (PORT ena (1093:1093:1093) (1068:1068:1068))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[5\]\~28\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (379:379:379) (422:422:422))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1312:1312:1312) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (958:958:958) (1017:1017:1017))
+        (PORT ena (1093:1093:1093) (1068:1068:1068))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[6\]\~30\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (229:229:229) (305:305:305))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1312:1312:1312) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (958:958:958) (1017:1017:1017))
+        (PORT ena (1093:1093:1093) (1068:1068:1068))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[7\]\~32\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (226:226:226) (298:298:298))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[7\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1642:1642:1642) (1665:1665:1665))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (958:958:958) (1017:1017:1017))
+        (PORT ena (1068:1068:1068) (1039:1039:1039))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[8\]\~34\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (229:229:229) (305:305:305))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[8\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1312:1312:1312) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (958:958:958) (1017:1017:1017))
+        (PORT ena (1093:1093:1093) (1068:1068:1068))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[9\]\~36\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (238:238:238) (307:307:307))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[9\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (656:656:656) (676:676:676))
+        (PORT ena (1084:1084:1084) (1060:1060:1060))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[10\]\~38\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (238:238:238) (307:307:307))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[10\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (656:656:656) (676:676:676))
+        (PORT ena (1084:1084:1084) (1060:1060:1060))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[11\]\~40\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (239:239:239) (308:308:308))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[11\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (656:656:656) (676:676:676))
+        (PORT ena (1084:1084:1084) (1060:1060:1060))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[12\]\~42\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (229:229:229) (306:306:306))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[12\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (656:656:656) (676:676:676))
+        (PORT ena (1084:1084:1084) (1060:1060:1060))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[13\]\~44\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (227:227:227) (300:300:300))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[13\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (656:656:656) (676:676:676))
+        (PORT ena (1084:1084:1084) (1060:1060:1060))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[14\]\~46\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (309:309:309))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[14\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (656:656:656) (676:676:676))
+        (PORT ena (1084:1084:1084) (1060:1060:1060))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[15\]\~48\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (306:306:306))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[15\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (656:656:656) (676:676:676))
+        (PORT ena (1084:1084:1084) (1060:1060:1060))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[16\]\~50\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (229:229:229) (301:301:301))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[16\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (656:656:656) (676:676:676))
+        (PORT ena (1084:1084:1084) (1060:1060:1060))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[17\]\~52\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (205:205:205) (267:267:267))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[17\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1329:1329:1329))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (656:656:656) (676:676:676))
+        (PORT ena (1084:1084:1084) (1060:1060:1060))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (309:309:309))
+        (PORT datab (229:229:229) (301:301:301))
+        (PORT datac (202:202:202) (274:274:274))
+        (PORT datad (206:206:206) (269:269:269))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (265:265:265) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (309:309:309))
+        (PORT datac (203:203:203) (275:275:275))
+        (PORT datad (217:217:217) (275:275:275))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (308:308:308))
+        (PORT datab (375:375:375) (422:422:422))
+        (PORT datac (523:523:523) (537:537:537))
+        (PORT datad (524:524:524) (536:536:536))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (380:380:380) (424:424:424))
+        (PORT datab (228:228:228) (302:302:302))
+        (PORT datac (202:202:202) (273:273:273))
+        (PORT datad (205:205:205) (267:267:267))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datab combout (295:295:295) (294:294:294))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (184:184:184) (220:220:220))
+        (PORT datab (230:230:230) (303:303:303))
+        (PORT datac (156:156:156) (186:186:186))
+        (PORT datad (159:159:159) (179:179:179))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (309:309:309))
+        (PORT datab (228:228:228) (301:301:301))
+        (PORT datac (297:297:297) (308:308:308))
+        (PORT datad (521:521:521) (506:506:506))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|clock_out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (223:223:223) (296:296:296))
+        (PORT datab (2964:2964:2964) (3186:3186:3186))
+        (PORT datac (1786:1786:1786) (1808:1808:1808))
+        (PORT datad (184:184:184) (207:207:207))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|clock_out\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (159:159:159) (180:180:180))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|clock_out\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1643:1643:1643) (1666:1666:1666))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\clockConv\|clock_out\~clkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (710:710:710) (738:738:738))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\button0\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|en\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1320:1320:1320))
+        (PORT asdata (870:870:870) (859:859:859))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|always0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3180:3180:3180) (3376:3376:3376))
+        (PORT datac (204:204:204) (274:274:274))
+        (PORT datad (2999:2999:2999) (3230:3230:3230))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (227:227:227) (262:262:262))
+        (PORT datad (583:583:583) (575:575:575))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (397:397:397) (449:449:449))
+        (PORT datab (621:621:621) (611:611:611))
+        (PORT datad (203:203:203) (229:229:229))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (283:283:283) (380:380:380))
+        (PORT datab (282:282:282) (364:364:364))
+        (PORT datac (243:243:243) (323:323:323))
+        (PORT datad (269:269:269) (340:340:340))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (308:308:308) (281:281:281))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (388:388:388) (443:443:443))
+        (PORT datac (359:359:359) (401:401:401))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (398:398:398) (408:408:408))
+        (PORT datab (616:616:616) (609:609:609))
+        (PORT datad (323:323:323) (325:325:325))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\[3\]\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3049:3049:3049) (3276:3276:3276))
+        (PORT datab (3180:3180:3180) (3376:3376:3376))
+        (PORT datac (201:201:201) (271:271:271))
+        (PORT datad (586:586:586) (578:578:578))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (412:412:412) (458:458:458))
+        (PORT datab (364:364:364) (364:364:364))
+        (PORT datad (547:547:547) (534:534:534))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datab combout (295:295:295) (294:294:294))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (423:423:423) (461:461:461))
+        (PORT datab (383:383:383) (425:425:425))
+        (PORT datac (357:357:357) (410:410:410))
+        (PORT datad (383:383:383) (420:420:420))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (201:201:201) (234:234:234))
+        (PORT datac (1566:1566:1566) (1560:1560:1560))
+        (PORT datad (159:159:159) (179:179:179))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (287:287:287) (388:388:388))
+        (PORT datab (284:284:284) (368:368:368))
+        (PORT datac (245:245:245) (327:327:327))
+        (PORT datad (266:266:266) (336:336:336))
+        (IOPATH dataa combout (272:272:272) (269:269:269))
+        (IOPATH datab combout (295:295:295) (285:285:285))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (182:182:182) (214:214:214))
+        (PORT datac (173:173:173) (204:204:204))
+        (PORT datad (1622:1622:1622) (1616:1616:1616))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (285:285:285) (386:386:386))
+        (PORT datab (271:271:271) (355:355:355))
+        (PORT datac (379:379:379) (416:416:416))
+        (PORT datad (266:266:266) (336:336:336))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (201:201:201) (235:235:235))
+        (PORT datac (157:157:157) (187:187:187))
+        (PORT datad (1618:1618:1618) (1612:1612:1612))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (283:283:283) (382:382:382))
+        (PORT datab (269:269:269) (352:352:352))
+        (PORT datac (381:381:381) (421:421:421))
+        (PORT datad (255:255:255) (328:328:328))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (312:312:312))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (201:201:201) (235:235:235))
+        (PORT datac (157:157:157) (188:188:188))
+        (PORT datad (1618:1618:1618) (1615:1615:1615))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (284:284:284) (384:384:384))
+        (PORT datab (282:282:282) (367:367:367))
+        (PORT datac (243:243:243) (327:327:327))
+        (PORT datad (268:268:268) (338:338:338))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (199:199:199) (233:233:233))
+        (PORT datac (1559:1559:1559) (1558:1558:1558))
+        (PORT datad (160:160:160) (182:182:182))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (284:284:284) (383:383:383))
+        (PORT datab (293:293:293) (374:374:374))
+        (PORT datac (379:379:379) (416:416:416))
+        (PORT datad (371:371:371) (411:411:411))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (202:202:202) (240:240:240))
+        (PORT datac (1566:1566:1566) (1562:1562:1562))
+        (PORT datad (303:303:303) (308:308:308))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (286:286:286) (387:387:387))
+        (PORT datab (284:284:284) (369:369:369))
+        (PORT datac (245:245:245) (328:328:328))
+        (PORT datad (265:265:265) (331:331:331))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (202:202:202) (239:239:239))
+        (PORT datac (156:156:156) (186:186:186))
+        (PORT datad (1621:1621:1621) (1612:1612:1612))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (366:366:366) (385:385:385))
+        (PORT datab (421:421:421) (436:436:436))
+        (PORT datad (605:605:605) (630:630:630))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1301:1301:1301) (1321:1321:1321))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (930:930:930) (911:911:911))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (439:439:439) (475:475:475))
+        (PORT datab (440:440:440) (483:483:483))
+        (PORT datac (598:598:598) (617:617:617))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (390:390:390))
+        (PORT datac (388:388:388) (402:402:402))
+        (PORT datad (291:291:291) (296:296:296))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1301:1301:1301) (1321:1321:1321))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (930:930:930) (911:911:911))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add2\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (665:665:665) (694:694:694))
+        (PORT datab (437:437:437) (470:470:470))
+        (PORT datac (598:598:598) (617:617:617))
+        (PORT datad (393:393:393) (432:432:432))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (366:366:366) (385:385:385))
+        (PORT datac (392:392:392) (408:408:408))
+        (PORT datad (306:306:306) (314:314:314))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1301:1301:1301) (1321:1321:1321))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (930:930:930) (911:911:911))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (297:297:297) (388:388:388))
+        (PORT datab (278:278:278) (374:374:374))
+        (PORT datac (260:260:260) (347:347:347))
+        (PORT datad (245:245:245) (311:311:311))
+        (IOPATH dataa combout (267:267:267) (269:269:269))
+        (IOPATH datab combout (267:267:267) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (389:389:389))
+        (PORT datab (417:417:417) (429:429:429))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1301:1301:1301) (1321:1321:1321))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (930:930:930) (911:911:911))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (435:435:435) (484:484:484))
+        (PORT datab (273:273:273) (365:365:365))
+        (PORT datac (270:270:270) (354:354:354))
+        (PORT datad (381:381:381) (413:413:413))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1397:1397:1397) (1433:1433:1433))
+        (PORT datac (303:303:303) (310:310:310))
+        (PORT datad (159:159:159) (179:179:179))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (286:286:286) (373:373:373))
+        (PORT datab (277:277:277) (372:372:372))
+        (PORT datac (265:265:265) (348:348:348))
+        (PORT datad (246:246:246) (311:311:311))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (308:308:308) (281:281:281))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1398:1398:1398) (1434:1434:1434))
+        (PORT datac (154:154:154) (185:185:185))
+        (PORT datad (176:176:176) (198:198:198))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (437:437:437) (476:476:476))
+        (PORT datab (426:426:426) (459:459:459))
+        (PORT datac (409:409:409) (454:454:454))
+        (PORT datad (397:397:397) (433:433:433))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1416:1416:1416) (1424:1424:1424))
+        (PORT datac (173:173:173) (205:205:205))
+        (PORT datad (158:158:158) (178:178:178))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (287:287:287) (377:377:377))
+        (PORT datab (275:275:275) (367:367:367))
+        (PORT datac (268:268:268) (353:353:353))
+        (PORT datad (244:244:244) (310:310:310))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1416:1416:1416) (1425:1425:1425))
+        (PORT datac (175:175:175) (206:206:206))
+        (PORT datad (295:295:295) (293:293:293))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (435:435:435) (484:484:484))
+        (PORT datab (274:274:274) (366:366:366))
+        (PORT datac (270:270:270) (354:354:354))
+        (PORT datad (381:381:381) (414:414:414))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1400:1400:1400) (1438:1438:1438))
+        (PORT datac (304:304:304) (311:311:311))
+        (PORT datad (159:159:159) (179:179:179))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (286:286:286) (375:375:375))
+        (PORT datab (273:273:273) (366:366:366))
+        (PORT datac (269:269:269) (353:353:353))
+        (PORT datad (240:240:240) (305:305:305))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1398:1398:1398) (1433:1433:1433))
+        (PORT datac (157:157:157) (187:187:187))
+        (PORT datad (177:177:177) (199:199:199))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (287:287:287) (378:378:378))
+        (PORT datab (275:275:275) (370:370:370))
+        (PORT datac (268:268:268) (355:355:355))
+        (PORT datad (242:242:242) (308:308:308))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1397:1397:1397) (1438:1438:1438))
+        (PORT datac (157:157:157) (188:188:188))
+        (PORT datad (178:178:178) (200:200:200))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (227:227:227) (279:279:279))
+        (PORT datad (219:219:219) (251:251:251))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (372:372:372) (384:384:384))
+        (PORT datac (560:560:560) (553:553:553))
+        (PORT datad (589:589:589) (579:579:579))
+        (IOPATH datab combout (273:273:273) (275:275:275))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (717:717:717) (715:715:715))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (225:225:225) (275:275:275))
+        (PORT datab (276:276:276) (370:370:370))
+        (PORT datad (215:215:215) (247:247:247))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (312:312:312))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (717:717:717) (715:715:715))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (282:282:282) (377:377:377))
+        (PORT datab (277:277:277) (368:368:368))
+        (PORT datad (249:249:249) (313:313:313))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (228:228:228) (280:280:280))
+        (PORT datac (529:529:529) (515:515:515))
+        (PORT datad (220:220:220) (252:252:252))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (717:717:717) (715:715:715))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (376:376:376))
+        (PORT datab (278:278:278) (373:373:373))
+        (PORT datac (239:239:239) (317:317:317))
+        (PORT datad (252:252:252) (319:319:319))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (308:308:308) (281:281:281))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add1\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (377:377:377))
+        (PORT datab (278:278:278) (374:374:374))
+        (PORT datac (240:240:240) (320:320:320))
+        (PORT datad (251:251:251) (318:318:318))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datab combout (295:295:295) (294:294:294))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~7\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (227:227:227) (279:279:279))
+        (PORT datab (243:243:243) (283:283:283))
+        (PORT datac (294:294:294) (299:299:299))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (717:717:717) (715:715:715))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (406:406:406) (457:457:457))
+        (PORT datab (399:399:399) (446:446:446))
+        (PORT datac (375:375:375) (415:415:415))
+        (PORT datad (388:388:388) (430:430:430))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1402:1402:1402) (1421:1421:1421))
+        (PORT datac (175:175:175) (206:206:206))
+        (PORT datad (160:160:160) (181:181:181))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (404:404:404) (461:461:461))
+        (PORT datab (399:399:399) (449:449:449))
+        (PORT datac (375:375:375) (418:418:418))
+        (PORT datad (390:390:390) (434:434:434))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (273:273:273) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1403:1403:1403) (1422:1422:1422))
+        (PORT datac (173:173:173) (205:205:205))
+        (PORT datad (159:159:159) (179:179:179))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (406:406:406) (462:462:462))
+        (PORT datab (399:399:399) (450:450:450))
+        (PORT datac (375:375:375) (416:416:416))
+        (PORT datad (388:388:388) (429:429:429))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1402:1402:1402) (1421:1421:1421))
+        (PORT datac (174:174:174) (205:205:205))
+        (PORT datad (160:160:160) (182:182:182))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (403:403:403) (456:456:456))
+        (PORT datab (395:395:395) (444:444:444))
+        (PORT datac (373:373:373) (415:415:415))
+        (PORT datad (392:392:392) (432:432:432))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1403:1403:1403) (1422:1422:1422))
+        (PORT datac (174:174:174) (205:205:205))
+        (PORT datad (161:161:161) (182:182:182))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (274:274:274) (367:367:367))
+        (PORT datab (273:273:273) (366:366:366))
+        (PORT datac (236:236:236) (313:313:313))
+        (PORT datad (247:247:247) (315:315:315))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1367:1367:1367) (1387:1387:1387))
+        (PORT datac (155:155:155) (185:185:185))
+        (PORT datad (176:176:176) (198:198:198))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (376:376:376))
+        (PORT datab (276:276:276) (366:366:366))
+        (PORT datac (239:239:239) (317:317:317))
+        (PORT datad (249:249:249) (312:312:312))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1365:1365:1365) (1383:1383:1383))
+        (PORT datac (155:155:155) (186:186:186))
+        (PORT datad (177:177:177) (199:199:199))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (275:275:275) (369:369:369))
+        (PORT datab (274:274:274) (366:366:366))
+        (PORT datac (236:236:236) (314:314:314))
+        (PORT datad (248:248:248) (315:315:315))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (295:295:295) (285:285:285))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1364:1364:1364) (1388:1388:1388))
+        (PORT datac (156:156:156) (187:187:187))
+        (PORT datad (178:178:178) (200:200:200))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (443:443:443) (489:489:489))
+        (PORT datac (399:399:399) (442:442:442))
+        (PORT datad (375:375:375) (415:415:415))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (621:621:621) (605:605:605))
+        (PORT datac (157:157:157) (187:187:187))
+        (PORT datad (178:178:178) (199:199:199))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\[1\]\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (610:610:610) (608:608:608))
+        (PORT datab (570:570:570) (556:556:556))
+        (PORT datac (369:369:369) (374:374:374))
+        (PORT datad (525:525:525) (510:510:510))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1321:1321:1321))
+        (PORT asdata (604:604:604) (602:602:602))
+        (PORT ena (745:745:745) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\[1\]\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (441:441:441) (492:492:492))
+        (PORT datab (400:400:400) (453:453:453))
+        (PORT datac (399:399:399) (443:443:443))
+        (PORT datad (390:390:390) (431:431:431))
+        (IOPATH dataa combout (273:273:273) (269:269:269))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (616:616:616) (616:616:616))
+        (PORT datad (340:340:340) (346:346:346))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1321:1321:1321))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (745:745:745) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (611:611:611) (609:609:609))
+        (PORT datab (284:284:284) (373:373:373))
+        (PORT datad (341:341:341) (351:351:351))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (273:273:273) (275:275:275))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1321:1321:1321))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (745:745:745) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (437:437:437) (486:486:486))
+        (PORT datab (400:400:400) (448:448:448))
+        (PORT datac (402:402:402) (446:446:446))
+        (PORT datad (388:388:388) (427:427:427))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (344:344:344) (351:351:351))
+        (PORT datac (582:582:582) (577:577:577))
+        (PORT datad (341:341:341) (351:351:351))
+        (IOPATH datab combout (273:273:273) (275:275:275))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1321:1321:1321))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (745:745:745) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (269:269:269) (355:355:355))
+        (PORT datab (269:269:269) (352:352:352))
+        (PORT datac (244:244:244) (333:333:333))
+        (PORT datad (255:255:255) (334:334:334))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (183:183:183) (217:217:217))
+        (PORT datac (1557:1557:1557) (1576:1576:1576))
+        (PORT datad (178:178:178) (200:200:200))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (280:280:280) (375:375:375))
+        (PORT datab (273:273:273) (358:358:358))
+        (PORT datac (248:248:248) (330:330:330))
+        (PORT datad (248:248:248) (325:325:325))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (571:571:571) (564:564:564))
+        (PORT datab (183:183:183) (217:217:217))
+        (PORT datad (1579:1579:1579) (1607:1607:1607))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (438:438:438) (488:488:488))
+        (PORT datab (426:426:426) (464:464:464))
+        (PORT datac (398:398:398) (441:441:441))
+        (PORT datad (373:373:373) (416:416:416))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (201:201:201) (235:235:235))
+        (PORT datac (1564:1564:1564) (1567:1567:1567))
+        (PORT datad (160:160:160) (181:181:181))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (277:277:277) (373:373:373))
+        (PORT datab (275:275:275) (362:362:362))
+        (PORT datac (244:244:244) (325:325:325))
+        (PORT datad (245:245:245) (317:317:317))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (201:201:201) (235:235:235))
+        (PORT datac (157:157:157) (188:188:188))
+        (PORT datad (1579:1579:1579) (1609:1609:1609))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (273:273:273) (367:367:367))
+        (PORT datab (281:281:281) (369:369:369))
+        (PORT datac (242:242:242) (323:323:323))
+        (PORT datad (244:244:244) (316:316:316))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (201:201:201) (235:235:235))
+        (PORT datac (156:156:156) (187:187:187))
+        (PORT datad (1579:1579:1579) (1609:1609:1609))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (277:277:277) (374:374:374))
+        (PORT datab (274:274:274) (361:361:361))
+        (PORT datac (243:243:243) (325:325:325))
+        (PORT datad (245:245:245) (317:317:317))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (202:202:202) (240:240:240))
+        (PORT datac (156:156:156) (187:187:187))
+        (PORT datad (1579:1579:1579) (1603:1603:1603))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (276:276:276) (372:372:372))
+        (PORT datab (272:272:272) (355:355:355))
+        (PORT datac (245:245:245) (326:326:326))
+        (PORT datad (252:252:252) (330:330:330))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (201:201:201) (238:238:238))
+        (PORT datac (156:156:156) (185:185:185))
+        (PORT datad (1579:1579:1579) (1604:1604:1604))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+)
diff --git a/stopClockVerilog/simulation/modelsim/stopclock_6_1200mv_85c_slow.vho b/stopClockVerilog/simulation/modelsim/stopclock_6_1200mv_85c_slow.vho
new file mode 100644
index 0000000..766487c
--- /dev/null
+++ b/stopClockVerilog/simulation/modelsim/stopclock_6_1200mv_85c_slow.vho
@@ -0,0 +1,3227 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "03/02/2016 15:24:50"
+
+-- 
+-- Device: Altera EP3C16U484C6 Package UFBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	stopclock IS
+    PORT (
+	clk : IN std_logic;
+	button0 : IN std_logic;
+	button1 : IN std_logic;
+	button2 : IN std_logic;
+	hex0 : BUFFER std_logic_vector(6 DOWNTO 0);
+	hex1 : BUFFER std_logic_vector(6 DOWNTO 0);
+	hex2 : BUFFER std_logic_vector(6 DOWNTO 0);
+	hex3 : BUFFER std_logic_vector(6 DOWNTO 0);
+	decimal_point : BUFFER std_logic
+	);
+END stopclock;
+
+-- Design Ports Information
+-- hex0[0]	=>  Location: PIN_E11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[1]	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[2]	=>  Location: PIN_H12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[3]	=>  Location: PIN_H13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[4]	=>  Location: PIN_G12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[5]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[6]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[0]	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[1]	=>  Location: PIN_B13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[2]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[3]	=>  Location: PIN_A14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[4]	=>  Location: PIN_B14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[5]	=>  Location: PIN_E14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[6]	=>  Location: PIN_A15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[0]	=>  Location: PIN_D15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[1]	=>  Location: PIN_A16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[2]	=>  Location: PIN_B16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[3]	=>  Location: PIN_E15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[4]	=>  Location: PIN_A17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[5]	=>  Location: PIN_B17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[6]	=>  Location: PIN_F14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[0]	=>  Location: PIN_B18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[1]	=>  Location: PIN_F15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[2]	=>  Location: PIN_A19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[3]	=>  Location: PIN_B19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[4]	=>  Location: PIN_C19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[5]	=>  Location: PIN_D19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[6]	=>  Location: PIN_G15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- decimal_point	=>  Location: PIN_A18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- button2	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- button0	=>  Location: PIN_H2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- button1	=>  Location: PIN_G3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- clk	=>  Location: PIN_G21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF stopclock IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_clk : std_logic;
+SIGNAL ww_button0 : std_logic;
+SIGNAL ww_button1 : std_logic;
+SIGNAL ww_button2 : std_logic;
+SIGNAL ww_hex0 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_hex1 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_hex2 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_hex3 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_decimal_point : std_logic;
+SIGNAL \clockConv|clock_out~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \hex0[0]~output_o\ : std_logic;
+SIGNAL \hex0[1]~output_o\ : std_logic;
+SIGNAL \hex0[2]~output_o\ : std_logic;
+SIGNAL \hex0[3]~output_o\ : std_logic;
+SIGNAL \hex0[4]~output_o\ : std_logic;
+SIGNAL \hex0[5]~output_o\ : std_logic;
+SIGNAL \hex0[6]~output_o\ : std_logic;
+SIGNAL \hex1[0]~output_o\ : std_logic;
+SIGNAL \hex1[1]~output_o\ : std_logic;
+SIGNAL \hex1[2]~output_o\ : std_logic;
+SIGNAL \hex1[3]~output_o\ : std_logic;
+SIGNAL \hex1[4]~output_o\ : std_logic;
+SIGNAL \hex1[5]~output_o\ : std_logic;
+SIGNAL \hex1[6]~output_o\ : std_logic;
+SIGNAL \hex2[0]~output_o\ : std_logic;
+SIGNAL \hex2[1]~output_o\ : std_logic;
+SIGNAL \hex2[2]~output_o\ : std_logic;
+SIGNAL \hex2[3]~output_o\ : std_logic;
+SIGNAL \hex2[4]~output_o\ : std_logic;
+SIGNAL \hex2[5]~output_o\ : std_logic;
+SIGNAL \hex2[6]~output_o\ : std_logic;
+SIGNAL \hex3[0]~output_o\ : std_logic;
+SIGNAL \hex3[1]~output_o\ : std_logic;
+SIGNAL \hex3[2]~output_o\ : std_logic;
+SIGNAL \hex3[3]~output_o\ : std_logic;
+SIGNAL \hex3[4]~output_o\ : std_logic;
+SIGNAL \hex3[5]~output_o\ : std_logic;
+SIGNAL \hex3[6]~output_o\ : std_logic;
+SIGNAL \decimal_point~output_o\ : std_logic;
+SIGNAL \button2~input_o\ : std_logic;
+SIGNAL \clk~input_o\ : std_logic;
+SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
+SIGNAL \button1~input_o\ : std_logic;
+SIGNAL \clockConv|start~0_combout\ : std_logic;
+SIGNAL \clockConv|start~q\ : std_logic;
+SIGNAL \clockConv|ctr[0]~18_combout\ : std_logic;
+SIGNAL \clockConv|ctr[0]~19\ : std_logic;
+SIGNAL \clockConv|ctr[1]~20_combout\ : std_logic;
+SIGNAL \clockConv|ctr[1]~21\ : std_logic;
+SIGNAL \clockConv|ctr[2]~22_combout\ : std_logic;
+SIGNAL \clockConv|ctr[2]~23\ : std_logic;
+SIGNAL \clockConv|ctr[3]~24_combout\ : std_logic;
+SIGNAL \clockConv|ctr[3]~25\ : std_logic;
+SIGNAL \clockConv|ctr[4]~26_combout\ : std_logic;
+SIGNAL \clockConv|ctr[4]~27\ : std_logic;
+SIGNAL \clockConv|ctr[5]~28_combout\ : std_logic;
+SIGNAL \clockConv|ctr[5]~29\ : std_logic;
+SIGNAL \clockConv|ctr[6]~30_combout\ : std_logic;
+SIGNAL \clockConv|ctr[6]~31\ : std_logic;
+SIGNAL \clockConv|ctr[7]~32_combout\ : std_logic;
+SIGNAL \clockConv|ctr[7]~33\ : std_logic;
+SIGNAL \clockConv|ctr[8]~34_combout\ : std_logic;
+SIGNAL \clockConv|ctr[8]~35\ : std_logic;
+SIGNAL \clockConv|ctr[9]~36_combout\ : std_logic;
+SIGNAL \clockConv|ctr[9]~37\ : std_logic;
+SIGNAL \clockConv|ctr[10]~38_combout\ : std_logic;
+SIGNAL \clockConv|ctr[10]~39\ : std_logic;
+SIGNAL \clockConv|ctr[11]~40_combout\ : std_logic;
+SIGNAL \clockConv|ctr[11]~41\ : std_logic;
+SIGNAL \clockConv|ctr[12]~42_combout\ : std_logic;
+SIGNAL \clockConv|ctr[12]~43\ : std_logic;
+SIGNAL \clockConv|ctr[13]~44_combout\ : std_logic;
+SIGNAL \clockConv|ctr[13]~45\ : std_logic;
+SIGNAL \clockConv|ctr[14]~46_combout\ : std_logic;
+SIGNAL \clockConv|ctr[14]~47\ : std_logic;
+SIGNAL \clockConv|ctr[15]~48_combout\ : std_logic;
+SIGNAL \clockConv|ctr[15]~49\ : std_logic;
+SIGNAL \clockConv|ctr[16]~50_combout\ : std_logic;
+SIGNAL \clockConv|ctr[16]~51\ : std_logic;
+SIGNAL \clockConv|ctr[17]~52_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~0_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~3_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~1_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~2_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~4_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~5_combout\ : std_logic;
+SIGNAL \clockConv|clock_out~0_combout\ : std_logic;
+SIGNAL \clockConv|clock_out~feeder_combout\ : std_logic;
+SIGNAL \clockConv|clock_out~q\ : std_logic;
+SIGNAL \clockConv|clock_out~clkctrl_outclk\ : std_logic;
+SIGNAL \button0~input_o\ : std_logic;
+SIGNAL \timeCount|en~q\ : std_logic;
+SIGNAL \timeCount|always0~0_combout\ : std_logic;
+SIGNAL \timeCount|c0~0_combout\ : std_logic;
+SIGNAL \timeCount|c0~1_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~0_combout\ : std_logic;
+SIGNAL \timeCount|Add3~0_combout\ : std_logic;
+SIGNAL \timeCount|c0~2_combout\ : std_logic;
+SIGNAL \timeCount|c0[3]~3_combout\ : std_logic;
+SIGNAL \timeCount|c0~4_combout\ : std_logic;
+SIGNAL \dss0|out~0_combout\ : std_logic;
+SIGNAL \dss0|out~1_combout\ : std_logic;
+SIGNAL \dss0|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr0~0_combout\ : std_logic;
+SIGNAL \timeCount|c1~1_combout\ : std_logic;
+SIGNAL \timeCount|Add2~0_combout\ : std_logic;
+SIGNAL \timeCount|c1~2_combout\ : std_logic;
+SIGNAL \timeCount|Add2~1_combout\ : std_logic;
+SIGNAL \timeCount|c1~3_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~1_combout\ : std_logic;
+SIGNAL \timeCount|c1~0_combout\ : std_logic;
+SIGNAL \dss1|out~0_combout\ : std_logic;
+SIGNAL \dss1|out~1_combout\ : std_logic;
+SIGNAL \dss1|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr0~0_combout\ : std_logic;
+SIGNAL \timeCount|c2~3_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~4_combout\ : std_logic;
+SIGNAL \timeCount|c2~5_combout\ : std_logic;
+SIGNAL \timeCount|Add1~0_combout\ : std_logic;
+SIGNAL \timeCount|c2~6_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~2_combout\ : std_logic;
+SIGNAL \timeCount|Add1~1_combout\ : std_logic;
+SIGNAL \timeCount|c2~7_combout\ : std_logic;
+SIGNAL \dss2|out~0_combout\ : std_logic;
+SIGNAL \dss2|out~1_combout\ : std_logic;
+SIGNAL \dss2|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr0~0_combout\ : std_logic;
+SIGNAL \timeCount|Add0~0_combout\ : std_logic;
+SIGNAL \timeCount|c3~4_combout\ : std_logic;
+SIGNAL \timeCount|c3[1]~2_combout\ : std_logic;
+SIGNAL \timeCount|c3[1]~0_combout\ : std_logic;
+SIGNAL \timeCount|c3~1_combout\ : std_logic;
+SIGNAL \timeCount|c3~3_combout\ : std_logic;
+SIGNAL \timeCount|Add0~1_combout\ : std_logic;
+SIGNAL \timeCount|c3~5_combout\ : std_logic;
+SIGNAL \dss3|out~0_combout\ : std_logic;
+SIGNAL \dss3|out~1_combout\ : std_logic;
+SIGNAL \dss3|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr0~0_combout\ : std_logic;
+SIGNAL \dss1|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \dss2|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \dss3|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \clockConv|ctr\ : std_logic_vector(17 DOWNTO 0);
+SIGNAL \timeCount|c3\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \timeCount|c2\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \timeCount|c1\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \timeCount|c0\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \dss0|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \timeCount|ALT_INV_c0[3]~3_combout\ : std_logic;
+SIGNAL \clockConv|ALT_INV_LessThan0~5_combout\ : std_logic;
+
+BEGIN
+
+ww_clk <= clk;
+ww_button0 <= button0;
+ww_button1 <= button1;
+ww_button2 <= button2;
+hex0 <= ww_hex0;
+hex1 <= ww_hex1;
+hex2 <= ww_hex2;
+hex3 <= ww_hex3;
+decimal_point <= ww_decimal_point;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\clockConv|clock_out~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clockConv|clock_out~q\);
+
+\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);
+\timeCount|ALT_INV_c0[3]~3_combout\ <= NOT \timeCount|c0[3]~3_combout\;
+\clockConv|ALT_INV_LessThan0~5_combout\ <= NOT \clockConv|LessThan0~5_combout\;
+
+-- Location: IOOBUF_X21_Y29_N23
+\hex0[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(0),
+	devoe => ww_devoe,
+	o => \hex0[0]~output_o\);
+
+-- Location: IOOBUF_X21_Y29_N30
+\hex0[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(1),
+	devoe => ww_devoe,
+	o => \hex0[1]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N2
+\hex0[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(2),
+	devoe => ww_devoe,
+	o => \hex0[2]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N30
+\hex0[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(3),
+	devoe => ww_devoe,
+	o => \hex0[3]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N9
+\hex0[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(4),
+	devoe => ww_devoe,
+	o => \hex0[4]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N23
+\hex0[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(5),
+	devoe => ww_devoe,
+	o => \hex0[5]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N16
+\hex0[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(6),
+	devoe => ww_devoe,
+	o => \hex0[6]~output_o\);
+
+-- Location: IOOBUF_X21_Y29_N2
+\hex1[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(0),
+	devoe => ww_devoe,
+	o => \hex1[0]~output_o\);
+
+-- Location: IOOBUF_X21_Y29_N9
+\hex1[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(1),
+	devoe => ww_devoe,
+	o => \hex1[1]~output_o\);
+
+-- Location: IOOBUF_X23_Y29_N2
+\hex1[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(2),
+	devoe => ww_devoe,
+	o => \hex1[2]~output_o\);
+
+-- Location: IOOBUF_X23_Y29_N23
+\hex1[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(3),
+	devoe => ww_devoe,
+	o => \hex1[3]~output_o\);
+
+-- Location: IOOBUF_X23_Y29_N30
+\hex1[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(4),
+	devoe => ww_devoe,
+	o => \hex1[4]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N16
+\hex1[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(5),
+	devoe => ww_devoe,
+	o => \hex1[5]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N23
+\hex1[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(6),
+	devoe => ww_devoe,
+	o => \hex1[6]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N30
+\hex2[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(0),
+	devoe => ww_devoe,
+	o => \hex2[0]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N30
+\hex2[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(1),
+	devoe => ww_devoe,
+	o => \hex2[1]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N2
+\hex2[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(2),
+	devoe => ww_devoe,
+	o => \hex2[2]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N2
+\hex2[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(3),
+	devoe => ww_devoe,
+	o => \hex2[3]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N16
+\hex2[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(4),
+	devoe => ww_devoe,
+	o => \hex2[4]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N23
+\hex2[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(5),
+	devoe => ww_devoe,
+	o => \hex2[5]~output_o\);
+
+-- Location: IOOBUF_X37_Y29_N2
+\hex2[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(6),
+	devoe => ww_devoe,
+	o => \hex2[6]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N23
+\hex3[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(0),
+	devoe => ww_devoe,
+	o => \hex3[0]~output_o\);
+
+-- Location: IOOBUF_X39_Y29_N16
+\hex3[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(1),
+	devoe => ww_devoe,
+	o => \hex3[1]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N9
+\hex3[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(2),
+	devoe => ww_devoe,
+	o => \hex3[2]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N2
+\hex3[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(3),
+	devoe => ww_devoe,
+	o => \hex3[3]~output_o\);
+
+-- Location: IOOBUF_X37_Y29_N23
+\hex3[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(4),
+	devoe => ww_devoe,
+	o => \hex3[4]~output_o\);
+
+-- Location: IOOBUF_X37_Y29_N30
+\hex3[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(5),
+	devoe => ww_devoe,
+	o => \hex3[5]~output_o\);
+
+-- Location: IOOBUF_X39_Y29_N30
+\hex3[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(6),
+	devoe => ww_devoe,
+	o => \hex3[6]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N16
+\decimal_point~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => GND,
+	devoe => ww_devoe,
+	o => \decimal_point~output_o\);
+
+-- Location: IOIBUF_X0_Y23_N1
+\button2~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_button2,
+	o => \button2~input_o\);
+
+-- Location: IOIBUF_X41_Y15_N1
+\clk~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_clk,
+	o => \clk~input_o\);
+
+-- Location: CLKCTRL_G9
+\clk~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \clk~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \clk~inputclkctrl_outclk\);
+
+-- Location: IOIBUF_X0_Y23_N15
+\button1~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_button1,
+	o => \button1~input_o\);
+
+-- Location: LCCOMB_X19_Y27_N26
+\clockConv|start~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|start~0_combout\ = (\clockConv|start~q\) # (!\button1~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001111110011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button1~input_o\,
+	datac => \clockConv|start~q\,
+	combout => \clockConv|start~0_combout\);
+
+-- Location: FF_X19_Y27_N27
+\clockConv|start\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|start~q\);
+
+-- Location: LCCOMB_X19_Y28_N14
+\clockConv|ctr[0]~18\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[0]~18_combout\ = \clockConv|ctr\(0) $ (VCC)
+-- \clockConv|ctr[0]~19\ = CARRY(\clockConv|ctr\(0))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011001111001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(0),
+	datad => VCC,
+	combout => \clockConv|ctr[0]~18_combout\,
+	cout => \clockConv|ctr[0]~19\);
+
+-- Location: FF_X19_Y28_N15
+\clockConv|ctr[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[0]~18_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(0));
+
+-- Location: LCCOMB_X19_Y28_N16
+\clockConv|ctr[1]~20\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[1]~20_combout\ = (\clockConv|ctr\(1) & (!\clockConv|ctr[0]~19\)) # (!\clockConv|ctr\(1) & ((\clockConv|ctr[0]~19\) # (GND)))
+-- \clockConv|ctr[1]~21\ = CARRY((!\clockConv|ctr[0]~19\) # (!\clockConv|ctr\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(1),
+	datad => VCC,
+	cin => \clockConv|ctr[0]~19\,
+	combout => \clockConv|ctr[1]~20_combout\,
+	cout => \clockConv|ctr[1]~21\);
+
+-- Location: FF_X19_Y28_N17
+\clockConv|ctr[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[1]~20_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(1));
+
+-- Location: LCCOMB_X19_Y28_N18
+\clockConv|ctr[2]~22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[2]~22_combout\ = (\clockConv|ctr\(2) & (\clockConv|ctr[1]~21\ $ (GND))) # (!\clockConv|ctr\(2) & (!\clockConv|ctr[1]~21\ & VCC))
+-- \clockConv|ctr[2]~23\ = CARRY((\clockConv|ctr\(2) & !\clockConv|ctr[1]~21\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(2),
+	datad => VCC,
+	cin => \clockConv|ctr[1]~21\,
+	combout => \clockConv|ctr[2]~22_combout\,
+	cout => \clockConv|ctr[2]~23\);
+
+-- Location: FF_X19_Y28_N19
+\clockConv|ctr[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[2]~22_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(2));
+
+-- Location: LCCOMB_X19_Y28_N20
+\clockConv|ctr[3]~24\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[3]~24_combout\ = (\clockConv|ctr\(3) & (!\clockConv|ctr[2]~23\)) # (!\clockConv|ctr\(3) & ((\clockConv|ctr[2]~23\) # (GND)))
+-- \clockConv|ctr[3]~25\ = CARRY((!\clockConv|ctr[2]~23\) # (!\clockConv|ctr\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(3),
+	datad => VCC,
+	cin => \clockConv|ctr[2]~23\,
+	combout => \clockConv|ctr[3]~24_combout\,
+	cout => \clockConv|ctr[3]~25\);
+
+-- Location: FF_X19_Y28_N21
+\clockConv|ctr[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[3]~24_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(3));
+
+-- Location: LCCOMB_X19_Y28_N22
+\clockConv|ctr[4]~26\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[4]~26_combout\ = (\clockConv|ctr\(4) & (\clockConv|ctr[3]~25\ $ (GND))) # (!\clockConv|ctr\(4) & (!\clockConv|ctr[3]~25\ & VCC))
+-- \clockConv|ctr[4]~27\ = CARRY((\clockConv|ctr\(4) & !\clockConv|ctr[3]~25\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(4),
+	datad => VCC,
+	cin => \clockConv|ctr[3]~25\,
+	combout => \clockConv|ctr[4]~26_combout\,
+	cout => \clockConv|ctr[4]~27\);
+
+-- Location: FF_X19_Y28_N23
+\clockConv|ctr[4]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[4]~26_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(4));
+
+-- Location: LCCOMB_X19_Y28_N24
+\clockConv|ctr[5]~28\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[5]~28_combout\ = (\clockConv|ctr\(5) & (!\clockConv|ctr[4]~27\)) # (!\clockConv|ctr\(5) & ((\clockConv|ctr[4]~27\) # (GND)))
+-- \clockConv|ctr[5]~29\ = CARRY((!\clockConv|ctr[4]~27\) # (!\clockConv|ctr\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(5),
+	datad => VCC,
+	cin => \clockConv|ctr[4]~27\,
+	combout => \clockConv|ctr[5]~28_combout\,
+	cout => \clockConv|ctr[5]~29\);
+
+-- Location: FF_X19_Y28_N25
+\clockConv|ctr[5]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[5]~28_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(5));
+
+-- Location: LCCOMB_X19_Y28_N26
+\clockConv|ctr[6]~30\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[6]~30_combout\ = (\clockConv|ctr\(6) & (\clockConv|ctr[5]~29\ $ (GND))) # (!\clockConv|ctr\(6) & (!\clockConv|ctr[5]~29\ & VCC))
+-- \clockConv|ctr[6]~31\ = CARRY((\clockConv|ctr\(6) & !\clockConv|ctr[5]~29\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(6),
+	datad => VCC,
+	cin => \clockConv|ctr[5]~29\,
+	combout => \clockConv|ctr[6]~30_combout\,
+	cout => \clockConv|ctr[6]~31\);
+
+-- Location: FF_X19_Y28_N27
+\clockConv|ctr[6]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[6]~30_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(6));
+
+-- Location: LCCOMB_X19_Y28_N28
+\clockConv|ctr[7]~32\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[7]~32_combout\ = (\clockConv|ctr\(7) & (!\clockConv|ctr[6]~31\)) # (!\clockConv|ctr\(7) & ((\clockConv|ctr[6]~31\) # (GND)))
+-- \clockConv|ctr[7]~33\ = CARRY((!\clockConv|ctr[6]~31\) # (!\clockConv|ctr\(7)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(7),
+	datad => VCC,
+	cin => \clockConv|ctr[6]~31\,
+	combout => \clockConv|ctr[7]~32_combout\,
+	cout => \clockConv|ctr[7]~33\);
+
+-- Location: FF_X19_Y28_N29
+\clockConv|ctr[7]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[7]~32_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(7));
+
+-- Location: LCCOMB_X19_Y28_N30
+\clockConv|ctr[8]~34\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[8]~34_combout\ = (\clockConv|ctr\(8) & (\clockConv|ctr[7]~33\ $ (GND))) # (!\clockConv|ctr\(8) & (!\clockConv|ctr[7]~33\ & VCC))
+-- \clockConv|ctr[8]~35\ = CARRY((\clockConv|ctr\(8) & !\clockConv|ctr[7]~33\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(8),
+	datad => VCC,
+	cin => \clockConv|ctr[7]~33\,
+	combout => \clockConv|ctr[8]~34_combout\,
+	cout => \clockConv|ctr[8]~35\);
+
+-- Location: FF_X19_Y28_N31
+\clockConv|ctr[8]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[8]~34_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(8));
+
+-- Location: LCCOMB_X19_Y27_N0
+\clockConv|ctr[9]~36\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[9]~36_combout\ = (\clockConv|ctr\(9) & (!\clockConv|ctr[8]~35\)) # (!\clockConv|ctr\(9) & ((\clockConv|ctr[8]~35\) # (GND)))
+-- \clockConv|ctr[9]~37\ = CARRY((!\clockConv|ctr[8]~35\) # (!\clockConv|ctr\(9)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(9),
+	datad => VCC,
+	cin => \clockConv|ctr[8]~35\,
+	combout => \clockConv|ctr[9]~36_combout\,
+	cout => \clockConv|ctr[9]~37\);
+
+-- Location: FF_X19_Y27_N1
+\clockConv|ctr[9]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[9]~36_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(9));
+
+-- Location: LCCOMB_X19_Y27_N2
+\clockConv|ctr[10]~38\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[10]~38_combout\ = (\clockConv|ctr\(10) & (\clockConv|ctr[9]~37\ $ (GND))) # (!\clockConv|ctr\(10) & (!\clockConv|ctr[9]~37\ & VCC))
+-- \clockConv|ctr[10]~39\ = CARRY((\clockConv|ctr\(10) & !\clockConv|ctr[9]~37\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(10),
+	datad => VCC,
+	cin => \clockConv|ctr[9]~37\,
+	combout => \clockConv|ctr[10]~38_combout\,
+	cout => \clockConv|ctr[10]~39\);
+
+-- Location: FF_X19_Y27_N3
+\clockConv|ctr[10]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[10]~38_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(10));
+
+-- Location: LCCOMB_X19_Y27_N4
+\clockConv|ctr[11]~40\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[11]~40_combout\ = (\clockConv|ctr\(11) & (!\clockConv|ctr[10]~39\)) # (!\clockConv|ctr\(11) & ((\clockConv|ctr[10]~39\) # (GND)))
+-- \clockConv|ctr[11]~41\ = CARRY((!\clockConv|ctr[10]~39\) # (!\clockConv|ctr\(11)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(11),
+	datad => VCC,
+	cin => \clockConv|ctr[10]~39\,
+	combout => \clockConv|ctr[11]~40_combout\,
+	cout => \clockConv|ctr[11]~41\);
+
+-- Location: FF_X19_Y27_N5
+\clockConv|ctr[11]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[11]~40_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(11));
+
+-- Location: LCCOMB_X19_Y27_N6
+\clockConv|ctr[12]~42\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[12]~42_combout\ = (\clockConv|ctr\(12) & (\clockConv|ctr[11]~41\ $ (GND))) # (!\clockConv|ctr\(12) & (!\clockConv|ctr[11]~41\ & VCC))
+-- \clockConv|ctr[12]~43\ = CARRY((\clockConv|ctr\(12) & !\clockConv|ctr[11]~41\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(12),
+	datad => VCC,
+	cin => \clockConv|ctr[11]~41\,
+	combout => \clockConv|ctr[12]~42_combout\,
+	cout => \clockConv|ctr[12]~43\);
+
+-- Location: FF_X19_Y27_N7
+\clockConv|ctr[12]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[12]~42_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(12));
+
+-- Location: LCCOMB_X19_Y27_N8
+\clockConv|ctr[13]~44\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[13]~44_combout\ = (\clockConv|ctr\(13) & (!\clockConv|ctr[12]~43\)) # (!\clockConv|ctr\(13) & ((\clockConv|ctr[12]~43\) # (GND)))
+-- \clockConv|ctr[13]~45\ = CARRY((!\clockConv|ctr[12]~43\) # (!\clockConv|ctr\(13)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(13),
+	datad => VCC,
+	cin => \clockConv|ctr[12]~43\,
+	combout => \clockConv|ctr[13]~44_combout\,
+	cout => \clockConv|ctr[13]~45\);
+
+-- Location: FF_X19_Y27_N9
+\clockConv|ctr[13]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[13]~44_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(13));
+
+-- Location: LCCOMB_X19_Y27_N10
+\clockConv|ctr[14]~46\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[14]~46_combout\ = (\clockConv|ctr\(14) & (\clockConv|ctr[13]~45\ $ (GND))) # (!\clockConv|ctr\(14) & (!\clockConv|ctr[13]~45\ & VCC))
+-- \clockConv|ctr[14]~47\ = CARRY((\clockConv|ctr\(14) & !\clockConv|ctr[13]~45\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(14),
+	datad => VCC,
+	cin => \clockConv|ctr[13]~45\,
+	combout => \clockConv|ctr[14]~46_combout\,
+	cout => \clockConv|ctr[14]~47\);
+
+-- Location: FF_X19_Y27_N11
+\clockConv|ctr[14]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[14]~46_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(14));
+
+-- Location: LCCOMB_X19_Y27_N12
+\clockConv|ctr[15]~48\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[15]~48_combout\ = (\clockConv|ctr\(15) & (!\clockConv|ctr[14]~47\)) # (!\clockConv|ctr\(15) & ((\clockConv|ctr[14]~47\) # (GND)))
+-- \clockConv|ctr[15]~49\ = CARRY((!\clockConv|ctr[14]~47\) # (!\clockConv|ctr\(15)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(15),
+	datad => VCC,
+	cin => \clockConv|ctr[14]~47\,
+	combout => \clockConv|ctr[15]~48_combout\,
+	cout => \clockConv|ctr[15]~49\);
+
+-- Location: FF_X19_Y27_N13
+\clockConv|ctr[15]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[15]~48_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(15));
+
+-- Location: LCCOMB_X19_Y27_N14
+\clockConv|ctr[16]~50\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[16]~50_combout\ = (\clockConv|ctr\(16) & (\clockConv|ctr[15]~49\ $ (GND))) # (!\clockConv|ctr\(16) & (!\clockConv|ctr[15]~49\ & VCC))
+-- \clockConv|ctr[16]~51\ = CARRY((\clockConv|ctr\(16) & !\clockConv|ctr[15]~49\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(16),
+	datad => VCC,
+	cin => \clockConv|ctr[15]~49\,
+	combout => \clockConv|ctr[16]~50_combout\,
+	cout => \clockConv|ctr[16]~51\);
+
+-- Location: FF_X19_Y27_N15
+\clockConv|ctr[16]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[16]~50_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(16));
+
+-- Location: LCCOMB_X19_Y27_N16
+\clockConv|ctr[17]~52\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[17]~52_combout\ = \clockConv|ctr[16]~51\ $ (\clockConv|ctr\(17))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111111110000",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datad => \clockConv|ctr\(17),
+	cin => \clockConv|ctr[16]~51\,
+	combout => \clockConv|ctr[17]~52_combout\);
+
+-- Location: FF_X19_Y27_N17
+\clockConv|ctr[17]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[17]~52_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(17));
+
+-- Location: LCCOMB_X19_Y27_N18
+\clockConv|LessThan0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~0_combout\ = (\clockConv|ctr\(14) & (\clockConv|ctr\(17) & (\clockConv|ctr\(16) & \clockConv|ctr\(15))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(14),
+	datab => \clockConv|ctr\(17),
+	datac => \clockConv|ctr\(16),
+	datad => \clockConv|ctr\(15),
+	combout => \clockConv|LessThan0~0_combout\);
+
+-- Location: LCCOMB_X19_Y28_N12
+\clockConv|LessThan0~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~3_combout\ = (!\clockConv|ctr\(6) & (!\clockConv|ctr\(4) & !\clockConv|ctr\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(6),
+	datac => \clockConv|ctr\(4),
+	datad => \clockConv|ctr\(5),
+	combout => \clockConv|LessThan0~3_combout\);
+
+-- Location: LCCOMB_X19_Y28_N8
+\clockConv|LessThan0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~1_combout\ = (!\clockConv|ctr\(8) & (!\clockConv|ctr\(9) & (!\clockConv|ctr\(10) & !\clockConv|ctr\(11))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(8),
+	datab => \clockConv|ctr\(9),
+	datac => \clockConv|ctr\(10),
+	datad => \clockConv|ctr\(11),
+	combout => \clockConv|LessThan0~1_combout\);
+
+-- Location: LCCOMB_X19_Y28_N10
+\clockConv|LessThan0~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~2_combout\ = (((!\clockConv|ctr\(1)) # (!\clockConv|ctr\(0))) # (!\clockConv|ctr\(2))) # (!\clockConv|ctr\(3))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111111111111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(3),
+	datab => \clockConv|ctr\(2),
+	datac => \clockConv|ctr\(0),
+	datad => \clockConv|ctr\(1),
+	combout => \clockConv|LessThan0~2_combout\);
+
+-- Location: LCCOMB_X19_Y28_N2
+\clockConv|LessThan0~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~4_combout\ = (\clockConv|LessThan0~1_combout\ & (((\clockConv|LessThan0~3_combout\ & \clockConv|LessThan0~2_combout\)) # (!\clockConv|ctr\(7))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1011000000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|LessThan0~3_combout\,
+	datab => \clockConv|ctr\(7),
+	datac => \clockConv|LessThan0~1_combout\,
+	datad => \clockConv|LessThan0~2_combout\,
+	combout => \clockConv|LessThan0~4_combout\);
+
+-- Location: LCCOMB_X19_Y27_N24
+\clockConv|LessThan0~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~5_combout\ = ((!\clockConv|ctr\(13) & ((\clockConv|LessThan0~4_combout\) # (!\clockConv|ctr\(12))))) # (!\clockConv|LessThan0~0_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011111100011111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(12),
+	datab => \clockConv|ctr\(13),
+	datac => \clockConv|LessThan0~0_combout\,
+	datad => \clockConv|LessThan0~4_combout\,
+	combout => \clockConv|LessThan0~5_combout\);
+
+-- Location: LCCOMB_X19_Y27_N28
+\clockConv|clock_out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|clock_out~0_combout\ = \clockConv|clock_out~q\ $ (((!\clockConv|LessThan0~5_combout\ & ((\clockConv|start~q\) # (!\button1~input_o\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000001001011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|start~q\,
+	datab => \button1~input_o\,
+	datac => \clockConv|clock_out~q\,
+	datad => \clockConv|LessThan0~5_combout\,
+	combout => \clockConv|clock_out~0_combout\);
+
+-- Location: LCCOMB_X19_Y27_N22
+\clockConv|clock_out~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|clock_out~feeder_combout\ = \clockConv|clock_out~0_combout\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \clockConv|clock_out~0_combout\,
+	combout => \clockConv|clock_out~feeder_combout\);
+
+-- Location: FF_X19_Y27_N23
+\clockConv|clock_out\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|clock_out~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|clock_out~q\);
+
+-- Location: CLKCTRL_G14
+\clockConv|clock_out~clkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \clockConv|clock_out~clkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \clockConv|clock_out~clkctrl_outclk\);
+
+-- Location: IOIBUF_X0_Y21_N8
+\button0~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_button0,
+	o => \button0~input_o\);
+
+-- Location: FF_X28_Y27_N27
+\timeCount|en\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	asdata => \timeCount|always0~0_combout\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|en~q\);
+
+-- Location: LCCOMB_X28_Y27_N0
+\timeCount|always0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|always0~0_combout\ = ((\timeCount|en~q\ & \button1~input_o\)) # (!\button0~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001100110011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button0~input_o\,
+	datac => \timeCount|en~q\,
+	datad => \button1~input_o\,
+	combout => \timeCount|always0~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N4
+\timeCount|c0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~0_combout\ = (!\timeCount|c2[0]~0_combout\ & (!\timeCount|c0\(0) & !\timeCount|always0~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|c2[0]~0_combout\,
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c0~0_combout\);
+
+-- Location: FF_X28_Y28_N5
+\timeCount|c0[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(0));
+
+-- Location: LCCOMB_X28_Y28_N6
+\timeCount|c0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~1_combout\ = (!\timeCount|always0~0_combout\ & (!\timeCount|c2[0]~0_combout\ & (\timeCount|c0\(0) $ (\timeCount|c0\(1)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000010010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(0),
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c0\(1),
+	datad => \timeCount|c2[0]~0_combout\,
+	combout => \timeCount|c0~1_combout\);
+
+-- Location: FF_X28_Y28_N7
+\timeCount|c0[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~1_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(1));
+
+-- Location: LCCOMB_X28_Y28_N0
+\timeCount|c2[0]~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~0_combout\ = (!\timeCount|c0\(1) & (\timeCount|c0\(3) & (\timeCount|c0\(0) & !\timeCount|c0\(2))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \timeCount|c2[0]~0_combout\);
+
+-- Location: LCCOMB_X29_Y28_N18
+\timeCount|Add3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add3~0_combout\ = (\timeCount|c0\(0) & \timeCount|c0\(1))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|c0\(0),
+	datac => \timeCount|c0\(1),
+	combout => \timeCount|Add3~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N24
+\timeCount|c0~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~2_combout\ = (!\timeCount|c2[0]~0_combout\ & (!\timeCount|always0~0_combout\ & (\timeCount|c0\(2) $ (\timeCount|Add3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~0_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c0\(2),
+	datad => \timeCount|Add3~0_combout\,
+	combout => \timeCount|c0~2_combout\);
+
+-- Location: FF_X28_Y28_N25
+\timeCount|c0[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(2));
+
+-- Location: LCCOMB_X28_Y27_N22
+\timeCount|c0[3]~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0[3]~3_combout\ = (\button0~input_o\ & (!\timeCount|c2[0]~0_combout\ & ((!\timeCount|en~q\) # (!\button1~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button1~input_o\,
+	datab => \button0~input_o\,
+	datac => \timeCount|en~q\,
+	datad => \timeCount|c2[0]~0_combout\,
+	combout => \timeCount|c0[3]~3_combout\);
+
+-- Location: LCCOMB_X28_Y28_N2
+\timeCount|c0~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~4_combout\ = (\timeCount|c0[3]~3_combout\ & (\timeCount|c0\(3) $ (((\timeCount|c0\(2) & \timeCount|Add3~0_combout\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(2),
+	datab => \timeCount|Add3~0_combout\,
+	datac => \timeCount|c0\(3),
+	datad => \timeCount|c0[3]~3_combout\,
+	combout => \timeCount|c0~4_combout\);
+
+-- Location: FF_X28_Y28_N3
+\timeCount|c0[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(3));
+
+-- Location: LCCOMB_X29_Y28_N12
+\dss0|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out~0_combout\ = (!\timeCount|c0\(3) & (!\timeCount|c0\(1) & (\timeCount|c0\(0) $ (\timeCount|c0\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(3),
+	datab => \timeCount|c0\(1),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|out~0_combout\);
+
+-- Location: LCCOMB_X29_Y28_N8
+\dss0|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(0) = (\button2~input_o\ & ((\dss0|out~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(0),
+	datac => \button2~input_o\,
+	datad => \dss0|out~0_combout\,
+	combout => \dss0|out\(0));
+
+-- Location: LCCOMB_X28_Y28_N20
+\dss0|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out~1_combout\ = (!\timeCount|c0\(3) & (\timeCount|c0\(2) & (\timeCount|c0\(1) $ (\timeCount|c0\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001001000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|out~1_combout\);
+
+-- Location: LCCOMB_X28_Y28_N30
+\dss0|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(1) = (\button2~input_o\ & (\dss0|out~1_combout\)) # (!\button2~input_o\ & ((\dss0|out\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out~1_combout\,
+	datac => \dss0|out\(1),
+	datad => \button2~input_o\,
+	combout => \dss0|out\(1));
+
+-- Location: LCCOMB_X28_Y28_N14
+\dss0|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr4~0_combout\ = (\timeCount|c0\(2) & (((\timeCount|c0\(3))))) # (!\timeCount|c0\(2) & (\timeCount|c0\(1) & ((\timeCount|c0\(3)) # (!\timeCount|c0\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000010100010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(0),
+	datac => \timeCount|c0\(3),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N16
+\dss0|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(2) = (\button2~input_o\ & ((\dss0|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(2),
+	datac => \dss0|WideOr4~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss0|out\(2));
+
+-- Location: LCCOMB_X28_Y28_N8
+\dss0|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr3~0_combout\ = (!\timeCount|c0\(3) & ((\timeCount|c0\(1) & (\timeCount|c0\(0) & \timeCount|c0\(2))) # (!\timeCount|c0\(1) & (\timeCount|c0\(0) $ (\timeCount|c0\(2))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000010010100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(0),
+	datac => \timeCount|c0\(2),
+	datad => \timeCount|c0\(3),
+	combout => \dss0|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N18
+\dss0|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(3) = (\button2~input_o\ & ((\dss0|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(3),
+	datac => \dss0|WideOr3~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss0|out\(3));
+
+-- Location: LCCOMB_X28_Y28_N10
+\dss0|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr2~0_combout\ = (\timeCount|c0\(1) & (!\timeCount|c0\(3) & (\timeCount|c0\(0)))) # (!\timeCount|c0\(1) & ((\timeCount|c0\(2) & (!\timeCount|c0\(3))) # (!\timeCount|c0\(2) & ((\timeCount|c0\(0))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011000101110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N28
+\dss0|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(4) = (\button2~input_o\ & ((\dss0|WideOr2~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(4)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(4),
+	datac => \button2~input_o\,
+	datad => \dss0|WideOr2~0_combout\,
+	combout => \dss0|out\(4));
+
+-- Location: LCCOMB_X28_Y28_N12
+\dss0|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr1~0_combout\ = (!\timeCount|c0\(3) & ((\timeCount|c0\(1) & ((\timeCount|c0\(0)) # (!\timeCount|c0\(2)))) # (!\timeCount|c0\(1) & (!\timeCount|c0\(2) & \timeCount|c0\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000101100000010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(2),
+	datac => \timeCount|c0\(3),
+	datad => \timeCount|c0\(0),
+	combout => \dss0|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X29_Y28_N10
+\dss0|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(5) = (\button2~input_o\ & ((\dss0|WideOr1~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101000001010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss0|out\(5),
+	datac => \button2~input_o\,
+	datad => \dss0|WideOr1~0_combout\,
+	combout => \dss0|out\(5));
+
+-- Location: LCCOMB_X28_Y28_N26
+\dss0|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr0~0_combout\ = (\timeCount|c0\(3)) # ((\timeCount|c0\(1) & ((!\timeCount|c0\(2)) # (!\timeCount|c0\(0)))) # (!\timeCount|c0\(1) & ((\timeCount|c0\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1101111111101110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N22
+\dss0|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(6) = (\button2~input_o\ & ((!\dss0|WideOr0~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(6)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111110101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss0|out\(6),
+	datac => \dss0|WideOr0~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss0|out\(6));
+
+-- Location: LCCOMB_X27_Y27_N22
+\timeCount|c1~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~1_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & (\timeCount|c1\(1) $ (\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \timeCount|c1~1_combout\);
+
+-- Location: FF_X27_Y27_N23
+\timeCount|c1[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~1_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(1));
+
+-- Location: LCCOMB_X26_Y27_N22
+\timeCount|Add2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add2~0_combout\ = \timeCount|c1\(2) $ (((\timeCount|c1\(0) & \timeCount|c1\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110101001101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(2),
+	datab => \timeCount|c1\(0),
+	datac => \timeCount|c1\(1),
+	combout => \timeCount|Add2~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N4
+\timeCount|c1~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~2_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|Add2~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|Add2~0_combout\,
+	combout => \timeCount|c1~2_combout\);
+
+-- Location: FF_X27_Y27_N5
+\timeCount|c1[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~2_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(2));
+
+-- Location: LCCOMB_X26_Y27_N24
+\timeCount|Add2~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add2~1_combout\ = \timeCount|c1\(3) $ (((\timeCount|c1\(0) & (\timeCount|c1\(1) & \timeCount|c1\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110110011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(0),
+	datab => \timeCount|c1\(3),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(2),
+	combout => \timeCount|Add2~1_combout\);
+
+-- Location: LCCOMB_X27_Y27_N26
+\timeCount|c1~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~3_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|Add2~1_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|Add2~1_combout\,
+	combout => \timeCount|c1~3_combout\);
+
+-- Location: FF_X27_Y27_N27
+\timeCount|c1[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~3_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(3));
+
+-- Location: LCCOMB_X27_Y27_N20
+\timeCount|c2[0]~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~1_combout\ = (!\timeCount|c1\(1) & (!\timeCount|c1\(2) & (\timeCount|c1\(3) & \timeCount|c1\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(1),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(3),
+	datad => \timeCount|c1\(0),
+	combout => \timeCount|c2[0]~1_combout\);
+
+-- Location: LCCOMB_X27_Y27_N0
+\timeCount|c1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~0_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & !\timeCount|c1\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c1\(0),
+	combout => \timeCount|c1~0_combout\);
+
+-- Location: FF_X27_Y27_N1
+\timeCount|c1[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~0_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(0));
+
+-- Location: LCCOMB_X27_Y27_N12
+\dss1|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out~0_combout\ = (!\timeCount|c1\(1) & (!\timeCount|c1\(3) & (\timeCount|c1\(0) $ (\timeCount|c1\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(0),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(3),
+	combout => \dss1|out~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N6
+\dss1|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(0) = (\button2~input_o\ & ((\dss1|out~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|out\(0),
+	datad => \dss1|out~0_combout\,
+	combout => \dss1|out\(0));
+
+-- Location: LCCOMB_X27_Y27_N30
+\dss1|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out~1_combout\ = (!\timeCount|c1\(3) & (\timeCount|c1\(2) & (\timeCount|c1\(1) $ (\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010001000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|out~1_combout\);
+
+-- Location: LCCOMB_X27_Y27_N28
+\dss1|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(1) = (\button2~input_o\ & (\dss1|out~1_combout\)) # (!\button2~input_o\ & ((\dss1|out\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111010110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|out~1_combout\,
+	datad => \dss1|out\(1),
+	combout => \dss1|out\(1));
+
+-- Location: LCCOMB_X26_Y27_N28
+\dss1|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr4~0_combout\ = (\timeCount|c1\(2) & (((\timeCount|c1\(3))))) # (!\timeCount|c1\(2) & (\timeCount|c1\(1) & ((\timeCount|c1\(3)) # (!\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110111000000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(2),
+	datab => \timeCount|c1\(1),
+	datac => \timeCount|c1\(0),
+	datad => \timeCount|c1\(3),
+	combout => \dss1|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X26_Y27_N30
+\dss1|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(2) = (\button2~input_o\ & ((\dss1|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss1|out\(2),
+	datad => \dss1|WideOr4~0_combout\,
+	combout => \dss1|out\(2));
+
+-- Location: LCCOMB_X27_Y27_N16
+\dss1|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr3~0_combout\ = (!\timeCount|c1\(3) & ((\timeCount|c1\(2) & (\timeCount|c1\(1) $ (!\timeCount|c1\(0)))) # (!\timeCount|c1\(2) & (!\timeCount|c1\(1) & \timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100000100000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X26_Y27_N8
+\dss1|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(3) = (\button2~input_o\ & ((\dss1|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss1|out\(3),
+	datad => \dss1|WideOr3~0_combout\,
+	combout => \dss1|out\(3));
+
+-- Location: LCCOMB_X27_Y27_N10
+\dss1|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr2~0_combout\ = (\timeCount|c1\(1) & (\timeCount|c1\(0) & ((!\timeCount|c1\(3))))) # (!\timeCount|c1\(1) & ((\timeCount|c1\(2) & ((!\timeCount|c1\(3)))) # (!\timeCount|c1\(2) & (\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000001010101110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(0),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(3),
+	combout => \dss1|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N2
+\dss1|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(4) = (\button2~input_o\ & ((\dss1|WideOr2~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(4)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|out\(4),
+	datad => \dss1|WideOr2~0_combout\,
+	combout => \dss1|out\(4));
+
+-- Location: LCCOMB_X27_Y27_N8
+\dss1|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr1~0_combout\ = (!\timeCount|c1\(3) & ((\timeCount|c1\(2) & (\timeCount|c1\(1) & \timeCount|c1\(0))) # (!\timeCount|c1\(2) & ((\timeCount|c1\(1)) # (\timeCount|c1\(0))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N24
+\dss1|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(5) = (\button2~input_o\ & (\dss1|WideOr1~0_combout\)) # (!\button2~input_o\ & ((\dss1|out\(5))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111010110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|WideOr1~0_combout\,
+	datad => \dss1|out\(5),
+	combout => \dss1|out\(5));
+
+-- Location: LCCOMB_X27_Y27_N14
+\dss1|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr0~0_combout\ = (\timeCount|c1\(3)) # ((\timeCount|c1\(2) & ((!\timeCount|c1\(0)) # (!\timeCount|c1\(1)))) # (!\timeCount|c1\(2) & (\timeCount|c1\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1011111011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N18
+\dss1|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(6) = (\button2~input_o\ & (!\dss1|WideOr0~0_combout\)) # (!\button2~input_o\ & ((\dss1|out\(6))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111100001010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|WideOr0~0_combout\,
+	datad => \dss1|out\(6),
+	combout => \dss1|out\(6));
+
+-- Location: LCCOMB_X28_Y27_N16
+\timeCount|c2~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~3_combout\ = (!\timeCount|c2[0]~2_combout\ & (!\timeCount|c2\(0) & !\timeCount|always0~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c2~3_combout\);
+
+-- Location: LCCOMB_X28_Y27_N18
+\timeCount|c2[0]~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~4_combout\ = (\timeCount|always0~0_combout\) # ((\timeCount|c2[0]~1_combout\ & \timeCount|c2[0]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|c2[0]~0_combout\,
+	combout => \timeCount|c2[0]~4_combout\);
+
+-- Location: FF_X28_Y27_N17
+\timeCount|c2[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~3_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(0));
+
+-- Location: LCCOMB_X28_Y27_N6
+\timeCount|c2~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~5_combout\ = (!\timeCount|c2[0]~2_combout\ & (!\timeCount|always0~0_combout\ & (\timeCount|c2\(0) $ (\timeCount|c2\(1)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000010100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(1),
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c2~5_combout\);
+
+-- Location: FF_X28_Y27_N7
+\timeCount|c2[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~5_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(1));
+
+-- Location: LCCOMB_X28_Y27_N26
+\timeCount|Add1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add1~0_combout\ = \timeCount|c2\(2) $ (((\timeCount|c2\(1) & \timeCount|c2\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111011110001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \timeCount|Add1~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N28
+\timeCount|c2~6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~6_combout\ = (!\timeCount|c2[0]~2_combout\ & (\timeCount|Add1~0_combout\ & !\timeCount|always0~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datac => \timeCount|Add1~0_combout\,
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c2~6_combout\);
+
+-- Location: FF_X28_Y27_N29
+\timeCount|c2[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~6_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(2));
+
+-- Location: LCCOMB_X28_Y27_N12
+\timeCount|c2[0]~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~2_combout\ = (!\timeCount|c2\(1) & (\timeCount|c2\(0) & (\timeCount|c2\(3) & !\timeCount|c2\(2))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \timeCount|c2[0]~2_combout\);
+
+-- Location: LCCOMB_X28_Y27_N20
+\timeCount|Add1~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add1~1_combout\ = \timeCount|c2\(3) $ (((\timeCount|c2\(1) & (\timeCount|c2\(0) & \timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \timeCount|Add1~1_combout\);
+
+-- Location: LCCOMB_X28_Y27_N14
+\timeCount|c2~7\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~7_combout\ = (!\timeCount|c2[0]~2_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|Add1~1_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001000000010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|Add1~1_combout\,
+	combout => \timeCount|c2~7_combout\);
+
+-- Location: FF_X28_Y27_N15
+\timeCount|c2[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~7_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(3));
+
+-- Location: LCCOMB_X29_Y27_N24
+\dss2|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out~0_combout\ = (!\timeCount|c2\(3) & (!\timeCount|c2\(1) & (\timeCount|c2\(0) $ (\timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|out~0_combout\);
+
+-- Location: LCCOMB_X29_Y27_N8
+\dss2|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(0) = (\button2~input_o\ & ((\dss2|out~0_combout\))) # (!\button2~input_o\ & (\dss2|out\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(0),
+	datad => \dss2|out~0_combout\,
+	combout => \dss2|out\(0));
+
+-- Location: LCCOMB_X29_Y27_N18
+\dss2|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out~1_combout\ = (!\timeCount|c2\(3) & (\timeCount|c2\(2) & (\timeCount|c2\(1) $ (\timeCount|c2\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001010000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|out~1_combout\);
+
+-- Location: LCCOMB_X29_Y27_N30
+\dss2|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(1) = (\button2~input_o\ & ((\dss2|out~1_combout\))) # (!\button2~input_o\ & (\dss2|out\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(1),
+	datad => \dss2|out~1_combout\,
+	combout => \dss2|out\(1));
+
+-- Location: LCCOMB_X29_Y27_N28
+\dss2|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr4~0_combout\ = (\timeCount|c2\(2) & (\timeCount|c2\(3))) # (!\timeCount|c2\(2) & (\timeCount|c2\(1) & ((\timeCount|c2\(3)) # (!\timeCount|c2\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101010001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X29_Y27_N4
+\dss2|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(2) = (\button2~input_o\ & ((\dss2|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss2|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(2),
+	datad => \dss2|WideOr4~0_combout\,
+	combout => \dss2|out\(2));
+
+-- Location: LCCOMB_X29_Y27_N6
+\dss2|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr3~0_combout\ = (!\timeCount|c2\(3) & ((\timeCount|c2\(1) & (\timeCount|c2\(0) & \timeCount|c2\(2))) # (!\timeCount|c2\(1) & (\timeCount|c2\(0) $ (\timeCount|c2\(2))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X29_Y27_N26
+\dss2|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(3) = (\button2~input_o\ & ((\dss2|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss2|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(3),
+	datad => \dss2|WideOr3~0_combout\,
+	combout => \dss2|out\(3));
+
+-- Location: LCCOMB_X28_Y27_N4
+\dss2|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr2~0_combout\ = (\timeCount|c2\(1) & (\timeCount|c2\(0) & (!\timeCount|c2\(3)))) # (!\timeCount|c2\(1) & ((\timeCount|c2\(2) & ((!\timeCount|c2\(3)))) # (!\timeCount|c2\(2) & (\timeCount|c2\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110101001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N2
+\dss2|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(4) = (\button2~input_o\ & (\dss2|WideOr2~0_combout\)) # (!\button2~input_o\ & ((\dss2|out\(4))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss2|WideOr2~0_combout\,
+	datad => \dss2|out\(4),
+	combout => \dss2|out\(4));
+
+-- Location: LCCOMB_X28_Y27_N30
+\dss2|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr1~0_combout\ = (!\timeCount|c2\(3) & ((\timeCount|c2\(1) & ((\timeCount|c2\(0)) # (!\timeCount|c2\(2)))) # (!\timeCount|c2\(1) & (\timeCount|c2\(0) & !\timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100000001110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N24
+\dss2|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(5) = (\button2~input_o\ & (\dss2|WideOr1~0_combout\)) # (!\button2~input_o\ & ((\dss2|out\(5))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss2|WideOr1~0_combout\,
+	datad => \dss2|out\(5),
+	combout => \dss2|out\(5));
+
+-- Location: LCCOMB_X28_Y27_N8
+\dss2|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr0~0_combout\ = (\timeCount|c2\(3)) # ((\timeCount|c2\(1) & ((!\timeCount|c2\(2)) # (!\timeCount|c2\(0)))) # (!\timeCount|c2\(1) & ((\timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011111111010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N10
+\dss2|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(6) = (\button2~input_o\ & (!\dss2|WideOr0~0_combout\)) # (!\button2~input_o\ & ((\dss2|out\(6))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011111100001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss2|WideOr0~0_combout\,
+	datad => \dss2|out\(6),
+	combout => \dss2|out\(6));
+
+-- Location: LCCOMB_X26_Y28_N8
+\timeCount|Add0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add0~0_combout\ = \timeCount|c3\(2) $ (((\timeCount|c3\(1) & \timeCount|c3\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(2),
+	combout => \timeCount|Add0~0_combout\);
+
+-- Location: LCCOMB_X26_Y28_N6
+\timeCount|c3~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~4_combout\ = (!\timeCount|always0~0_combout\ & (\timeCount|Add0~0_combout\ & \timeCount|c3[1]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datac => \timeCount|Add0~0_combout\,
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~4_combout\);
+
+-- Location: LCCOMB_X27_Y28_N28
+\timeCount|c3[1]~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3[1]~2_combout\ = (\timeCount|always0~0_combout\) # ((\timeCount|c2[0]~1_combout\ & (\timeCount|c2[0]~0_combout\ & \timeCount|c2[0]~2_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datab => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|c2[0]~0_combout\,
+	datad => \timeCount|c2[0]~2_combout\,
+	combout => \timeCount|c3[1]~2_combout\);
+
+-- Location: FF_X27_Y28_N17
+\timeCount|c3[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	asdata => \timeCount|c3~4_combout\,
+	sload => VCC,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(2));
+
+-- Location: LCCOMB_X26_Y28_N10
+\timeCount|c3[1]~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3[1]~0_combout\ = (\timeCount|c3\(1)) # ((\timeCount|c3\(2)) # ((!\timeCount|c3\(3)) # (!\timeCount|c3\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110111111111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(3),
+	combout => \timeCount|c3[1]~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N0
+\timeCount|c3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~1_combout\ = (!\timeCount|always0~0_combout\ & (!\timeCount|c3\(0) & \timeCount|c3[1]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~1_combout\);
+
+-- Location: FF_X27_Y28_N1
+\timeCount|c3[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c3~1_combout\,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(0));
+
+-- Location: LCCOMB_X27_Y28_N30
+\timeCount|c3~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~3_combout\ = (!\timeCount|always0~0_combout\ & (\timeCount|c3[1]~0_combout\ & (\timeCount|c3\(0) $ (\timeCount|c3\(1)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001010000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(1),
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~3_combout\);
+
+-- Location: FF_X27_Y28_N31
+\timeCount|c3[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c3~3_combout\,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(1));
+
+-- Location: LCCOMB_X26_Y28_N24
+\timeCount|Add0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add0~1_combout\ = \timeCount|c3\(3) $ (((\timeCount|c3\(1) & (\timeCount|c3\(2) & \timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111111110000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(3),
+	combout => \timeCount|Add0~1_combout\);
+
+-- Location: LCCOMB_X27_Y28_N26
+\timeCount|c3~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~5_combout\ = (\timeCount|Add0~1_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|c3[1]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|Add0~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~5_combout\);
+
+-- Location: FF_X27_Y28_N27
+\timeCount|c3[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c3~5_combout\,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(3));
+
+-- Location: LCCOMB_X27_Y28_N24
+\dss3|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out~0_combout\ = (!\timeCount|c3\(3) & (!\timeCount|c3\(1) & (\timeCount|c3\(2) $ (\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(3),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(1),
+	datad => \timeCount|c3\(0),
+	combout => \dss3|out~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N10
+\dss3|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(0) = (\button2~input_o\ & (\dss3|out~0_combout\)) # (!\button2~input_o\ & ((\dss3|out\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100111111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out~0_combout\,
+	datac => \button2~input_o\,
+	datad => \dss3|out\(0),
+	combout => \dss3|out\(0));
+
+-- Location: LCCOMB_X27_Y28_N2
+\dss3|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out~1_combout\ = (\timeCount|c3\(2) & (!\timeCount|c3\(3) & (\timeCount|c3\(1) $ (\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010000001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(0),
+	combout => \dss3|out~1_combout\);
+
+-- Location: LCCOMB_X27_Y28_N16
+\dss3|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(1) = (\button2~input_o\ & ((\dss3|out~1_combout\))) # (!\button2~input_o\ & (\dss3|out\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110010101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss3|out\(1),
+	datab => \dss3|out~1_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(1));
+
+-- Location: LCCOMB_X26_Y28_N12
+\dss3|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr4~0_combout\ = (\timeCount|c3\(2) & (((\timeCount|c3\(3))))) # (!\timeCount|c3\(2) & (\timeCount|c3\(1) & ((\timeCount|c3\(3)) # (!\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110010001010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(3),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X26_Y28_N18
+\dss3|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(2) = (\button2~input_o\ & ((\dss3|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out\(2),
+	datac => \button2~input_o\,
+	datad => \dss3|WideOr4~0_combout\,
+	combout => \dss3|out\(2));
+
+-- Location: LCCOMB_X27_Y28_N8
+\dss3|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr3~0_combout\ = (!\timeCount|c3\(3) & ((\timeCount|c3\(1) & (\timeCount|c3\(0) & \timeCount|c3\(2))) # (!\timeCount|c3\(1) & (\timeCount|c3\(0) $ (\timeCount|c3\(2))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100100000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N20
+\dss3|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(3) = (\button2~input_o\ & ((\dss3|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out\(3),
+	datac => \dss3|WideOr3~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(3));
+
+-- Location: LCCOMB_X27_Y28_N22
+\dss3|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr2~0_combout\ = (\timeCount|c3\(1) & (\timeCount|c3\(0) & (!\timeCount|c3\(3)))) # (!\timeCount|c3\(1) & ((\timeCount|c3\(2) & ((!\timeCount|c3\(3)))) # (!\timeCount|c3\(2) & (\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110101001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N18
+\dss3|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(4) = (\button2~input_o\ & ((\dss3|WideOr2~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(4)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out\(4),
+	datac => \dss3|WideOr2~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(4));
+
+-- Location: LCCOMB_X27_Y28_N4
+\dss3|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr1~0_combout\ = (!\timeCount|c3\(3) & ((\timeCount|c3\(1) & ((\timeCount|c3\(0)) # (!\timeCount|c3\(2)))) # (!\timeCount|c3\(1) & (\timeCount|c3\(0) & !\timeCount|c3\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100000001110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N12
+\dss3|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(5) = (\button2~input_o\ & ((\dss3|WideOr1~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000010101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss3|out\(5),
+	datac => \dss3|WideOr1~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(5));
+
+-- Location: LCCOMB_X27_Y28_N14
+\dss3|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr0~0_combout\ = (\timeCount|c3\(3)) # ((\timeCount|c3\(1) & ((!\timeCount|c3\(0)) # (!\timeCount|c3\(2)))) # (!\timeCount|c3\(1) & (\timeCount|c3\(2))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(0),
+	combout => \dss3|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N6
+\dss3|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(6) = (\button2~input_o\ & ((!\dss3|WideOr0~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(6)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111110101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss3|out\(6),
+	datac => \dss3|WideOr0~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(6));
+
+ww_hex0(0) <= \hex0[0]~output_o\;
+
+ww_hex0(1) <= \hex0[1]~output_o\;
+
+ww_hex0(2) <= \hex0[2]~output_o\;
+
+ww_hex0(3) <= \hex0[3]~output_o\;
+
+ww_hex0(4) <= \hex0[4]~output_o\;
+
+ww_hex0(5) <= \hex0[5]~output_o\;
+
+ww_hex0(6) <= \hex0[6]~output_o\;
+
+ww_hex1(0) <= \hex1[0]~output_o\;
+
+ww_hex1(1) <= \hex1[1]~output_o\;
+
+ww_hex1(2) <= \hex1[2]~output_o\;
+
+ww_hex1(3) <= \hex1[3]~output_o\;
+
+ww_hex1(4) <= \hex1[4]~output_o\;
+
+ww_hex1(5) <= \hex1[5]~output_o\;
+
+ww_hex1(6) <= \hex1[6]~output_o\;
+
+ww_hex2(0) <= \hex2[0]~output_o\;
+
+ww_hex2(1) <= \hex2[1]~output_o\;
+
+ww_hex2(2) <= \hex2[2]~output_o\;
+
+ww_hex2(3) <= \hex2[3]~output_o\;
+
+ww_hex2(4) <= \hex2[4]~output_o\;
+
+ww_hex2(5) <= \hex2[5]~output_o\;
+
+ww_hex2(6) <= \hex2[6]~output_o\;
+
+ww_hex3(0) <= \hex3[0]~output_o\;
+
+ww_hex3(1) <= \hex3[1]~output_o\;
+
+ww_hex3(2) <= \hex3[2]~output_o\;
+
+ww_hex3(3) <= \hex3[3]~output_o\;
+
+ww_hex3(4) <= \hex3[4]~output_o\;
+
+ww_hex3(5) <= \hex3[5]~output_o\;
+
+ww_hex3(6) <= \hex3[6]~output_o\;
+
+ww_decimal_point <= \decimal_point~output_o\;
+END structure;
+
+
diff --git a/stopClockVerilog/simulation/modelsim/stopclock_6_1200mv_85c_vhd_slow.sdo b/stopClockVerilog/simulation/modelsim/stopclock_6_1200mv_85c_vhd_slow.sdo
new file mode 100644
index 0000000..17a6f79
--- /dev/null
+++ b/stopClockVerilog/simulation/modelsim/stopclock_6_1200mv_85c_vhd_slow.sdo
@@ -0,0 +1,2657 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16U484C6 Package UFBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16U484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "stopclock")
+  (DATE "03/02/2016 15:24:50")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (936:936:936) (922:922:922))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1016:1016:1016) (985:985:985))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (507:507:507) (491:491:491))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (486:486:486) (472:472:472))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (705:705:705) (690:690:690))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (484:484:484) (472:472:472))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (697:697:697) (680:680:680))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (780:780:780) (774:774:774))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (813:813:813) (804:804:804))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (792:792:792) (785:785:785))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (786:786:786) (767:767:767))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1039:1039:1039) (1026:1026:1026))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (766:766:766) (750:750:750))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (740:740:740) (729:729:729))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (736:736:736) (717:717:717))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (655:655:655) (677:677:677))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (507:507:507) (501:501:501))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (755:755:755) (742:742:742))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (727:727:727) (713:713:713))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (772:772:772) (758:758:758))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1128:1128:1128) (1089:1089:1089))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (898:898:898) (861:861:861))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1275:1275:1275) (1223:1223:1223))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (876:876:876) (841:841:841))
+        (IOPATH i o (2080:2080:2080) (2029:2029:2029))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (935:935:935) (901:901:901))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1103:1103:1103) (1056:1056:1056))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1103:1103:1103) (1053:1053:1053))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1100:1100:1100) (1050:1050:1050))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\button2\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\clk\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (745:745:745) (906:906:906))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\clk\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (163:163:163) (145:145:145))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\button1\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|start\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3396:3396:3396) (3721:3721:3721))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|start\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1847:1847:1847) (1883:1883:1883))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[0\]\~18\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (251:251:251) (336:336:336))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1847:1847:1847) (1882:1882:1882))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1159:1159:1159) (1150:1150:1150))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[1\]\~20\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (250:250:250) (336:336:336))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1847:1847:1847) (1882:1882:1882))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1159:1159:1159) (1150:1150:1150))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[2\]\~22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (251:251:251) (337:337:337))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1186:1186:1186) (1183:1183:1183))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[3\]\~24\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (263:263:263) (346:346:346))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1186:1186:1186) (1183:1183:1183))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[4\]\~26\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (341:341:341))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1186:1186:1186) (1183:1183:1183))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[5\]\~28\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (408:408:408) (479:479:479))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1186:1186:1186) (1183:1183:1183))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[6\]\~30\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (341:341:341))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1186:1186:1186) (1183:1183:1183))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[7\]\~32\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (250:250:250) (334:334:334))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[7\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1847:1847:1847) (1882:1882:1882))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1159:1159:1159) (1150:1150:1150))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[8\]\~34\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (341:341:341))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[8\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1186:1186:1186) (1183:1183:1183))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[9\]\~36\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (261:261:261) (343:343:343))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[9\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[10\]\~38\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (262:262:262) (344:344:344))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[10\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[11\]\~40\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (262:262:262) (344:344:344))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[11\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[12\]\~42\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (343:343:343))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[12\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[13\]\~44\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (251:251:251) (336:336:336))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[13\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[14\]\~46\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (254:254:254) (345:345:345))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[14\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[15\]\~48\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (343:343:343))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[15\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[16\]\~50\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (252:252:252) (338:338:338))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[16\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[17\]\~52\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (227:227:227) (299:299:299))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[17\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (254:254:254) (346:346:346))
+        (PORT datab (251:251:251) (337:337:337))
+        (PORT datac (224:224:224) (305:305:305))
+        (PORT datad (226:226:226) (300:300:300))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (345:345:345))
+        (PORT datac (224:224:224) (305:305:305))
+        (PORT datad (239:239:239) (308:308:308))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (344:344:344))
+        (PORT datab (407:407:407) (476:476:476))
+        (PORT datac (561:561:561) (606:606:606))
+        (PORT datad (556:556:556) (603:603:603))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (409:409:409) (481:481:481))
+        (PORT datab (252:252:252) (338:338:338))
+        (PORT datac (224:224:224) (305:305:305))
+        (PORT datad (226:226:226) (299:299:299))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (201:201:201) (245:245:245))
+        (PORT datab (253:253:253) (339:339:339))
+        (PORT datac (172:172:172) (204:204:204))
+        (PORT datad (173:173:173) (199:199:199))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (254:254:254) (345:345:345))
+        (PORT datab (252:252:252) (337:337:337))
+        (PORT datac (314:314:314) (342:342:342))
+        (PORT datad (555:555:555) (567:567:567))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|clock_out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (245:245:245) (332:332:332))
+        (PORT datab (3396:3396:3396) (3721:3721:3721))
+        (PORT datac (1928:1928:1928) (2034:2034:2034))
+        (PORT datad (202:202:202) (229:229:229))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|clock_out\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (173:173:173) (199:199:199))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|clock_out\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1847:1847:1847) (1883:1883:1883))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\clockConv\|clock_out\~clkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (780:780:780) (826:826:826))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\button0\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|en\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT asdata (955:955:955) (962:962:962))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|always0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3629:3629:3629) (3929:3929:3929))
+        (PORT datac (226:226:226) (306:306:306))
+        (PORT datad (3427:3427:3427) (3742:3742:3742))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (248:248:248) (290:290:290))
+        (PORT datad (631:631:631) (639:639:639))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (424:424:424) (506:506:506))
+        (PORT datab (668:668:668) (678:678:678))
+        (PORT datad (224:224:224) (253:253:253))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (309:309:309) (420:420:420))
+        (PORT datab (316:316:316) (407:407:407))
+        (PORT datac (276:276:276) (364:364:364))
+        (PORT datad (297:297:297) (380:380:380))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (342:342:342) (318:318:318))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (421:421:421) (496:496:496))
+        (PORT datac (387:387:387) (448:448:448))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (430:430:430) (457:457:457))
+        (PORT datab (664:664:664) (676:676:676))
+        (PORT datad (348:348:348) (370:370:370))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\[3\]\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3473:3473:3473) (3794:3794:3794))
+        (PORT datab (3629:3629:3629) (3929:3929:3929))
+        (PORT datac (223:223:223) (303:303:303))
+        (PORT datad (633:633:633) (641:641:641))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (446:446:446) (518:518:518))
+        (PORT datab (387:387:387) (413:413:413))
+        (PORT datad (589:589:589) (593:593:593))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (454:454:454) (514:514:514))
+        (PORT datab (412:412:412) (477:477:477))
+        (PORT datac (389:389:389) (459:459:459))
+        (PORT datad (414:414:414) (467:467:467))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (220:220:220) (258:258:258))
+        (PORT datac (1696:1696:1696) (1753:1753:1753))
+        (PORT datad (174:174:174) (198:198:198))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (314:314:314) (427:427:427))
+        (PORT datab (317:317:317) (412:412:412))
+        (PORT datac (277:277:277) (368:368:368))
+        (PORT datad (294:294:294) (377:377:377))
+        (IOPATH dataa combout (303:303:303) (299:299:299))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (199:199:199) (237:237:237))
+        (PORT datac (192:192:192) (225:225:225))
+        (PORT datad (1752:1752:1752) (1818:1818:1818))
+        (IOPATH datab combout (306:306:306) (311:311:311))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (313:313:313) (425:425:425))
+        (PORT datab (305:305:305) (402:402:402))
+        (PORT datac (411:411:411) (469:469:469))
+        (PORT datad (294:294:294) (376:376:376))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (260:260:260))
+        (PORT datac (172:172:172) (206:206:206))
+        (PORT datad (1748:1748:1748) (1816:1816:1816))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (311:311:311) (422:422:422))
+        (PORT datab (303:303:303) (399:399:399))
+        (PORT datac (412:412:412) (473:473:473))
+        (PORT datad (287:287:287) (368:368:368))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (260:260:260))
+        (PORT datac (173:173:173) (206:206:206))
+        (PORT datad (1748:1748:1748) (1817:1817:1817))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (311:311:311) (423:423:423))
+        (PORT datab (315:315:315) (411:411:411))
+        (PORT datac (276:276:276) (368:368:368))
+        (PORT datad (296:296:296) (379:379:379))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (219:219:219) (258:258:258))
+        (PORT datac (1684:1684:1684) (1752:1752:1752))
+        (PORT datad (175:175:175) (201:201:201))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (310:310:310) (423:423:423))
+        (PORT datab (322:322:322) (418:418:418))
+        (PORT datac (411:411:411) (469:469:469))
+        (PORT datad (395:395:395) (461:461:461))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (267:267:267))
+        (PORT datac (1696:1696:1696) (1755:1755:1755))
+        (PORT datad (327:327:327) (344:344:344))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (314:314:314) (426:426:426))
+        (PORT datab (318:318:318) (412:412:412))
+        (PORT datac (277:277:277) (369:369:369))
+        (PORT datad (293:293:293) (371:371:371))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (265:265:265))
+        (PORT datac (171:171:171) (204:204:204))
+        (PORT datad (1751:1751:1751) (1816:1816:1816))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (394:394:394) (433:433:433))
+        (PORT datab (457:457:457) (493:493:493))
+        (PORT datad (658:658:658) (712:712:712))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1036:1036:1036) (987:987:987))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (471:471:471) (540:540:540))
+        (PORT datab (474:474:474) (550:550:550))
+        (PORT datac (642:642:642) (693:693:693))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (399:399:399) (436:436:436))
+        (PORT datac (419:419:419) (454:454:454))
+        (PORT datad (311:311:311) (326:326:326))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1036:1036:1036) (987:987:987))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add2\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (720:720:720) (788:788:788))
+        (PORT datab (467:467:467) (533:533:533))
+        (PORT datac (642:642:642) (692:692:692))
+        (PORT datad (429:429:429) (492:492:492))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (395:395:395) (432:432:432))
+        (PORT datac (423:423:423) (460:460:460))
+        (PORT datad (330:330:330) (347:347:347))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1036:1036:1036) (987:987:987))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (335:335:335) (441:441:441))
+        (PORT datab (317:317:317) (418:418:418))
+        (PORT datac (287:287:287) (383:383:383))
+        (PORT datad (269:269:269) (349:349:349))
+        (IOPATH dataa combout (301:301:301) (299:299:299))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (399:399:399) (436:436:436))
+        (PORT datab (452:452:452) (486:486:486))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1036:1036:1036) (987:987:987))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (476:476:476) (548:548:548))
+        (PORT datab (311:311:311) (409:409:409))
+        (PORT datac (303:303:303) (398:398:398))
+        (PORT datad (404:404:404) (463:463:463))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1530:1530:1530) (1619:1619:1619))
+        (PORT datac (326:326:326) (348:348:348))
+        (PORT datad (173:173:173) (198:198:198))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (316:316:316) (416:416:416))
+        (PORT datab (316:316:316) (416:416:416))
+        (PORT datac (298:298:298) (393:393:393))
+        (PORT datad (269:269:269) (349:349:349))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (342:342:342) (318:318:318))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1531:1531:1531) (1620:1620:1620))
+        (PORT datac (170:170:170) (203:203:203))
+        (PORT datad (194:194:194) (219:219:219))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (469:469:469) (541:541:541))
+        (PORT datab (457:457:457) (521:521:521))
+        (PORT datac (441:441:441) (516:516:516))
+        (PORT datad (428:428:428) (491:491:491))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1530:1530:1530) (1610:1610:1610))
+        (PORT datac (192:192:192) (225:225:225))
+        (PORT datad (172:172:172) (197:197:197))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (317:317:317) (420:420:420))
+        (PORT datab (313:313:313) (411:411:411))
+        (PORT datac (301:301:301) (397:397:397))
+        (PORT datad (268:268:268) (347:347:347))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1530:1530:1530) (1610:1610:1610))
+        (PORT datac (193:193:193) (226:226:226))
+        (PORT datad (314:314:314) (332:332:332))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (475:475:475) (548:548:548))
+        (PORT datab (311:311:311) (410:410:410))
+        (PORT datac (303:303:303) (399:399:399))
+        (PORT datad (404:404:404) (463:463:463))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1534:1534:1534) (1624:1624:1624))
+        (PORT datac (327:327:327) (349:349:349))
+        (PORT datad (173:173:173) (198:198:198))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (316:316:316) (418:418:418))
+        (PORT datab (311:311:311) (410:410:410))
+        (PORT datac (303:303:303) (398:398:398))
+        (PORT datad (263:263:263) (342:342:342))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1531:1531:1531) (1619:1619:1619))
+        (PORT datac (172:172:172) (205:205:205))
+        (PORT datad (195:195:195) (220:220:220))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (317:317:317) (421:421:421))
+        (PORT datab (313:313:313) (414:414:414))
+        (PORT datac (302:302:302) (399:399:399))
+        (PORT datad (266:266:266) (345:345:345))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1531:1531:1531) (1624:1624:1624))
+        (PORT datac (172:172:172) (206:206:206))
+        (PORT datad (195:195:195) (221:221:221))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (249:249:249) (306:306:306))
+        (PORT datad (241:241:241) (278:278:278))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (399:399:399) (426:426:426))
+        (PORT datac (612:612:612) (621:621:621))
+        (PORT datad (635:635:635) (643:643:643))
+        (IOPATH datab combout (304:304:304) (311:311:311))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (790:790:790) (783:783:783))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (247:247:247) (303:303:303))
+        (PORT datab (314:314:314) (414:414:414))
+        (PORT datad (237:237:237) (273:273:273))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (790:790:790) (783:783:783))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (309:309:309) (419:419:419))
+        (PORT datab (316:316:316) (412:412:412))
+        (PORT datad (273:273:273) (352:352:352))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (250:250:250) (308:308:308))
+        (PORT datac (565:565:565) (578:578:578))
+        (PORT datad (243:243:243) (279:279:279))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (790:790:790) (783:783:783))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (306:306:306) (416:416:416))
+        (PORT datab (316:316:316) (418:418:418))
+        (PORT datac (269:269:269) (358:358:358))
+        (PORT datad (276:276:276) (358:358:358))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (342:342:342) (318:318:318))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add1\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (309:309:309) (419:419:419))
+        (PORT datab (317:317:317) (418:418:418))
+        (PORT datac (270:270:270) (359:359:359))
+        (PORT datad (275:275:275) (357:357:357))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~7\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (249:249:249) (306:306:306))
+        (PORT datab (266:266:266) (314:314:314))
+        (PORT datac (316:316:316) (336:336:336))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (790:790:790) (783:783:783))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (435:435:435) (511:511:511))
+        (PORT datab (434:434:434) (501:501:501))
+        (PORT datac (405:405:405) (467:467:467))
+        (PORT datad (417:417:417) (479:479:479))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1529:1529:1529) (1605:1605:1605))
+        (PORT datac (193:193:193) (226:226:226))
+        (PORT datad (175:175:175) (200:200:200))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (431:431:431) (515:515:515))
+        (PORT datab (433:433:433) (504:504:504))
+        (PORT datac (404:404:404) (469:469:469))
+        (PORT datad (419:419:419) (482:482:482))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (304:304:304) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1531:1531:1531) (1606:1606:1606))
+        (PORT datac (192:192:192) (225:225:225))
+        (PORT datad (173:173:173) (199:199:199))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (432:432:432) (515:515:515))
+        (PORT datab (434:434:434) (504:504:504))
+        (PORT datac (405:405:405) (468:468:468))
+        (PORT datad (418:418:418) (478:478:478))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1529:1529:1529) (1606:1606:1606))
+        (PORT datac (192:192:192) (225:225:225))
+        (PORT datad (174:174:174) (201:201:201))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (432:432:432) (510:510:510))
+        (PORT datab (429:429:429) (498:498:498))
+        (PORT datac (404:404:404) (467:467:467))
+        (PORT datad (422:422:422) (480:480:480))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1530:1530:1530) (1606:1606:1606))
+        (PORT datac (192:192:192) (225:225:225))
+        (PORT datad (175:175:175) (201:201:201))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (301:301:301) (409:409:409))
+        (PORT datab (311:311:311) (410:410:410))
+        (PORT datac (265:265:265) (352:352:352))
+        (PORT datad (271:271:271) (353:353:353))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1474:1474:1474) (1564:1564:1564))
+        (PORT datac (171:171:171) (203:203:203))
+        (PORT datad (194:194:194) (219:219:219))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (308:308:308) (418:418:418))
+        (PORT datab (315:315:315) (410:410:410))
+        (PORT datac (268:268:268) (357:357:357))
+        (PORT datad (273:273:273) (351:351:351))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1471:1471:1471) (1560:1560:1560))
+        (PORT datac (171:171:171) (204:204:204))
+        (PORT datad (195:195:195) (220:220:220))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (302:302:302) (410:410:410))
+        (PORT datab (311:311:311) (410:410:410))
+        (PORT datac (266:266:266) (352:352:352))
+        (PORT datad (272:272:272) (353:353:353))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1471:1471:1471) (1565:1565:1565))
+        (PORT datac (172:172:172) (206:206:206))
+        (PORT datad (196:196:196) (221:221:221))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (485:485:485) (558:558:558))
+        (PORT datac (432:432:432) (504:504:504))
+        (PORT datad (405:405:405) (472:472:472))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (670:670:670) (683:683:683))
+        (PORT datac (172:172:172) (205:205:205))
+        (PORT datad (196:196:196) (220:220:220))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\[1\]\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (654:654:654) (682:682:682))
+        (PORT datab (605:605:605) (623:623:623))
+        (PORT datac (394:394:394) (421:421:421))
+        (PORT datad (566:566:566) (571:571:571))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT asdata (655:655:655) (670:670:670))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\[1\]\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (482:482:482) (562:562:562))
+        (PORT datab (432:432:432) (515:515:515))
+        (PORT datac (432:432:432) (505:505:505))
+        (PORT datad (419:419:419) (489:489:489))
+        (IOPATH dataa combout (304:304:304) (299:299:299))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (661:661:661) (690:690:690))
+        (PORT datad (365:365:365) (382:382:382))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (656:656:656) (683:683:683))
+        (PORT datab (318:318:318) (418:418:418))
+        (PORT datad (366:366:366) (387:387:387))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (304:304:304) (308:308:308))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (479:479:479) (556:556:556))
+        (PORT datab (432:432:432) (509:509:509))
+        (PORT datac (435:435:435) (508:508:508))
+        (PORT datad (417:417:417) (485:485:485))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (333:333:333) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (369:369:369) (390:390:390))
+        (PORT datac (623:623:623) (644:644:644))
+        (PORT datad (365:365:365) (387:387:387))
+        (IOPATH datab combout (304:304:304) (311:311:311))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (303:303:303) (404:404:404))
+        (PORT datab (300:300:300) (395:395:395))
+        (PORT datac (270:270:270) (367:367:367))
+        (PORT datad (287:287:287) (374:374:374))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (200:200:200) (240:240:240))
+        (PORT datac (1691:1691:1691) (1757:1757:1757))
+        (PORT datad (196:196:196) (221:221:221))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (309:309:309) (416:416:416))
+        (PORT datab (304:304:304) (401:401:401))
+        (PORT datac (278:278:278) (371:371:371))
+        (PORT datad (279:279:279) (365:365:365))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (615:615:615) (634:634:634))
+        (PORT datab (200:200:200) (240:240:240))
+        (PORT datad (1710:1710:1710) (1789:1789:1789))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (306:306:306) (311:311:311))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (480:480:480) (559:559:559))
+        (PORT datab (454:454:454) (527:527:527))
+        (PORT datac (431:431:431) (504:504:504))
+        (PORT datad (403:403:403) (473:473:473))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (220:220:220) (260:260:260))
+        (PORT datac (1696:1696:1696) (1758:1758:1758))
+        (PORT datad (174:174:174) (200:200:200))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (305:305:305) (413:413:413))
+        (PORT datab (307:307:307) (406:406:406))
+        (PORT datac (274:274:274) (366:366:366))
+        (PORT datad (274:274:274) (355:355:355))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (260:260:260))
+        (PORT datac (173:173:173) (207:207:207))
+        (PORT datad (1711:1711:1711) (1791:1791:1791))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (302:302:302) (408:408:408))
+        (PORT datab (314:314:314) (414:414:414))
+        (PORT datac (271:271:271) (364:364:364))
+        (PORT datad (273:273:273) (355:355:355))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (220:220:220) (260:260:260))
+        (PORT datac (172:172:172) (205:205:205))
+        (PORT datad (1710:1710:1710) (1790:1790:1790))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (304:304:304) (415:415:415))
+        (PORT datab (307:307:307) (406:406:406))
+        (PORT datac (273:273:273) (366:366:366))
+        (PORT datad (273:273:273) (356:356:356))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (266:266:266))
+        (PORT datac (171:171:171) (205:205:205))
+        (PORT datad (1710:1710:1710) (1790:1790:1790))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (305:305:305) (414:414:414))
+        (PORT datab (302:302:302) (398:398:398))
+        (PORT datac (275:275:275) (367:367:367))
+        (PORT datad (283:283:283) (370:370:370))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (221:221:221) (264:264:264))
+        (PORT datac (172:172:172) (203:203:203))
+        (PORT datad (1710:1710:1710) (1786:1786:1786))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+)
diff --git a/stopClockVerilog/simulation/modelsim/stopclock_min_1200mv_0c_fast.vho b/stopClockVerilog/simulation/modelsim/stopclock_min_1200mv_0c_fast.vho
new file mode 100644
index 0000000..766487c
--- /dev/null
+++ b/stopClockVerilog/simulation/modelsim/stopclock_min_1200mv_0c_fast.vho
@@ -0,0 +1,3227 @@
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus II 64-Bit"
+-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+-- DATE "03/02/2016 15:24:50"
+
+-- 
+-- Device: Altera EP3C16U484C6 Package UFBGA484
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIII;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	stopclock IS
+    PORT (
+	clk : IN std_logic;
+	button0 : IN std_logic;
+	button1 : IN std_logic;
+	button2 : IN std_logic;
+	hex0 : BUFFER std_logic_vector(6 DOWNTO 0);
+	hex1 : BUFFER std_logic_vector(6 DOWNTO 0);
+	hex2 : BUFFER std_logic_vector(6 DOWNTO 0);
+	hex3 : BUFFER std_logic_vector(6 DOWNTO 0);
+	decimal_point : BUFFER std_logic
+	);
+END stopclock;
+
+-- Design Ports Information
+-- hex0[0]	=>  Location: PIN_E11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[1]	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[2]	=>  Location: PIN_H12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[3]	=>  Location: PIN_H13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[4]	=>  Location: PIN_G12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[5]	=>  Location: PIN_F12,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex0[6]	=>  Location: PIN_F13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[0]	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[1]	=>  Location: PIN_B13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[2]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[3]	=>  Location: PIN_A14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[4]	=>  Location: PIN_B14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[5]	=>  Location: PIN_E14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex1[6]	=>  Location: PIN_A15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[0]	=>  Location: PIN_D15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[1]	=>  Location: PIN_A16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[2]	=>  Location: PIN_B16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[3]	=>  Location: PIN_E15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[4]	=>  Location: PIN_A17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[5]	=>  Location: PIN_B17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex2[6]	=>  Location: PIN_F14,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[0]	=>  Location: PIN_B18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[1]	=>  Location: PIN_F15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[2]	=>  Location: PIN_A19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[3]	=>  Location: PIN_B19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[4]	=>  Location: PIN_C19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[5]	=>  Location: PIN_D19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- hex3[6]	=>  Location: PIN_G15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- decimal_point	=>  Location: PIN_A18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- button2	=>  Location: PIN_F1,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- button0	=>  Location: PIN_H2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- button1	=>  Location: PIN_G3,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- clk	=>  Location: PIN_G21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF stopclock IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_clk : std_logic;
+SIGNAL ww_button0 : std_logic;
+SIGNAL ww_button1 : std_logic;
+SIGNAL ww_button2 : std_logic;
+SIGNAL ww_hex0 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_hex1 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_hex2 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_hex3 : std_logic_vector(6 DOWNTO 0);
+SIGNAL ww_decimal_point : std_logic;
+SIGNAL \clockConv|clock_out~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \hex0[0]~output_o\ : std_logic;
+SIGNAL \hex0[1]~output_o\ : std_logic;
+SIGNAL \hex0[2]~output_o\ : std_logic;
+SIGNAL \hex0[3]~output_o\ : std_logic;
+SIGNAL \hex0[4]~output_o\ : std_logic;
+SIGNAL \hex0[5]~output_o\ : std_logic;
+SIGNAL \hex0[6]~output_o\ : std_logic;
+SIGNAL \hex1[0]~output_o\ : std_logic;
+SIGNAL \hex1[1]~output_o\ : std_logic;
+SIGNAL \hex1[2]~output_o\ : std_logic;
+SIGNAL \hex1[3]~output_o\ : std_logic;
+SIGNAL \hex1[4]~output_o\ : std_logic;
+SIGNAL \hex1[5]~output_o\ : std_logic;
+SIGNAL \hex1[6]~output_o\ : std_logic;
+SIGNAL \hex2[0]~output_o\ : std_logic;
+SIGNAL \hex2[1]~output_o\ : std_logic;
+SIGNAL \hex2[2]~output_o\ : std_logic;
+SIGNAL \hex2[3]~output_o\ : std_logic;
+SIGNAL \hex2[4]~output_o\ : std_logic;
+SIGNAL \hex2[5]~output_o\ : std_logic;
+SIGNAL \hex2[6]~output_o\ : std_logic;
+SIGNAL \hex3[0]~output_o\ : std_logic;
+SIGNAL \hex3[1]~output_o\ : std_logic;
+SIGNAL \hex3[2]~output_o\ : std_logic;
+SIGNAL \hex3[3]~output_o\ : std_logic;
+SIGNAL \hex3[4]~output_o\ : std_logic;
+SIGNAL \hex3[5]~output_o\ : std_logic;
+SIGNAL \hex3[6]~output_o\ : std_logic;
+SIGNAL \decimal_point~output_o\ : std_logic;
+SIGNAL \button2~input_o\ : std_logic;
+SIGNAL \clk~input_o\ : std_logic;
+SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
+SIGNAL \button1~input_o\ : std_logic;
+SIGNAL \clockConv|start~0_combout\ : std_logic;
+SIGNAL \clockConv|start~q\ : std_logic;
+SIGNAL \clockConv|ctr[0]~18_combout\ : std_logic;
+SIGNAL \clockConv|ctr[0]~19\ : std_logic;
+SIGNAL \clockConv|ctr[1]~20_combout\ : std_logic;
+SIGNAL \clockConv|ctr[1]~21\ : std_logic;
+SIGNAL \clockConv|ctr[2]~22_combout\ : std_logic;
+SIGNAL \clockConv|ctr[2]~23\ : std_logic;
+SIGNAL \clockConv|ctr[3]~24_combout\ : std_logic;
+SIGNAL \clockConv|ctr[3]~25\ : std_logic;
+SIGNAL \clockConv|ctr[4]~26_combout\ : std_logic;
+SIGNAL \clockConv|ctr[4]~27\ : std_logic;
+SIGNAL \clockConv|ctr[5]~28_combout\ : std_logic;
+SIGNAL \clockConv|ctr[5]~29\ : std_logic;
+SIGNAL \clockConv|ctr[6]~30_combout\ : std_logic;
+SIGNAL \clockConv|ctr[6]~31\ : std_logic;
+SIGNAL \clockConv|ctr[7]~32_combout\ : std_logic;
+SIGNAL \clockConv|ctr[7]~33\ : std_logic;
+SIGNAL \clockConv|ctr[8]~34_combout\ : std_logic;
+SIGNAL \clockConv|ctr[8]~35\ : std_logic;
+SIGNAL \clockConv|ctr[9]~36_combout\ : std_logic;
+SIGNAL \clockConv|ctr[9]~37\ : std_logic;
+SIGNAL \clockConv|ctr[10]~38_combout\ : std_logic;
+SIGNAL \clockConv|ctr[10]~39\ : std_logic;
+SIGNAL \clockConv|ctr[11]~40_combout\ : std_logic;
+SIGNAL \clockConv|ctr[11]~41\ : std_logic;
+SIGNAL \clockConv|ctr[12]~42_combout\ : std_logic;
+SIGNAL \clockConv|ctr[12]~43\ : std_logic;
+SIGNAL \clockConv|ctr[13]~44_combout\ : std_logic;
+SIGNAL \clockConv|ctr[13]~45\ : std_logic;
+SIGNAL \clockConv|ctr[14]~46_combout\ : std_logic;
+SIGNAL \clockConv|ctr[14]~47\ : std_logic;
+SIGNAL \clockConv|ctr[15]~48_combout\ : std_logic;
+SIGNAL \clockConv|ctr[15]~49\ : std_logic;
+SIGNAL \clockConv|ctr[16]~50_combout\ : std_logic;
+SIGNAL \clockConv|ctr[16]~51\ : std_logic;
+SIGNAL \clockConv|ctr[17]~52_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~0_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~3_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~1_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~2_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~4_combout\ : std_logic;
+SIGNAL \clockConv|LessThan0~5_combout\ : std_logic;
+SIGNAL \clockConv|clock_out~0_combout\ : std_logic;
+SIGNAL \clockConv|clock_out~feeder_combout\ : std_logic;
+SIGNAL \clockConv|clock_out~q\ : std_logic;
+SIGNAL \clockConv|clock_out~clkctrl_outclk\ : std_logic;
+SIGNAL \button0~input_o\ : std_logic;
+SIGNAL \timeCount|en~q\ : std_logic;
+SIGNAL \timeCount|always0~0_combout\ : std_logic;
+SIGNAL \timeCount|c0~0_combout\ : std_logic;
+SIGNAL \timeCount|c0~1_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~0_combout\ : std_logic;
+SIGNAL \timeCount|Add3~0_combout\ : std_logic;
+SIGNAL \timeCount|c0~2_combout\ : std_logic;
+SIGNAL \timeCount|c0[3]~3_combout\ : std_logic;
+SIGNAL \timeCount|c0~4_combout\ : std_logic;
+SIGNAL \dss0|out~0_combout\ : std_logic;
+SIGNAL \dss0|out~1_combout\ : std_logic;
+SIGNAL \dss0|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss0|WideOr0~0_combout\ : std_logic;
+SIGNAL \timeCount|c1~1_combout\ : std_logic;
+SIGNAL \timeCount|Add2~0_combout\ : std_logic;
+SIGNAL \timeCount|c1~2_combout\ : std_logic;
+SIGNAL \timeCount|Add2~1_combout\ : std_logic;
+SIGNAL \timeCount|c1~3_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~1_combout\ : std_logic;
+SIGNAL \timeCount|c1~0_combout\ : std_logic;
+SIGNAL \dss1|out~0_combout\ : std_logic;
+SIGNAL \dss1|out~1_combout\ : std_logic;
+SIGNAL \dss1|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss1|WideOr0~0_combout\ : std_logic;
+SIGNAL \timeCount|c2~3_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~4_combout\ : std_logic;
+SIGNAL \timeCount|c2~5_combout\ : std_logic;
+SIGNAL \timeCount|Add1~0_combout\ : std_logic;
+SIGNAL \timeCount|c2~6_combout\ : std_logic;
+SIGNAL \timeCount|c2[0]~2_combout\ : std_logic;
+SIGNAL \timeCount|Add1~1_combout\ : std_logic;
+SIGNAL \timeCount|c2~7_combout\ : std_logic;
+SIGNAL \dss2|out~0_combout\ : std_logic;
+SIGNAL \dss2|out~1_combout\ : std_logic;
+SIGNAL \dss2|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss2|WideOr0~0_combout\ : std_logic;
+SIGNAL \timeCount|Add0~0_combout\ : std_logic;
+SIGNAL \timeCount|c3~4_combout\ : std_logic;
+SIGNAL \timeCount|c3[1]~2_combout\ : std_logic;
+SIGNAL \timeCount|c3[1]~0_combout\ : std_logic;
+SIGNAL \timeCount|c3~1_combout\ : std_logic;
+SIGNAL \timeCount|c3~3_combout\ : std_logic;
+SIGNAL \timeCount|Add0~1_combout\ : std_logic;
+SIGNAL \timeCount|c3~5_combout\ : std_logic;
+SIGNAL \dss3|out~0_combout\ : std_logic;
+SIGNAL \dss3|out~1_combout\ : std_logic;
+SIGNAL \dss3|WideOr4~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr3~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr2~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr1~0_combout\ : std_logic;
+SIGNAL \dss3|WideOr0~0_combout\ : std_logic;
+SIGNAL \dss1|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \dss2|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \dss3|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \clockConv|ctr\ : std_logic_vector(17 DOWNTO 0);
+SIGNAL \timeCount|c3\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \timeCount|c2\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \timeCount|c1\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \timeCount|c0\ : std_logic_vector(3 DOWNTO 0);
+SIGNAL \dss0|out\ : std_logic_vector(6 DOWNTO 0);
+SIGNAL \timeCount|ALT_INV_c0[3]~3_combout\ : std_logic;
+SIGNAL \clockConv|ALT_INV_LessThan0~5_combout\ : std_logic;
+
+BEGIN
+
+ww_clk <= clk;
+ww_button0 <= button0;
+ww_button1 <= button1;
+ww_button2 <= button2;
+hex0 <= ww_hex0;
+hex1 <= ww_hex1;
+hex2 <= ww_hex2;
+hex3 <= ww_hex3;
+decimal_point <= ww_decimal_point;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\clockConv|clock_out~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clockConv|clock_out~q\);
+
+\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);
+\timeCount|ALT_INV_c0[3]~3_combout\ <= NOT \timeCount|c0[3]~3_combout\;
+\clockConv|ALT_INV_LessThan0~5_combout\ <= NOT \clockConv|LessThan0~5_combout\;
+
+-- Location: IOOBUF_X21_Y29_N23
+\hex0[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(0),
+	devoe => ww_devoe,
+	o => \hex0[0]~output_o\);
+
+-- Location: IOOBUF_X21_Y29_N30
+\hex0[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(1),
+	devoe => ww_devoe,
+	o => \hex0[1]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N2
+\hex0[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(2),
+	devoe => ww_devoe,
+	o => \hex0[2]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N30
+\hex0[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(3),
+	devoe => ww_devoe,
+	o => \hex0[3]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N9
+\hex0[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(4),
+	devoe => ww_devoe,
+	o => \hex0[4]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N23
+\hex0[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(5),
+	devoe => ww_devoe,
+	o => \hex0[5]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N16
+\hex0[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss0|out\(6),
+	devoe => ww_devoe,
+	o => \hex0[6]~output_o\);
+
+-- Location: IOOBUF_X21_Y29_N2
+\hex1[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(0),
+	devoe => ww_devoe,
+	o => \hex1[0]~output_o\);
+
+-- Location: IOOBUF_X21_Y29_N9
+\hex1[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(1),
+	devoe => ww_devoe,
+	o => \hex1[1]~output_o\);
+
+-- Location: IOOBUF_X23_Y29_N2
+\hex1[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(2),
+	devoe => ww_devoe,
+	o => \hex1[2]~output_o\);
+
+-- Location: IOOBUF_X23_Y29_N23
+\hex1[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(3),
+	devoe => ww_devoe,
+	o => \hex1[3]~output_o\);
+
+-- Location: IOOBUF_X23_Y29_N30
+\hex1[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(4),
+	devoe => ww_devoe,
+	o => \hex1[4]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N16
+\hex1[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(5),
+	devoe => ww_devoe,
+	o => \hex1[5]~output_o\);
+
+-- Location: IOOBUF_X26_Y29_N23
+\hex1[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss1|out\(6),
+	devoe => ww_devoe,
+	o => \hex1[6]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N30
+\hex2[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(0),
+	devoe => ww_devoe,
+	o => \hex2[0]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N30
+\hex2[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(1),
+	devoe => ww_devoe,
+	o => \hex2[1]~output_o\);
+
+-- Location: IOOBUF_X28_Y29_N2
+\hex2[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(2),
+	devoe => ww_devoe,
+	o => \hex2[2]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N2
+\hex2[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(3),
+	devoe => ww_devoe,
+	o => \hex2[3]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N16
+\hex2[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(4),
+	devoe => ww_devoe,
+	o => \hex2[4]~output_o\);
+
+-- Location: IOOBUF_X30_Y29_N23
+\hex2[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(5),
+	devoe => ww_devoe,
+	o => \hex2[5]~output_o\);
+
+-- Location: IOOBUF_X37_Y29_N2
+\hex2[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss2|out\(6),
+	devoe => ww_devoe,
+	o => \hex2[6]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N23
+\hex3[0]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(0),
+	devoe => ww_devoe,
+	o => \hex3[0]~output_o\);
+
+-- Location: IOOBUF_X39_Y29_N16
+\hex3[1]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(1),
+	devoe => ww_devoe,
+	o => \hex3[1]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N9
+\hex3[2]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(2),
+	devoe => ww_devoe,
+	o => \hex3[2]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N2
+\hex3[3]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(3),
+	devoe => ww_devoe,
+	o => \hex3[3]~output_o\);
+
+-- Location: IOOBUF_X37_Y29_N23
+\hex3[4]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(4),
+	devoe => ww_devoe,
+	o => \hex3[4]~output_o\);
+
+-- Location: IOOBUF_X37_Y29_N30
+\hex3[5]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(5),
+	devoe => ww_devoe,
+	o => \hex3[5]~output_o\);
+
+-- Location: IOOBUF_X39_Y29_N30
+\hex3[6]~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \dss3|out\(6),
+	devoe => ww_devoe,
+	o => \hex3[6]~output_o\);
+
+-- Location: IOOBUF_X32_Y29_N16
+\decimal_point~output\ : cycloneiii_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => GND,
+	devoe => ww_devoe,
+	o => \decimal_point~output_o\);
+
+-- Location: IOIBUF_X0_Y23_N1
+\button2~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_button2,
+	o => \button2~input_o\);
+
+-- Location: IOIBUF_X41_Y15_N1
+\clk~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_clk,
+	o => \clk~input_o\);
+
+-- Location: CLKCTRL_G9
+\clk~inputclkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \clk~inputclkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \clk~inputclkctrl_outclk\);
+
+-- Location: IOIBUF_X0_Y23_N15
+\button1~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_button1,
+	o => \button1~input_o\);
+
+-- Location: LCCOMB_X19_Y27_N26
+\clockConv|start~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|start~0_combout\ = (\clockConv|start~q\) # (!\button1~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001111110011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button1~input_o\,
+	datac => \clockConv|start~q\,
+	combout => \clockConv|start~0_combout\);
+
+-- Location: FF_X19_Y27_N27
+\clockConv|start\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|start~q\);
+
+-- Location: LCCOMB_X19_Y28_N14
+\clockConv|ctr[0]~18\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[0]~18_combout\ = \clockConv|ctr\(0) $ (VCC)
+-- \clockConv|ctr[0]~19\ = CARRY(\clockConv|ctr\(0))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011001111001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(0),
+	datad => VCC,
+	combout => \clockConv|ctr[0]~18_combout\,
+	cout => \clockConv|ctr[0]~19\);
+
+-- Location: FF_X19_Y28_N15
+\clockConv|ctr[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[0]~18_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(0));
+
+-- Location: LCCOMB_X19_Y28_N16
+\clockConv|ctr[1]~20\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[1]~20_combout\ = (\clockConv|ctr\(1) & (!\clockConv|ctr[0]~19\)) # (!\clockConv|ctr\(1) & ((\clockConv|ctr[0]~19\) # (GND)))
+-- \clockConv|ctr[1]~21\ = CARRY((!\clockConv|ctr[0]~19\) # (!\clockConv|ctr\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(1),
+	datad => VCC,
+	cin => \clockConv|ctr[0]~19\,
+	combout => \clockConv|ctr[1]~20_combout\,
+	cout => \clockConv|ctr[1]~21\);
+
+-- Location: FF_X19_Y28_N17
+\clockConv|ctr[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[1]~20_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(1));
+
+-- Location: LCCOMB_X19_Y28_N18
+\clockConv|ctr[2]~22\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[2]~22_combout\ = (\clockConv|ctr\(2) & (\clockConv|ctr[1]~21\ $ (GND))) # (!\clockConv|ctr\(2) & (!\clockConv|ctr[1]~21\ & VCC))
+-- \clockConv|ctr[2]~23\ = CARRY((\clockConv|ctr\(2) & !\clockConv|ctr[1]~21\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(2),
+	datad => VCC,
+	cin => \clockConv|ctr[1]~21\,
+	combout => \clockConv|ctr[2]~22_combout\,
+	cout => \clockConv|ctr[2]~23\);
+
+-- Location: FF_X19_Y28_N19
+\clockConv|ctr[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[2]~22_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(2));
+
+-- Location: LCCOMB_X19_Y28_N20
+\clockConv|ctr[3]~24\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[3]~24_combout\ = (\clockConv|ctr\(3) & (!\clockConv|ctr[2]~23\)) # (!\clockConv|ctr\(3) & ((\clockConv|ctr[2]~23\) # (GND)))
+-- \clockConv|ctr[3]~25\ = CARRY((!\clockConv|ctr[2]~23\) # (!\clockConv|ctr\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(3),
+	datad => VCC,
+	cin => \clockConv|ctr[2]~23\,
+	combout => \clockConv|ctr[3]~24_combout\,
+	cout => \clockConv|ctr[3]~25\);
+
+-- Location: FF_X19_Y28_N21
+\clockConv|ctr[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[3]~24_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(3));
+
+-- Location: LCCOMB_X19_Y28_N22
+\clockConv|ctr[4]~26\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[4]~26_combout\ = (\clockConv|ctr\(4) & (\clockConv|ctr[3]~25\ $ (GND))) # (!\clockConv|ctr\(4) & (!\clockConv|ctr[3]~25\ & VCC))
+-- \clockConv|ctr[4]~27\ = CARRY((\clockConv|ctr\(4) & !\clockConv|ctr[3]~25\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(4),
+	datad => VCC,
+	cin => \clockConv|ctr[3]~25\,
+	combout => \clockConv|ctr[4]~26_combout\,
+	cout => \clockConv|ctr[4]~27\);
+
+-- Location: FF_X19_Y28_N23
+\clockConv|ctr[4]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[4]~26_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(4));
+
+-- Location: LCCOMB_X19_Y28_N24
+\clockConv|ctr[5]~28\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[5]~28_combout\ = (\clockConv|ctr\(5) & (!\clockConv|ctr[4]~27\)) # (!\clockConv|ctr\(5) & ((\clockConv|ctr[4]~27\) # (GND)))
+-- \clockConv|ctr[5]~29\ = CARRY((!\clockConv|ctr[4]~27\) # (!\clockConv|ctr\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(5),
+	datad => VCC,
+	cin => \clockConv|ctr[4]~27\,
+	combout => \clockConv|ctr[5]~28_combout\,
+	cout => \clockConv|ctr[5]~29\);
+
+-- Location: FF_X19_Y28_N25
+\clockConv|ctr[5]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[5]~28_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(5));
+
+-- Location: LCCOMB_X19_Y28_N26
+\clockConv|ctr[6]~30\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[6]~30_combout\ = (\clockConv|ctr\(6) & (\clockConv|ctr[5]~29\ $ (GND))) # (!\clockConv|ctr\(6) & (!\clockConv|ctr[5]~29\ & VCC))
+-- \clockConv|ctr[6]~31\ = CARRY((\clockConv|ctr\(6) & !\clockConv|ctr[5]~29\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(6),
+	datad => VCC,
+	cin => \clockConv|ctr[5]~29\,
+	combout => \clockConv|ctr[6]~30_combout\,
+	cout => \clockConv|ctr[6]~31\);
+
+-- Location: FF_X19_Y28_N27
+\clockConv|ctr[6]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[6]~30_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(6));
+
+-- Location: LCCOMB_X19_Y28_N28
+\clockConv|ctr[7]~32\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[7]~32_combout\ = (\clockConv|ctr\(7) & (!\clockConv|ctr[6]~31\)) # (!\clockConv|ctr\(7) & ((\clockConv|ctr[6]~31\) # (GND)))
+-- \clockConv|ctr[7]~33\ = CARRY((!\clockConv|ctr[6]~31\) # (!\clockConv|ctr\(7)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(7),
+	datad => VCC,
+	cin => \clockConv|ctr[6]~31\,
+	combout => \clockConv|ctr[7]~32_combout\,
+	cout => \clockConv|ctr[7]~33\);
+
+-- Location: FF_X19_Y28_N29
+\clockConv|ctr[7]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[7]~32_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(7));
+
+-- Location: LCCOMB_X19_Y28_N30
+\clockConv|ctr[8]~34\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[8]~34_combout\ = (\clockConv|ctr\(8) & (\clockConv|ctr[7]~33\ $ (GND))) # (!\clockConv|ctr\(8) & (!\clockConv|ctr[7]~33\ & VCC))
+-- \clockConv|ctr[8]~35\ = CARRY((\clockConv|ctr\(8) & !\clockConv|ctr[7]~33\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(8),
+	datad => VCC,
+	cin => \clockConv|ctr[7]~33\,
+	combout => \clockConv|ctr[8]~34_combout\,
+	cout => \clockConv|ctr[8]~35\);
+
+-- Location: FF_X19_Y28_N31
+\clockConv|ctr[8]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[8]~34_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(8));
+
+-- Location: LCCOMB_X19_Y27_N0
+\clockConv|ctr[9]~36\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[9]~36_combout\ = (\clockConv|ctr\(9) & (!\clockConv|ctr[8]~35\)) # (!\clockConv|ctr\(9) & ((\clockConv|ctr[8]~35\) # (GND)))
+-- \clockConv|ctr[9]~37\ = CARRY((!\clockConv|ctr[8]~35\) # (!\clockConv|ctr\(9)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(9),
+	datad => VCC,
+	cin => \clockConv|ctr[8]~35\,
+	combout => \clockConv|ctr[9]~36_combout\,
+	cout => \clockConv|ctr[9]~37\);
+
+-- Location: FF_X19_Y27_N1
+\clockConv|ctr[9]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[9]~36_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(9));
+
+-- Location: LCCOMB_X19_Y27_N2
+\clockConv|ctr[10]~38\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[10]~38_combout\ = (\clockConv|ctr\(10) & (\clockConv|ctr[9]~37\ $ (GND))) # (!\clockConv|ctr\(10) & (!\clockConv|ctr[9]~37\ & VCC))
+-- \clockConv|ctr[10]~39\ = CARRY((\clockConv|ctr\(10) & !\clockConv|ctr[9]~37\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(10),
+	datad => VCC,
+	cin => \clockConv|ctr[9]~37\,
+	combout => \clockConv|ctr[10]~38_combout\,
+	cout => \clockConv|ctr[10]~39\);
+
+-- Location: FF_X19_Y27_N3
+\clockConv|ctr[10]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[10]~38_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(10));
+
+-- Location: LCCOMB_X19_Y27_N4
+\clockConv|ctr[11]~40\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[11]~40_combout\ = (\clockConv|ctr\(11) & (!\clockConv|ctr[10]~39\)) # (!\clockConv|ctr\(11) & ((\clockConv|ctr[10]~39\) # (GND)))
+-- \clockConv|ctr[11]~41\ = CARRY((!\clockConv|ctr[10]~39\) # (!\clockConv|ctr\(11)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(11),
+	datad => VCC,
+	cin => \clockConv|ctr[10]~39\,
+	combout => \clockConv|ctr[11]~40_combout\,
+	cout => \clockConv|ctr[11]~41\);
+
+-- Location: FF_X19_Y27_N5
+\clockConv|ctr[11]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[11]~40_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(11));
+
+-- Location: LCCOMB_X19_Y27_N6
+\clockConv|ctr[12]~42\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[12]~42_combout\ = (\clockConv|ctr\(12) & (\clockConv|ctr[11]~41\ $ (GND))) # (!\clockConv|ctr\(12) & (!\clockConv|ctr[11]~41\ & VCC))
+-- \clockConv|ctr[12]~43\ = CARRY((\clockConv|ctr\(12) & !\clockConv|ctr[11]~41\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(12),
+	datad => VCC,
+	cin => \clockConv|ctr[11]~41\,
+	combout => \clockConv|ctr[12]~42_combout\,
+	cout => \clockConv|ctr[12]~43\);
+
+-- Location: FF_X19_Y27_N7
+\clockConv|ctr[12]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[12]~42_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(12));
+
+-- Location: LCCOMB_X19_Y27_N8
+\clockConv|ctr[13]~44\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[13]~44_combout\ = (\clockConv|ctr\(13) & (!\clockConv|ctr[12]~43\)) # (!\clockConv|ctr\(13) & ((\clockConv|ctr[12]~43\) # (GND)))
+-- \clockConv|ctr[13]~45\ = CARRY((!\clockConv|ctr[12]~43\) # (!\clockConv|ctr\(13)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011110000111111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(13),
+	datad => VCC,
+	cin => \clockConv|ctr[12]~43\,
+	combout => \clockConv|ctr[13]~44_combout\,
+	cout => \clockConv|ctr[13]~45\);
+
+-- Location: FF_X19_Y27_N9
+\clockConv|ctr[13]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[13]~44_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(13));
+
+-- Location: LCCOMB_X19_Y27_N10
+\clockConv|ctr[14]~46\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[14]~46_combout\ = (\clockConv|ctr\(14) & (\clockConv|ctr[13]~45\ $ (GND))) # (!\clockConv|ctr\(14) & (!\clockConv|ctr[13]~45\ & VCC))
+-- \clockConv|ctr[14]~47\ = CARRY((\clockConv|ctr\(14) & !\clockConv|ctr[13]~45\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010010100001010",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(14),
+	datad => VCC,
+	cin => \clockConv|ctr[13]~45\,
+	combout => \clockConv|ctr[14]~46_combout\,
+	cout => \clockConv|ctr[14]~47\);
+
+-- Location: FF_X19_Y27_N11
+\clockConv|ctr[14]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[14]~46_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(14));
+
+-- Location: LCCOMB_X19_Y27_N12
+\clockConv|ctr[15]~48\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[15]~48_combout\ = (\clockConv|ctr\(15) & (!\clockConv|ctr[14]~47\)) # (!\clockConv|ctr\(15) & ((\clockConv|ctr[14]~47\) # (GND)))
+-- \clockConv|ctr[15]~49\ = CARRY((!\clockConv|ctr[14]~47\) # (!\clockConv|ctr\(15)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101101001011111",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(15),
+	datad => VCC,
+	cin => \clockConv|ctr[14]~47\,
+	combout => \clockConv|ctr[15]~48_combout\,
+	cout => \clockConv|ctr[15]~49\);
+
+-- Location: FF_X19_Y27_N13
+\clockConv|ctr[15]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[15]~48_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(15));
+
+-- Location: LCCOMB_X19_Y27_N14
+\clockConv|ctr[16]~50\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[16]~50_combout\ = (\clockConv|ctr\(16) & (\clockConv|ctr[15]~49\ $ (GND))) # (!\clockConv|ctr\(16) & (!\clockConv|ctr[15]~49\ & VCC))
+-- \clockConv|ctr[16]~51\ = CARRY((\clockConv|ctr\(16) & !\clockConv|ctr[15]~49\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100001100001100",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datab => \clockConv|ctr\(16),
+	datad => VCC,
+	cin => \clockConv|ctr[15]~49\,
+	combout => \clockConv|ctr[16]~50_combout\,
+	cout => \clockConv|ctr[16]~51\);
+
+-- Location: FF_X19_Y27_N15
+\clockConv|ctr[16]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[16]~50_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(16));
+
+-- Location: LCCOMB_X19_Y27_N16
+\clockConv|ctr[17]~52\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|ctr[17]~52_combout\ = \clockConv|ctr[16]~51\ $ (\clockConv|ctr\(17))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111111110000",
+	sum_lutc_input => "cin")
+-- pragma translate_on
+PORT MAP (
+	datad => \clockConv|ctr\(17),
+	cin => \clockConv|ctr[16]~51\,
+	combout => \clockConv|ctr[17]~52_combout\);
+
+-- Location: FF_X19_Y27_N17
+\clockConv|ctr[17]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|ctr[17]~52_combout\,
+	sclr => \clockConv|ALT_INV_LessThan0~5_combout\,
+	ena => \clockConv|start~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|ctr\(17));
+
+-- Location: LCCOMB_X19_Y27_N18
+\clockConv|LessThan0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~0_combout\ = (\clockConv|ctr\(14) & (\clockConv|ctr\(17) & (\clockConv|ctr\(16) & \clockConv|ctr\(15))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1000000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(14),
+	datab => \clockConv|ctr\(17),
+	datac => \clockConv|ctr\(16),
+	datad => \clockConv|ctr\(15),
+	combout => \clockConv|LessThan0~0_combout\);
+
+-- Location: LCCOMB_X19_Y28_N12
+\clockConv|LessThan0~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~3_combout\ = (!\clockConv|ctr\(6) & (!\clockConv|ctr\(4) & !\clockConv|ctr\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(6),
+	datac => \clockConv|ctr\(4),
+	datad => \clockConv|ctr\(5),
+	combout => \clockConv|LessThan0~3_combout\);
+
+-- Location: LCCOMB_X19_Y28_N8
+\clockConv|LessThan0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~1_combout\ = (!\clockConv|ctr\(8) & (!\clockConv|ctr\(9) & (!\clockConv|ctr\(10) & !\clockConv|ctr\(11))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(8),
+	datab => \clockConv|ctr\(9),
+	datac => \clockConv|ctr\(10),
+	datad => \clockConv|ctr\(11),
+	combout => \clockConv|LessThan0~1_combout\);
+
+-- Location: LCCOMB_X19_Y28_N10
+\clockConv|LessThan0~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~2_combout\ = (((!\clockConv|ctr\(1)) # (!\clockConv|ctr\(0))) # (!\clockConv|ctr\(2))) # (!\clockConv|ctr\(3))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111111111111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(3),
+	datab => \clockConv|ctr\(2),
+	datac => \clockConv|ctr\(0),
+	datad => \clockConv|ctr\(1),
+	combout => \clockConv|LessThan0~2_combout\);
+
+-- Location: LCCOMB_X19_Y28_N2
+\clockConv|LessThan0~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~4_combout\ = (\clockConv|LessThan0~1_combout\ & (((\clockConv|LessThan0~3_combout\ & \clockConv|LessThan0~2_combout\)) # (!\clockConv|ctr\(7))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1011000000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|LessThan0~3_combout\,
+	datab => \clockConv|ctr\(7),
+	datac => \clockConv|LessThan0~1_combout\,
+	datad => \clockConv|LessThan0~2_combout\,
+	combout => \clockConv|LessThan0~4_combout\);
+
+-- Location: LCCOMB_X19_Y27_N24
+\clockConv|LessThan0~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|LessThan0~5_combout\ = ((!\clockConv|ctr\(13) & ((\clockConv|LessThan0~4_combout\) # (!\clockConv|ctr\(12))))) # (!\clockConv|LessThan0~0_combout\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011111100011111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|ctr\(12),
+	datab => \clockConv|ctr\(13),
+	datac => \clockConv|LessThan0~0_combout\,
+	datad => \clockConv|LessThan0~4_combout\,
+	combout => \clockConv|LessThan0~5_combout\);
+
+-- Location: LCCOMB_X19_Y27_N28
+\clockConv|clock_out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|clock_out~0_combout\ = \clockConv|clock_out~q\ $ (((!\clockConv|LessThan0~5_combout\ & ((\clockConv|start~q\) # (!\button1~input_o\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000001001011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \clockConv|start~q\,
+	datab => \button1~input_o\,
+	datac => \clockConv|clock_out~q\,
+	datad => \clockConv|LessThan0~5_combout\,
+	combout => \clockConv|clock_out~0_combout\);
+
+-- Location: LCCOMB_X19_Y27_N22
+\clockConv|clock_out~feeder\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \clockConv|clock_out~feeder_combout\ = \clockConv|clock_out~0_combout\
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datad => \clockConv|clock_out~0_combout\,
+	combout => \clockConv|clock_out~feeder_combout\);
+
+-- Location: FF_X19_Y27_N23
+\clockConv|clock_out\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clk~inputclkctrl_outclk\,
+	d => \clockConv|clock_out~feeder_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \clockConv|clock_out~q\);
+
+-- Location: CLKCTRL_G14
+\clockConv|clock_out~clkctrl\ : cycloneiii_clkctrl
+-- pragma translate_off
+GENERIC MAP (
+	clock_type => "global clock",
+	ena_register_mode => "none")
+-- pragma translate_on
+PORT MAP (
+	inclk => \clockConv|clock_out~clkctrl_INCLK_bus\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	outclk => \clockConv|clock_out~clkctrl_outclk\);
+
+-- Location: IOIBUF_X0_Y21_N8
+\button0~input\ : cycloneiii_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_button0,
+	o => \button0~input_o\);
+
+-- Location: FF_X28_Y27_N27
+\timeCount|en\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	asdata => \timeCount|always0~0_combout\,
+	sload => VCC,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|en~q\);
+
+-- Location: LCCOMB_X28_Y27_N0
+\timeCount|always0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|always0~0_combout\ = ((\timeCount|en~q\ & \button1~input_o\)) # (!\button0~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001100110011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button0~input_o\,
+	datac => \timeCount|en~q\,
+	datad => \button1~input_o\,
+	combout => \timeCount|always0~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N4
+\timeCount|c0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~0_combout\ = (!\timeCount|c2[0]~0_combout\ & (!\timeCount|c0\(0) & !\timeCount|always0~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000011",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|c2[0]~0_combout\,
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c0~0_combout\);
+
+-- Location: FF_X28_Y28_N5
+\timeCount|c0[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~0_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(0));
+
+-- Location: LCCOMB_X28_Y28_N6
+\timeCount|c0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~1_combout\ = (!\timeCount|always0~0_combout\ & (!\timeCount|c2[0]~0_combout\ & (\timeCount|c0\(0) $ (\timeCount|c0\(1)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000010010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(0),
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c0\(1),
+	datad => \timeCount|c2[0]~0_combout\,
+	combout => \timeCount|c0~1_combout\);
+
+-- Location: FF_X28_Y28_N7
+\timeCount|c0[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~1_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(1));
+
+-- Location: LCCOMB_X28_Y28_N0
+\timeCount|c2[0]~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~0_combout\ = (!\timeCount|c0\(1) & (\timeCount|c0\(3) & (\timeCount|c0\(0) & !\timeCount|c0\(2))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \timeCount|c2[0]~0_combout\);
+
+-- Location: LCCOMB_X29_Y28_N18
+\timeCount|Add3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add3~0_combout\ = (\timeCount|c0\(0) & \timeCount|c0\(1))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100000011000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|c0\(0),
+	datac => \timeCount|c0\(1),
+	combout => \timeCount|Add3~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N24
+\timeCount|c0~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~2_combout\ = (!\timeCount|c2[0]~0_combout\ & (!\timeCount|always0~0_combout\ & (\timeCount|c0\(2) $ (\timeCount|Add3~0_combout\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~0_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c0\(2),
+	datad => \timeCount|Add3~0_combout\,
+	combout => \timeCount|c0~2_combout\);
+
+-- Location: FF_X28_Y28_N25
+\timeCount|c0[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(2));
+
+-- Location: LCCOMB_X28_Y27_N22
+\timeCount|c0[3]~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0[3]~3_combout\ = (\button0~input_o\ & (!\timeCount|c2[0]~0_combout\ & ((!\timeCount|en~q\) # (!\button1~input_o\))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button1~input_o\,
+	datab => \button0~input_o\,
+	datac => \timeCount|en~q\,
+	datad => \timeCount|c2[0]~0_combout\,
+	combout => \timeCount|c0[3]~3_combout\);
+
+-- Location: LCCOMB_X28_Y28_N2
+\timeCount|c0~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c0~4_combout\ = (\timeCount|c0[3]~3_combout\ & (\timeCount|c0\(3) $ (((\timeCount|c0\(2) & \timeCount|Add3~0_combout\)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(2),
+	datab => \timeCount|Add3~0_combout\,
+	datac => \timeCount|c0\(3),
+	datad => \timeCount|c0[3]~3_combout\,
+	combout => \timeCount|c0~4_combout\);
+
+-- Location: FF_X28_Y28_N3
+\timeCount|c0[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c0~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c0\(3));
+
+-- Location: LCCOMB_X29_Y28_N12
+\dss0|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out~0_combout\ = (!\timeCount|c0\(3) & (!\timeCount|c0\(1) & (\timeCount|c0\(0) $ (\timeCount|c0\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(3),
+	datab => \timeCount|c0\(1),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|out~0_combout\);
+
+-- Location: LCCOMB_X29_Y28_N8
+\dss0|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(0) = (\button2~input_o\ & ((\dss0|out~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(0),
+	datac => \button2~input_o\,
+	datad => \dss0|out~0_combout\,
+	combout => \dss0|out\(0));
+
+-- Location: LCCOMB_X28_Y28_N20
+\dss0|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out~1_combout\ = (!\timeCount|c0\(3) & (\timeCount|c0\(2) & (\timeCount|c0\(1) $ (\timeCount|c0\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001001000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|out~1_combout\);
+
+-- Location: LCCOMB_X28_Y28_N30
+\dss0|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(1) = (\button2~input_o\ & (\dss0|out~1_combout\)) # (!\button2~input_o\ & ((\dss0|out\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out~1_combout\,
+	datac => \dss0|out\(1),
+	datad => \button2~input_o\,
+	combout => \dss0|out\(1));
+
+-- Location: LCCOMB_X28_Y28_N14
+\dss0|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr4~0_combout\ = (\timeCount|c0\(2) & (((\timeCount|c0\(3))))) # (!\timeCount|c0\(2) & (\timeCount|c0\(1) & ((\timeCount|c0\(3)) # (!\timeCount|c0\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000010100010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(0),
+	datac => \timeCount|c0\(3),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N16
+\dss0|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(2) = (\button2~input_o\ & ((\dss0|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(2),
+	datac => \dss0|WideOr4~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss0|out\(2));
+
+-- Location: LCCOMB_X28_Y28_N8
+\dss0|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr3~0_combout\ = (!\timeCount|c0\(3) & ((\timeCount|c0\(1) & (\timeCount|c0\(0) & \timeCount|c0\(2))) # (!\timeCount|c0\(1) & (\timeCount|c0\(0) $ (\timeCount|c0\(2))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000010010100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(0),
+	datac => \timeCount|c0\(2),
+	datad => \timeCount|c0\(3),
+	combout => \dss0|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N18
+\dss0|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(3) = (\button2~input_o\ & ((\dss0|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(3),
+	datac => \dss0|WideOr3~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss0|out\(3));
+
+-- Location: LCCOMB_X28_Y28_N10
+\dss0|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr2~0_combout\ = (\timeCount|c0\(1) & (!\timeCount|c0\(3) & (\timeCount|c0\(0)))) # (!\timeCount|c0\(1) & ((\timeCount|c0\(2) & (!\timeCount|c0\(3))) # (!\timeCount|c0\(2) & ((\timeCount|c0\(0))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011000101110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N28
+\dss0|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(4) = (\button2~input_o\ & ((\dss0|WideOr2~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(4)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss0|out\(4),
+	datac => \button2~input_o\,
+	datad => \dss0|WideOr2~0_combout\,
+	combout => \dss0|out\(4));
+
+-- Location: LCCOMB_X28_Y28_N12
+\dss0|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr1~0_combout\ = (!\timeCount|c0\(3) & ((\timeCount|c0\(1) & ((\timeCount|c0\(0)) # (!\timeCount|c0\(2)))) # (!\timeCount|c0\(1) & (!\timeCount|c0\(2) & \timeCount|c0\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000101100000010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(2),
+	datac => \timeCount|c0\(3),
+	datad => \timeCount|c0\(0),
+	combout => \dss0|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X29_Y28_N10
+\dss0|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(5) = (\button2~input_o\ & ((\dss0|WideOr1~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101000001010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss0|out\(5),
+	datac => \button2~input_o\,
+	datad => \dss0|WideOr1~0_combout\,
+	combout => \dss0|out\(5));
+
+-- Location: LCCOMB_X28_Y28_N26
+\dss0|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|WideOr0~0_combout\ = (\timeCount|c0\(3)) # ((\timeCount|c0\(1) & ((!\timeCount|c0\(2)) # (!\timeCount|c0\(0)))) # (!\timeCount|c0\(1) & ((\timeCount|c0\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1101111111101110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c0\(1),
+	datab => \timeCount|c0\(3),
+	datac => \timeCount|c0\(0),
+	datad => \timeCount|c0\(2),
+	combout => \dss0|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X28_Y28_N22
+\dss0|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss0|out\(6) = (\button2~input_o\ & ((!\dss0|WideOr0~0_combout\))) # (!\button2~input_o\ & (\dss0|out\(6)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111110101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss0|out\(6),
+	datac => \dss0|WideOr0~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss0|out\(6));
+
+-- Location: LCCOMB_X27_Y27_N22
+\timeCount|c1~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~1_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & (\timeCount|c1\(1) $ (\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \timeCount|c1~1_combout\);
+
+-- Location: FF_X27_Y27_N23
+\timeCount|c1[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~1_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(1));
+
+-- Location: LCCOMB_X26_Y27_N22
+\timeCount|Add2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add2~0_combout\ = \timeCount|c1\(2) $ (((\timeCount|c1\(0) & \timeCount|c1\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110101001101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(2),
+	datab => \timeCount|c1\(0),
+	datac => \timeCount|c1\(1),
+	combout => \timeCount|Add2~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N4
+\timeCount|c1~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~2_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|Add2~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|Add2~0_combout\,
+	combout => \timeCount|c1~2_combout\);
+
+-- Location: FF_X27_Y27_N5
+\timeCount|c1[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~2_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(2));
+
+-- Location: LCCOMB_X26_Y27_N24
+\timeCount|Add2~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add2~1_combout\ = \timeCount|c1\(3) $ (((\timeCount|c1\(0) & (\timeCount|c1\(1) & \timeCount|c1\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0110110011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(0),
+	datab => \timeCount|c1\(3),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(2),
+	combout => \timeCount|Add2~1_combout\);
+
+-- Location: LCCOMB_X27_Y27_N26
+\timeCount|c1~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~3_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|Add2~1_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|Add2~1_combout\,
+	combout => \timeCount|c1~3_combout\);
+
+-- Location: FF_X27_Y27_N27
+\timeCount|c1[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~3_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(3));
+
+-- Location: LCCOMB_X27_Y27_N20
+\timeCount|c2[0]~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~1_combout\ = (!\timeCount|c1\(1) & (!\timeCount|c1\(2) & (\timeCount|c1\(3) & \timeCount|c1\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(1),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(3),
+	datad => \timeCount|c1\(0),
+	combout => \timeCount|c2[0]~1_combout\);
+
+-- Location: LCCOMB_X27_Y27_N0
+\timeCount|c1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c1~0_combout\ = (!\timeCount|c2[0]~1_combout\ & (!\timeCount|always0~0_combout\ & !\timeCount|c1\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100000001",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~1_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|c1\(0),
+	combout => \timeCount|c1~0_combout\);
+
+-- Location: FF_X27_Y27_N1
+\timeCount|c1[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c1~0_combout\,
+	ena => \timeCount|ALT_INV_c0[3]~3_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c1\(0));
+
+-- Location: LCCOMB_X27_Y27_N12
+\dss1|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out~0_combout\ = (!\timeCount|c1\(1) & (!\timeCount|c1\(3) & (\timeCount|c1\(0) $ (\timeCount|c1\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(0),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(3),
+	combout => \dss1|out~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N6
+\dss1|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(0) = (\button2~input_o\ & ((\dss1|out~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|out\(0),
+	datad => \dss1|out~0_combout\,
+	combout => \dss1|out\(0));
+
+-- Location: LCCOMB_X27_Y27_N30
+\dss1|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out~1_combout\ = (!\timeCount|c1\(3) & (\timeCount|c1\(2) & (\timeCount|c1\(1) $ (\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010001000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|out~1_combout\);
+
+-- Location: LCCOMB_X27_Y27_N28
+\dss1|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(1) = (\button2~input_o\ & (\dss1|out~1_combout\)) # (!\button2~input_o\ & ((\dss1|out\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111010110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|out~1_combout\,
+	datad => \dss1|out\(1),
+	combout => \dss1|out\(1));
+
+-- Location: LCCOMB_X26_Y27_N28
+\dss1|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr4~0_combout\ = (\timeCount|c1\(2) & (((\timeCount|c1\(3))))) # (!\timeCount|c1\(2) & (\timeCount|c1\(1) & ((\timeCount|c1\(3)) # (!\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110111000000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(2),
+	datab => \timeCount|c1\(1),
+	datac => \timeCount|c1\(0),
+	datad => \timeCount|c1\(3),
+	combout => \dss1|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X26_Y27_N30
+\dss1|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(2) = (\button2~input_o\ & ((\dss1|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss1|out\(2),
+	datad => \dss1|WideOr4~0_combout\,
+	combout => \dss1|out\(2));
+
+-- Location: LCCOMB_X27_Y27_N16
+\dss1|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr3~0_combout\ = (!\timeCount|c1\(3) & ((\timeCount|c1\(2) & (\timeCount|c1\(1) $ (!\timeCount|c1\(0)))) # (!\timeCount|c1\(2) & (!\timeCount|c1\(1) & \timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100000100000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X26_Y27_N8
+\dss1|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(3) = (\button2~input_o\ & ((\dss1|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss1|out\(3),
+	datad => \dss1|WideOr3~0_combout\,
+	combout => \dss1|out\(3));
+
+-- Location: LCCOMB_X27_Y27_N10
+\dss1|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr2~0_combout\ = (\timeCount|c1\(1) & (\timeCount|c1\(0) & ((!\timeCount|c1\(3))))) # (!\timeCount|c1\(1) & ((\timeCount|c1\(2) & ((!\timeCount|c1\(3)))) # (!\timeCount|c1\(2) & (\timeCount|c1\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000001010101110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(0),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(3),
+	combout => \dss1|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N2
+\dss1|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(4) = (\button2~input_o\ & ((\dss1|WideOr2~0_combout\))) # (!\button2~input_o\ & (\dss1|out\(4)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|out\(4),
+	datad => \dss1|WideOr2~0_combout\,
+	combout => \dss1|out\(4));
+
+-- Location: LCCOMB_X27_Y27_N8
+\dss1|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr1~0_combout\ = (!\timeCount|c1\(3) & ((\timeCount|c1\(2) & (\timeCount|c1\(1) & \timeCount|c1\(0))) # (!\timeCount|c1\(2) & ((\timeCount|c1\(1)) # (\timeCount|c1\(0))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N24
+\dss1|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(5) = (\button2~input_o\ & (\dss1|WideOr1~0_combout\)) # (!\button2~input_o\ & ((\dss1|out\(5))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111010110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|WideOr1~0_combout\,
+	datad => \dss1|out\(5),
+	combout => \dss1|out\(5));
+
+-- Location: LCCOMB_X27_Y27_N14
+\dss1|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|WideOr0~0_combout\ = (\timeCount|c1\(3)) # ((\timeCount|c1\(2) & ((!\timeCount|c1\(0)) # (!\timeCount|c1\(1)))) # (!\timeCount|c1\(2) & (\timeCount|c1\(1))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1011111011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c1\(3),
+	datab => \timeCount|c1\(2),
+	datac => \timeCount|c1\(1),
+	datad => \timeCount|c1\(0),
+	combout => \dss1|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X27_Y27_N18
+\dss1|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss1|out\(6) = (\button2~input_o\ & (!\dss1|WideOr0~0_combout\)) # (!\button2~input_o\ & ((\dss1|out\(6))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111100001010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss1|WideOr0~0_combout\,
+	datad => \dss1|out\(6),
+	combout => \dss1|out\(6));
+
+-- Location: LCCOMB_X28_Y27_N16
+\timeCount|c2~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~3_combout\ = (!\timeCount|c2[0]~2_combout\ & (!\timeCount|c2\(0) & !\timeCount|always0~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000000101",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c2~3_combout\);
+
+-- Location: LCCOMB_X28_Y27_N18
+\timeCount|c2[0]~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~4_combout\ = (\timeCount|always0~0_combout\) # ((\timeCount|c2[0]~1_combout\ & \timeCount|c2[0]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|c2[0]~0_combout\,
+	combout => \timeCount|c2[0]~4_combout\);
+
+-- Location: FF_X28_Y27_N17
+\timeCount|c2[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~3_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(0));
+
+-- Location: LCCOMB_X28_Y27_N6
+\timeCount|c2~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~5_combout\ = (!\timeCount|c2[0]~2_combout\ & (!\timeCount|always0~0_combout\ & (\timeCount|c2\(0) $ (\timeCount|c2\(1)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000000010100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(1),
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c2~5_combout\);
+
+-- Location: FF_X28_Y27_N7
+\timeCount|c2[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~5_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(1));
+
+-- Location: LCCOMB_X28_Y27_N26
+\timeCount|Add1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add1~0_combout\ = \timeCount|c2\(2) $ (((\timeCount|c2\(1) & \timeCount|c2\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111011110001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \timeCount|Add1~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N28
+\timeCount|c2~6\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~6_combout\ = (!\timeCount|c2[0]~2_combout\ & (\timeCount|Add1~0_combout\ & !\timeCount|always0~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datac => \timeCount|Add1~0_combout\,
+	datad => \timeCount|always0~0_combout\,
+	combout => \timeCount|c2~6_combout\);
+
+-- Location: FF_X28_Y27_N29
+\timeCount|c2[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~6_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(2));
+
+-- Location: LCCOMB_X28_Y27_N12
+\timeCount|c2[0]~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2[0]~2_combout\ = (!\timeCount|c2\(1) & (\timeCount|c2\(0) & (\timeCount|c2\(3) & !\timeCount|c2\(2))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000001000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \timeCount|c2[0]~2_combout\);
+
+-- Location: LCCOMB_X28_Y27_N20
+\timeCount|Add1~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add1~1_combout\ = \timeCount|c2\(3) $ (((\timeCount|c2\(1) & (\timeCount|c2\(0) & \timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111100011110000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \timeCount|Add1~1_combout\);
+
+-- Location: LCCOMB_X28_Y27_N14
+\timeCount|c2~7\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c2~7_combout\ = (!\timeCount|c2[0]~2_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|Add1~1_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001000000010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2[0]~2_combout\,
+	datab => \timeCount|always0~0_combout\,
+	datac => \timeCount|Add1~1_combout\,
+	combout => \timeCount|c2~7_combout\);
+
+-- Location: FF_X28_Y27_N15
+\timeCount|c2[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c2~7_combout\,
+	ena => \timeCount|c2[0]~4_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c2\(3));
+
+-- Location: LCCOMB_X29_Y27_N24
+\dss2|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out~0_combout\ = (!\timeCount|c2\(3) & (!\timeCount|c2\(1) & (\timeCount|c2\(0) $ (\timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|out~0_combout\);
+
+-- Location: LCCOMB_X29_Y27_N8
+\dss2|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(0) = (\button2~input_o\ & ((\dss2|out~0_combout\))) # (!\button2~input_o\ & (\dss2|out\(0)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(0),
+	datad => \dss2|out~0_combout\,
+	combout => \dss2|out\(0));
+
+-- Location: LCCOMB_X29_Y27_N18
+\dss2|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out~1_combout\ = (!\timeCount|c2\(3) & (\timeCount|c2\(2) & (\timeCount|c2\(1) $ (\timeCount|c2\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001010000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|out~1_combout\);
+
+-- Location: LCCOMB_X29_Y27_N30
+\dss2|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(1) = (\button2~input_o\ & ((\dss2|out~1_combout\))) # (!\button2~input_o\ & (\dss2|out\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(1),
+	datad => \dss2|out~1_combout\,
+	combout => \dss2|out\(1));
+
+-- Location: LCCOMB_X29_Y27_N28
+\dss2|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr4~0_combout\ = (\timeCount|c2\(2) & (\timeCount|c2\(3))) # (!\timeCount|c2\(2) & (\timeCount|c2\(1) & ((\timeCount|c2\(3)) # (!\timeCount|c2\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1010101010001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X29_Y27_N4
+\dss2|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(2) = (\button2~input_o\ & ((\dss2|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss2|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(2),
+	datad => \dss2|WideOr4~0_combout\,
+	combout => \dss2|out\(2));
+
+-- Location: LCCOMB_X29_Y27_N6
+\dss2|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr3~0_combout\ = (!\timeCount|c2\(3) & ((\timeCount|c2\(1) & (\timeCount|c2\(0) & \timeCount|c2\(2))) # (!\timeCount|c2\(1) & (\timeCount|c2\(0) $ (\timeCount|c2\(2))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0100000100010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(3),
+	datab => \timeCount|c2\(1),
+	datac => \timeCount|c2\(0),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X29_Y27_N26
+\dss2|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(3) = (\button2~input_o\ & ((\dss2|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss2|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111101001010000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \button2~input_o\,
+	datac => \dss2|out\(3),
+	datad => \dss2|WideOr3~0_combout\,
+	combout => \dss2|out\(3));
+
+-- Location: LCCOMB_X28_Y27_N4
+\dss2|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr2~0_combout\ = (\timeCount|c2\(1) & (\timeCount|c2\(0) & (!\timeCount|c2\(3)))) # (!\timeCount|c2\(1) & ((\timeCount|c2\(2) & ((!\timeCount|c2\(3)))) # (!\timeCount|c2\(2) & (\timeCount|c2\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110101001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N2
+\dss2|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(4) = (\button2~input_o\ & (\dss2|WideOr2~0_combout\)) # (!\button2~input_o\ & ((\dss2|out\(4))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss2|WideOr2~0_combout\,
+	datad => \dss2|out\(4),
+	combout => \dss2|out\(4));
+
+-- Location: LCCOMB_X28_Y27_N30
+\dss2|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr1~0_combout\ = (!\timeCount|c2\(3) & ((\timeCount|c2\(1) & ((\timeCount|c2\(0)) # (!\timeCount|c2\(2)))) # (!\timeCount|c2\(1) & (\timeCount|c2\(0) & !\timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100000001110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N24
+\dss2|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(5) = (\button2~input_o\ & (\dss2|WideOr1~0_combout\)) # (!\button2~input_o\ & ((\dss2|out\(5))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111001111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss2|WideOr1~0_combout\,
+	datad => \dss2|out\(5),
+	combout => \dss2|out\(5));
+
+-- Location: LCCOMB_X28_Y27_N8
+\dss2|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|WideOr0~0_combout\ = (\timeCount|c2\(3)) # ((\timeCount|c2\(1) & ((!\timeCount|c2\(2)) # (!\timeCount|c2\(0)))) # (!\timeCount|c2\(1) & ((\timeCount|c2\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011111111010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c2\(1),
+	datab => \timeCount|c2\(0),
+	datac => \timeCount|c2\(3),
+	datad => \timeCount|c2\(2),
+	combout => \dss2|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X28_Y27_N10
+\dss2|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss2|out\(6) = (\button2~input_o\ & (!\dss2|WideOr0~0_combout\)) # (!\button2~input_o\ & ((\dss2|out\(6))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011111100001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \button2~input_o\,
+	datac => \dss2|WideOr0~0_combout\,
+	datad => \dss2|out\(6),
+	combout => \dss2|out\(6));
+
+-- Location: LCCOMB_X26_Y28_N8
+\timeCount|Add0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add0~0_combout\ = \timeCount|c3\(2) $ (((\timeCount|c3\(1) & \timeCount|c3\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101111110100000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(2),
+	combout => \timeCount|Add0~0_combout\);
+
+-- Location: LCCOMB_X26_Y28_N6
+\timeCount|c3~4\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~4_combout\ = (!\timeCount|always0~0_combout\ & (\timeCount|Add0~0_combout\ & \timeCount|c3[1]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0101000000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datac => \timeCount|Add0~0_combout\,
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~4_combout\);
+
+-- Location: LCCOMB_X27_Y28_N28
+\timeCount|c3[1]~2\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3[1]~2_combout\ = (\timeCount|always0~0_combout\) # ((\timeCount|c2[0]~1_combout\ & (\timeCount|c2[0]~0_combout\ & \timeCount|c2[0]~2_combout\)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110101010101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datab => \timeCount|c2[0]~1_combout\,
+	datac => \timeCount|c2[0]~0_combout\,
+	datad => \timeCount|c2[0]~2_combout\,
+	combout => \timeCount|c3[1]~2_combout\);
+
+-- Location: FF_X27_Y28_N17
+\timeCount|c3[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	asdata => \timeCount|c3~4_combout\,
+	sload => VCC,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(2));
+
+-- Location: LCCOMB_X26_Y28_N10
+\timeCount|c3[1]~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3[1]~0_combout\ = (\timeCount|c3\(1)) # ((\timeCount|c3\(2)) # ((!\timeCount|c3\(3)) # (!\timeCount|c3\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1110111111111111",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(3),
+	combout => \timeCount|c3[1]~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N0
+\timeCount|c3~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~1_combout\ = (!\timeCount|always0~0_combout\ & (!\timeCount|c3\(0) & \timeCount|c3[1]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010100000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~1_combout\);
+
+-- Location: FF_X27_Y28_N1
+\timeCount|c3[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c3~1_combout\,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(0));
+
+-- Location: LCCOMB_X27_Y28_N30
+\timeCount|c3~3\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~3_combout\ = (!\timeCount|always0~0_combout\ & (\timeCount|c3[1]~0_combout\ & (\timeCount|c3\(0) $ (\timeCount|c3\(1)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0001010000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|always0~0_combout\,
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(1),
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~3_combout\);
+
+-- Location: FF_X27_Y28_N31
+\timeCount|c3[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c3~3_combout\,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(1));
+
+-- Location: LCCOMB_X26_Y28_N24
+\timeCount|Add0~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|Add0~1_combout\ = \timeCount|c3\(3) $ (((\timeCount|c3\(1) & (\timeCount|c3\(2) & \timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0111111110000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(3),
+	combout => \timeCount|Add0~1_combout\);
+
+-- Location: LCCOMB_X27_Y28_N26
+\timeCount|c3~5\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \timeCount|c3~5_combout\ = (\timeCount|Add0~1_combout\ & (!\timeCount|always0~0_combout\ & \timeCount|c3[1]~0_combout\))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \timeCount|Add0~1_combout\,
+	datac => \timeCount|always0~0_combout\,
+	datad => \timeCount|c3[1]~0_combout\,
+	combout => \timeCount|c3~5_combout\);
+
+-- Location: FF_X27_Y28_N27
+\timeCount|c3[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+	is_wysiwyg => "true",
+	power_up => "low")
+-- pragma translate_on
+PORT MAP (
+	clk => \clockConv|clock_out~clkctrl_outclk\,
+	d => \timeCount|c3~5_combout\,
+	ena => \timeCount|c3[1]~2_combout\,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor,
+	q => \timeCount|c3\(3));
+
+-- Location: LCCOMB_X27_Y28_N24
+\dss3|out~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out~0_combout\ = (!\timeCount|c3\(3) & (!\timeCount|c3\(1) & (\timeCount|c3\(2) $ (\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000000100000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(3),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(1),
+	datad => \timeCount|c3\(0),
+	combout => \dss3|out~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N10
+\dss3|out[0]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(0) = (\button2~input_o\ & (\dss3|out~0_combout\)) # (!\button2~input_o\ & ((\dss3|out\(0))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100111111000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out~0_combout\,
+	datac => \button2~input_o\,
+	datad => \dss3|out\(0),
+	combout => \dss3|out\(0));
+
+-- Location: LCCOMB_X27_Y28_N2
+\dss3|out~1\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out~1_combout\ = (\timeCount|c3\(2) & (!\timeCount|c3\(3) & (\timeCount|c3\(1) $ (\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000010000001000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(0),
+	combout => \dss3|out~1_combout\);
+
+-- Location: LCCOMB_X27_Y28_N16
+\dss3|out[1]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(1) = (\button2~input_o\ & ((\dss3|out~1_combout\))) # (!\button2~input_o\ & (\dss3|out\(1)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110010101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss3|out\(1),
+	datab => \dss3|out~1_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(1));
+
+-- Location: LCCOMB_X26_Y28_N12
+\dss3|WideOr4~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr4~0_combout\ = (\timeCount|c3\(2) & (((\timeCount|c3\(3))))) # (!\timeCount|c3\(2) & (\timeCount|c3\(1) & ((\timeCount|c3\(3)) # (!\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110010001010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(3),
+	datac => \timeCount|c3\(0),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr4~0_combout\);
+
+-- Location: LCCOMB_X26_Y28_N18
+\dss3|out[2]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(2) = (\button2~input_o\ & ((\dss3|WideOr4~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(2)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111110000001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out\(2),
+	datac => \button2~input_o\,
+	datad => \dss3|WideOr4~0_combout\,
+	combout => \dss3|out\(2));
+
+-- Location: LCCOMB_X27_Y28_N8
+\dss3|WideOr3~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr3~0_combout\ = (!\timeCount|c3\(3) & ((\timeCount|c3\(1) & (\timeCount|c3\(0) & \timeCount|c3\(2))) # (!\timeCount|c3\(1) & (\timeCount|c3\(0) $ (\timeCount|c3\(2))))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100100000100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr3~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N20
+\dss3|out[3]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(3) = (\button2~input_o\ & ((\dss3|WideOr3~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(3)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out\(3),
+	datac => \dss3|WideOr3~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(3));
+
+-- Location: LCCOMB_X27_Y28_N22
+\dss3|WideOr2~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr2~0_combout\ = (\timeCount|c3\(1) & (\timeCount|c3\(0) & (!\timeCount|c3\(3)))) # (!\timeCount|c3\(1) & ((\timeCount|c3\(2) & ((!\timeCount|c3\(3)))) # (!\timeCount|c3\(2) & (\timeCount|c3\(0)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000110101001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr2~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N18
+\dss3|out[4]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(4) = (\button2~input_o\ & ((\dss3|WideOr2~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(4)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000011001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \dss3|out\(4),
+	datac => \dss3|WideOr2~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(4));
+
+-- Location: LCCOMB_X27_Y28_N4
+\dss3|WideOr1~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr1~0_combout\ = (!\timeCount|c3\(3) & ((\timeCount|c3\(1) & ((\timeCount|c3\(0)) # (!\timeCount|c3\(2)))) # (!\timeCount|c3\(1) & (\timeCount|c3\(0) & !\timeCount|c3\(2)))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000100000001110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(0),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(2),
+	combout => \dss3|WideOr1~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N12
+\dss3|out[5]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(5) = (\button2~input_o\ & ((\dss3|WideOr1~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(5)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111000010101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss3|out\(5),
+	datac => \dss3|WideOr1~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(5));
+
+-- Location: LCCOMB_X27_Y28_N14
+\dss3|WideOr0~0\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|WideOr0~0_combout\ = (\timeCount|c3\(3)) # ((\timeCount|c3\(1) & ((!\timeCount|c3\(0)) # (!\timeCount|c3\(2)))) # (!\timeCount|c3\(1) & (\timeCount|c3\(2))))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111011011111110",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \timeCount|c3\(1),
+	datab => \timeCount|c3\(2),
+	datac => \timeCount|c3\(3),
+	datad => \timeCount|c3\(0),
+	combout => \dss3|WideOr0~0_combout\);
+
+-- Location: LCCOMB_X27_Y28_N6
+\dss3|out[6]\ : cycloneiii_lcell_comb
+-- Equation(s):
+-- \dss3|out\(6) = (\button2~input_o\ & ((!\dss3|WideOr0~0_combout\))) # (!\button2~input_o\ & (\dss3|out\(6)))
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0000111110101010",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	dataa => \dss3|out\(6),
+	datac => \dss3|WideOr0~0_combout\,
+	datad => \button2~input_o\,
+	combout => \dss3|out\(6));
+
+ww_hex0(0) <= \hex0[0]~output_o\;
+
+ww_hex0(1) <= \hex0[1]~output_o\;
+
+ww_hex0(2) <= \hex0[2]~output_o\;
+
+ww_hex0(3) <= \hex0[3]~output_o\;
+
+ww_hex0(4) <= \hex0[4]~output_o\;
+
+ww_hex0(5) <= \hex0[5]~output_o\;
+
+ww_hex0(6) <= \hex0[6]~output_o\;
+
+ww_hex1(0) <= \hex1[0]~output_o\;
+
+ww_hex1(1) <= \hex1[1]~output_o\;
+
+ww_hex1(2) <= \hex1[2]~output_o\;
+
+ww_hex1(3) <= \hex1[3]~output_o\;
+
+ww_hex1(4) <= \hex1[4]~output_o\;
+
+ww_hex1(5) <= \hex1[5]~output_o\;
+
+ww_hex1(6) <= \hex1[6]~output_o\;
+
+ww_hex2(0) <= \hex2[0]~output_o\;
+
+ww_hex2(1) <= \hex2[1]~output_o\;
+
+ww_hex2(2) <= \hex2[2]~output_o\;
+
+ww_hex2(3) <= \hex2[3]~output_o\;
+
+ww_hex2(4) <= \hex2[4]~output_o\;
+
+ww_hex2(5) <= \hex2[5]~output_o\;
+
+ww_hex2(6) <= \hex2[6]~output_o\;
+
+ww_hex3(0) <= \hex3[0]~output_o\;
+
+ww_hex3(1) <= \hex3[1]~output_o\;
+
+ww_hex3(2) <= \hex3[2]~output_o\;
+
+ww_hex3(3) <= \hex3[3]~output_o\;
+
+ww_hex3(4) <= \hex3[4]~output_o\;
+
+ww_hex3(5) <= \hex3[5]~output_o\;
+
+ww_hex3(6) <= \hex3[6]~output_o\;
+
+ww_decimal_point <= \decimal_point~output_o\;
+END structure;
+
+
diff --git a/stopClockVerilog/simulation/modelsim/stopclock_min_1200mv_0c_vhd_fast.sdo b/stopClockVerilog/simulation/modelsim/stopclock_min_1200mv_0c_vhd_fast.sdo
new file mode 100644
index 0000000..45beb2a
--- /dev/null
+++ b/stopClockVerilog/simulation/modelsim/stopclock_min_1200mv_0c_vhd_fast.sdo
@@ -0,0 +1,2657 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16U484C6 Package UFBGA484
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP3C16U484C6,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "stopclock")
+  (DATE "03/02/2016 15:24:50")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (502:502:502) (550:550:550))
+        (IOPATH i o (1290:1290:1290) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (536:536:536) (591:591:591))
+        (IOPATH i o (1300:1300:1300) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (258:258:258) (279:279:279))
+        (IOPATH i o (1300:1300:1300) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (250:250:250) (270:270:270))
+        (IOPATH i o (1310:1310:1310) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (358:358:358) (386:386:386))
+        (IOPATH i o (1300:1300:1300) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (248:248:248) (270:270:270))
+        (IOPATH i o (1290:1290:1290) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (352:352:352) (382:382:382))
+        (IOPATH i o (1300:1300:1300) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (415:415:415) (465:465:465))
+        (IOPATH i o (1300:1300:1300) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (435:435:435) (484:484:484))
+        (IOPATH i o (1300:1300:1300) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (433:433:433) (470:470:470))
+        (IOPATH i o (1290:1290:1290) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (420:420:420) (461:461:461))
+        (IOPATH i o (1310:1310:1310) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (548:548:548) (613:613:613))
+        (IOPATH i o (1300:1300:1300) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (396:396:396) (435:435:435))
+        (IOPATH i o (1300:1300:1300) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (380:380:380) (415:415:415))
+        (IOPATH i o (1310:1310:1310) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (392:392:392) (429:429:429))
+        (IOPATH i o (1290:1290:1290) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (367:367:367) (405:405:405))
+        (IOPATH i o (1310:1310:1310) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (263:263:263) (288:288:288))
+        (IOPATH i o (1310:1310:1310) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (403:403:403) (441:441:441))
+        (IOPATH i o (1290:1290:1290) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (388:388:388) (425:425:425))
+        (IOPATH i o (1310:1310:1310) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (405:405:405) (445:445:445))
+        (IOPATH i o (1310:1310:1310) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (594:594:594) (655:655:655))
+        (IOPATH i o (1300:1300:1300) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (472:472:472) (510:510:510))
+        (IOPATH i o (1310:1310:1310) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (666:666:666) (736:736:736))
+        (IOPATH i o (1300:1300:1300) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (464:464:464) (506:506:506))
+        (IOPATH i o (1320:1320:1320) (1311:1311:1311))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (497:497:497) (531:531:531))
+        (IOPATH i o (1310:1310:1310) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (588:588:588) (640:640:640))
+        (IOPATH i o (1310:1310:1310) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (580:580:580) (637:637:637))
+        (IOPATH i o (1310:1310:1310) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (581:581:581) (640:640:640))
+        (IOPATH i o (1290:1290:1290) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\button2\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (391:391:391) (773:773:773))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\clk\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (401:401:401) (783:783:783))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\clk\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (97:97:97) (82:82:82))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\button1\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|start\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1981:1981:1981) (2225:2225:2225))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|start\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1076:1076:1076) (1110:1110:1110))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[0\]\~18\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (184:184:184))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1076:1076:1076) (1109:1109:1109))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (555:555:555) (562:562:562))
+        (PORT ena (604:604:604) (644:644:644))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[1\]\~20\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (133:133:133) (183:183:183))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1076:1076:1076) (1109:1109:1109))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (555:555:555) (562:562:562))
+        (PORT ena (604:604:604) (644:644:644))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[2\]\~22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (134:134:134) (185:185:185))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (880:880:880) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (555:555:555) (562:562:562))
+        (PORT ena (618:618:618) (665:665:665))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[3\]\~24\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (880:880:880) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (555:555:555) (562:562:562))
+        (PORT ena (618:618:618) (665:665:665))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[4\]\~26\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (186:186:186))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (880:880:880) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (555:555:555) (562:562:562))
+        (PORT ena (618:618:618) (665:665:665))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[5\]\~28\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (213:213:213) (267:267:267))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (880:880:880) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (555:555:555) (562:562:562))
+        (PORT ena (618:618:618) (665:665:665))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[6\]\~30\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (188:188:188))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (880:880:880) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (555:555:555) (562:562:562))
+        (PORT ena (618:618:618) (665:665:665))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[7\]\~32\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (133:133:133) (183:183:183))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[7\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1076:1076:1076) (1109:1109:1109))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (555:555:555) (562:562:562))
+        (PORT ena (604:604:604) (644:644:644))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[8\]\~34\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (187:187:187))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[8\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (880:880:880) (885:885:885))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (555:555:555) (562:562:562))
+        (PORT ena (618:618:618) (665:665:665))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[9\]\~36\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (140:140:140) (188:188:188))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[9\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (374:374:374))
+        (PORT ena (606:606:606) (657:657:657))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[10\]\~38\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (141:141:141) (189:189:189))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[10\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (374:374:374))
+        (PORT ena (606:606:606) (657:657:657))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[11\]\~40\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (189:189:189))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[11\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (374:374:374))
+        (PORT ena (606:606:606) (657:657:657))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[12\]\~42\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (188:188:188))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[12\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (374:374:374))
+        (PORT ena (606:606:606) (657:657:657))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[13\]\~44\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (184:184:184))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[13\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (374:374:374))
+        (PORT ena (606:606:606) (657:657:657))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[14\]\~46\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (189:189:189))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[14\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (374:374:374))
+        (PORT ena (606:606:606) (657:657:657))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[15\]\~48\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (188:188:188))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[15\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (374:374:374))
+        (PORT ena (606:606:606) (657:657:657))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[16\]\~50\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[16\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (374:374:374))
+        (PORT ena (606:606:606) (657:657:657))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[17\]\~52\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (122:122:122) (160:160:160))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[17\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (884:884:884))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (348:348:348) (374:374:374))
+        (PORT ena (606:606:606) (657:657:657))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (190:190:190))
+        (PORT datab (134:134:134) (184:184:184))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (122:122:122) (162:162:162))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (191:191:191))
+        (PORT datac (123:123:123) (165:165:165))
+        (PORT datad (130:130:130) (167:167:167))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (139:139:139) (191:191:191))
+        (PORT datab (214:214:214) (269:269:269))
+        (PORT datac (294:294:294) (345:345:345))
+        (PORT datad (293:293:293) (345:345:345))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (214:214:214) (269:269:269))
+        (PORT datab (135:135:135) (186:186:186))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (122:122:122) (161:161:161))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (135:135:135))
+        (PORT datab (138:138:138) (189:189:189))
+        (PORT datac (89:89:89) (110:110:110))
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (139:139:139) (191:191:191))
+        (PORT datab (137:137:137) (187:187:187))
+        (PORT datac (161:161:161) (193:193:193))
+        (PORT datad (298:298:298) (342:342:342))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|clock_out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (130:130:130) (181:181:181))
+        (PORT datab (1981:1981:1981) (2225:2225:2225))
+        (PORT datac (1105:1105:1105) (1256:1256:1256))
+        (PORT datad (107:107:107) (124:124:124))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|clock_out\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|clock_out\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1076:1076:1076) (1110:1110:1110))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\clockConv\|clock_out\~clkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (427:427:427) (471:471:471))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\button0\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (381:381:381) (763:763:763))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|en\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT asdata (495:495:495) (527:527:527))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|always0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2082:2082:2082) (2343:2343:2343))
+        (PORT datac (124:124:124) (168:168:168))
+        (PORT datad (1997:1997:1997) (2253:2253:2253))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (133:133:133) (163:163:163))
+        (PORT datad (327:327:327) (375:375:375))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (874:874:874) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (285:285:285))
+        (PORT datab (345:345:345) (401:401:401))
+        (PORT datad (121:121:121) (139:139:139))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (874:874:874) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (172:172:172) (236:236:236))
+        (PORT datab (172:172:172) (226:226:226))
+        (PORT datac (151:151:151) (200:200:200))
+        (PORT datad (166:166:166) (213:213:213))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (222:222:222) (282:282:282))
+        (PORT datac (203:203:203) (250:250:250))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (261:261:261))
+        (PORT datab (342:342:342) (399:399:399))
+        (PORT datad (176:176:176) (208:208:208))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (874:874:874) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\[3\]\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2022:2022:2022) (2285:2285:2285))
+        (PORT datab (2083:2083:2083) (2343:2343:2343))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (337:337:337) (384:384:384))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (236:236:236) (293:293:293))
+        (PORT datab (197:197:197) (237:237:237))
+        (PORT datad (305:305:305) (346:346:346))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (160:160:160) (176:176:176))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (874:874:874) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (237:237:237) (290:290:290))
+        (PORT datab (214:214:214) (269:269:269))
+        (PORT datac (205:205:205) (256:256:256))
+        (PORT datad (217:217:217) (263:263:263))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (115:115:115) (142:142:142))
+        (PORT datac (969:969:969) (1094:1094:1094))
+        (PORT datad (90:90:90) (106:106:106))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (176:176:176) (239:239:239))
+        (PORT datab (176:176:176) (232:232:232))
+        (PORT datac (154:154:154) (203:203:203))
+        (PORT datad (161:161:161) (206:206:206))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (103:103:103) (130:130:130))
+        (PORT datac (101:101:101) (121:121:121))
+        (PORT datad (1000:1000:1000) (1133:1133:1133))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (174:174:174) (238:238:238))
+        (PORT datab (168:168:168) (224:224:224))
+        (PORT datac (217:217:217) (263:263:263))
+        (PORT datad (165:165:165) (207:207:207))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (115:115:115) (143:143:143))
+        (PORT datac (89:89:89) (109:109:109))
+        (PORT datad (996:996:996) (1128:1128:1128))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (173:173:173) (236:236:236))
+        (PORT datab (166:166:166) (224:224:224))
+        (PORT datac (219:219:219) (265:265:265))
+        (PORT datad (159:159:159) (204:204:204))
+        (IOPATH dataa combout (181:181:181) (193:193:193))
+        (IOPATH datab combout (191:191:191) (188:188:188))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (115:115:115) (144:144:144))
+        (PORT datac (90:90:90) (112:112:112))
+        (PORT datad (999:999:999) (1132:1132:1132))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (173:173:173) (238:238:238))
+        (PORT datab (172:172:172) (228:228:228))
+        (PORT datac (151:151:151) (202:202:202))
+        (PORT datad (161:161:161) (211:211:211))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (114:114:114) (142:142:142))
+        (PORT datac (964:964:964) (1095:1095:1095))
+        (PORT datad (91:91:91) (109:109:109))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (172:172:172) (239:239:239))
+        (PORT datab (178:178:178) (232:232:232))
+        (PORT datac (217:217:217) (263:263:263))
+        (PORT datad (209:209:209) (258:258:258))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (116:116:116) (147:147:147))
+        (PORT datac (969:969:969) (1096:1096:1096))
+        (PORT datad (166:166:166) (193:193:193))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (177:177:177) (242:242:242))
+        (PORT datab (176:176:176) (233:233:233))
+        (PORT datac (154:154:154) (208:208:208))
+        (PORT datad (160:160:160) (204:204:204))
+        (IOPATH dataa combout (172:172:172) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (116:116:116) (146:146:146))
+        (PORT datac (89:89:89) (110:110:110))
+        (PORT datad (998:998:998) (1130:1130:1130))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (207:207:207) (248:248:248))
+        (PORT datab (242:242:242) (287:287:287))
+        (PORT datad (342:342:342) (401:401:401))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (874:874:874) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (553:553:553) (523:523:523))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (305:305:305))
+        (PORT datab (251:251:251) (315:315:315))
+        (PORT datac (340:340:340) (397:397:397))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (209:209:209) (252:252:252))
+        (PORT datac (218:218:218) (261:261:261))
+        (PORT datad (159:159:159) (185:185:185))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (874:874:874) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (553:553:553) (523:523:523))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add2\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (373:373:373) (446:446:446))
+        (PORT datab (245:245:245) (301:301:301))
+        (PORT datac (340:340:340) (397:397:397))
+        (PORT datad (221:221:221) (276:276:276))
+        (IOPATH dataa combout (166:166:166) (157:157:157))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (206:206:206) (248:248:248))
+        (PORT datac (224:224:224) (267:267:267))
+        (PORT datad (167:167:167) (196:196:196))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (874:874:874) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (553:553:553) (523:523:523))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (183:183:183) (248:248:248))
+        (PORT datab (175:175:175) (234:234:234))
+        (PORT datac (160:160:160) (211:211:211))
+        (PORT datad (149:149:149) (194:194:194))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (210:210:210) (252:252:252))
+        (PORT datab (235:235:235) (280:280:280))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (874:874:874) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (553:553:553) (523:523:523))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (247:247:247) (311:311:311))
+        (PORT datab (169:169:169) (232:232:232))
+        (PORT datac (169:169:169) (224:224:224))
+        (PORT datad (215:215:215) (261:261:261))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (872:872:872) (993:993:993))
+        (PORT datac (166:166:166) (195:195:195))
+        (PORT datad (90:90:90) (106:106:106))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (174:174:174) (232:232:232))
+        (PORT datab (175:175:175) (236:236:236))
+        (PORT datac (165:165:165) (219:219:219))
+        (PORT datad (150:150:150) (194:194:194))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (872:872:872) (993:993:993))
+        (PORT datac (88:88:88) (109:109:109))
+        (PORT datad (102:102:102) (118:118:118))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (308:308:308))
+        (PORT datab (238:238:238) (293:293:293))
+        (PORT datac (233:233:233) (294:294:294))
+        (PORT datad (225:225:225) (274:274:274))
+        (IOPATH dataa combout (166:166:166) (159:159:159))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (871:871:871) (988:988:988))
+        (PORT datac (101:101:101) (121:121:121))
+        (PORT datad (89:89:89) (106:106:106))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (176:176:176) (234:234:234))
+        (PORT datab (172:172:172) (232:232:232))
+        (PORT datac (167:167:167) (222:222:222))
+        (PORT datad (149:149:149) (192:192:192))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (872:872:872) (988:988:988))
+        (PORT datac (102:102:102) (122:122:122))
+        (PORT datad (161:161:161) (186:186:186))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (247:247:247) (311:311:311))
+        (PORT datab (169:169:169) (230:230:230))
+        (PORT datac (169:169:169) (224:224:224))
+        (PORT datad (215:215:215) (261:261:261))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (874:874:874) (997:997:997))
+        (PORT datac (166:166:166) (195:195:195))
+        (PORT datad (90:90:90) (106:106:106))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (178:178:178) (236:236:236))
+        (PORT datab (169:169:169) (229:229:229))
+        (PORT datac (170:170:170) (225:225:225))
+        (PORT datad (144:144:144) (188:188:188))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (871:871:871) (993:993:993))
+        (PORT datac (91:91:91) (111:111:111))
+        (PORT datad (102:102:102) (118:118:118))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (178:178:178) (239:239:239))
+        (PORT datab (171:171:171) (230:230:230))
+        (PORT datac (169:169:169) (223:223:223))
+        (PORT datad (146:146:146) (191:191:191))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (169:169:169) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (871:871:871) (992:992:992))
+        (PORT datac (89:89:89) (110:110:110))
+        (PORT datad (103:103:103) (120:120:120))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (132:132:132) (170:170:170))
+        (PORT datad (132:132:132) (155:155:155))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (204:204:204) (242:242:242))
+        (PORT datac (317:317:317) (351:351:351))
+        (PORT datad (337:337:337) (384:384:384))
+        (IOPATH datab combout (166:166:166) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (406:406:406) (422:422:422))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (132:132:132) (169:169:169))
+        (PORT datab (170:170:170) (232:232:232))
+        (PORT datad (128:128:128) (151:151:151))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (191:191:191) (188:188:188))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (406:406:406) (422:422:422))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (174:174:174) (239:239:239))
+        (PORT datab (171:171:171) (232:232:232))
+        (PORT datad (148:148:148) (192:192:192))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (133:133:133) (175:175:175))
+        (PORT datac (286:286:286) (333:333:333))
+        (PORT datad (133:133:133) (156:156:156))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (406:406:406) (422:422:422))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (169:169:169) (234:234:234))
+        (PORT datab (169:169:169) (229:229:229))
+        (PORT datac (147:147:147) (197:197:197))
+        (PORT datad (150:150:150) (199:199:199))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add1\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (174:174:174) (234:234:234))
+        (PORT datab (171:171:171) (231:231:231))
+        (PORT datac (146:146:146) (195:195:195))
+        (PORT datad (149:149:149) (194:194:194))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (160:160:160) (176:176:176))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~7\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (134:134:134) (170:170:170))
+        (PORT datab (144:144:144) (178:178:178))
+        (PORT datac (161:161:161) (189:189:189))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (406:406:406) (422:422:422))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (229:229:229) (290:290:290))
+        (PORT datab (227:227:227) (284:284:284))
+        (PORT datac (212:212:212) (262:262:262))
+        (PORT datad (220:220:220) (271:271:271))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (868:868:868) (985:985:985))
+        (PORT datac (102:102:102) (122:122:122))
+        (PORT datad (92:92:92) (108:108:108))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (292:292:292))
+        (PORT datab (228:228:228) (286:286:286))
+        (PORT datac (212:212:212) (262:262:262))
+        (PORT datad (221:221:221) (271:271:271))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (868:868:868) (985:985:985))
+        (PORT datac (101:101:101) (121:121:121))
+        (PORT datad (90:90:90) (106:106:106))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (232:232:232) (293:293:293))
+        (PORT datab (229:229:229) (287:287:287))
+        (PORT datac (213:213:213) (263:263:263))
+        (PORT datad (220:220:220) (271:271:271))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (868:868:868) (985:985:985))
+        (PORT datac (101:101:101) (122:122:122))
+        (PORT datad (93:93:93) (109:109:109))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (227:227:227) (288:288:288))
+        (PORT datab (224:224:224) (281:281:281))
+        (PORT datac (212:212:212) (262:262:262))
+        (PORT datad (222:222:222) (273:273:273))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (868:868:868) (985:985:985))
+        (PORT datac (101:101:101) (122:122:122))
+        (PORT datad (92:92:92) (110:110:110))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (167:167:167) (228:228:228))
+        (PORT datab (169:169:169) (230:230:230))
+        (PORT datac (145:145:145) (193:193:193))
+        (PORT datad (153:153:153) (195:195:195))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (850:850:850) (963:963:963))
+        (PORT datac (88:88:88) (109:109:109))
+        (PORT datad (102:102:102) (118:118:118))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (173:173:173) (238:238:238))
+        (PORT datab (170:170:170) (231:231:231))
+        (PORT datac (146:146:146) (199:199:199))
+        (PORT datad (148:148:148) (191:191:191))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (847:847:847) (959:959:959))
+        (PORT datac (89:89:89) (109:109:109))
+        (PORT datad (102:102:102) (118:118:118))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (167:167:167) (230:230:230))
+        (PORT datab (168:168:168) (230:230:230))
+        (PORT datac (146:146:146) (195:195:195))
+        (PORT datad (153:153:153) (195:195:195))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (849:849:849) (962:962:962))
+        (PORT datac (89:89:89) (110:110:110))
+        (PORT datad (103:103:103) (119:119:119))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (248:248:248) (316:316:316))
+        (PORT datac (228:228:228) (287:287:287))
+        (PORT datad (215:215:215) (263:263:263))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (399:399:399))
+        (PORT datac (90:90:90) (110:110:110))
+        (PORT datad (103:103:103) (119:119:119))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\[1\]\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (397:397:397))
+        (PORT datab (318:318:318) (365:365:365))
+        (PORT datac (204:204:204) (241:241:241))
+        (PORT datad (293:293:293) (331:331:331))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (874:874:874) (878:878:878))
+        (PORT asdata (337:337:337) (361:361:361))
+        (PORT ena (422:422:422) (450:450:450))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\[1\]\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (249:249:249) (319:319:319))
+        (PORT datab (229:229:229) (290:290:290))
+        (PORT datac (230:230:230) (288:288:288))
+        (PORT datad (222:222:222) (275:275:275))
+        (IOPATH dataa combout (166:166:166) (157:157:157))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (351:351:351) (404:404:404))
+        (PORT datad (189:189:189) (219:219:219))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (874:874:874) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (422:422:422) (450:450:450))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (397:397:397))
+        (PORT datab (175:175:175) (237:237:237))
+        (PORT datad (193:193:193) (223:223:223))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (874:874:874) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (422:422:422) (450:450:450))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (245:245:245) (313:313:313))
+        (PORT datab (226:226:226) (286:286:286))
+        (PORT datac (232:232:232) (291:291:291))
+        (PORT datad (219:219:219) (271:271:271))
+        (IOPATH dataa combout (181:181:181) (180:180:180))
+        (IOPATH datab combout (182:182:182) (181:181:181))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (186:186:186) (222:222:222))
+        (PORT datac (329:329:329) (372:372:372))
+        (PORT datad (193:193:193) (223:223:223))
+        (IOPATH datab combout (166:166:166) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (874:874:874) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (422:422:422) (450:450:450))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (165:165:165) (225:225:225))
+        (PORT datab (162:162:162) (218:218:218))
+        (PORT datac (150:150:150) (201:201:201))
+        (PORT datad (160:160:160) (210:210:210))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (103:103:103) (133:133:133))
+        (PORT datac (971:971:971) (1091:1091:1091))
+        (PORT datad (103:103:103) (119:119:119))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (173:173:173) (237:237:237))
+        (PORT datab (168:168:168) (226:226:226))
+        (PORT datac (156:156:156) (210:210:210))
+        (PORT datad (152:152:152) (200:200:200))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (313:313:313) (360:360:360))
+        (PORT datab (104:104:104) (133:133:133))
+        (PORT datad (987:987:987) (1117:1117:1117))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (167:167:167) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (248:248:248) (317:317:317))
+        (PORT datab (239:239:239) (299:299:299))
+        (PORT datac (229:229:229) (287:287:287))
+        (PORT datad (212:212:212) (261:261:261))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (115:115:115) (144:144:144))
+        (PORT datac (961:961:961) (1088:1088:1088))
+        (PORT datad (90:90:90) (107:107:107))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (173:173:173) (235:235:235))
+        (PORT datab (167:167:167) (227:227:227))
+        (PORT datac (155:155:155) (205:205:205))
+        (PORT datad (149:149:149) (197:197:197))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (115:115:115) (143:143:143))
+        (PORT datac (90:90:90) (112:112:112))
+        (PORT datad (990:990:990) (1122:1122:1122))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (167:167:167) (230:230:230))
+        (PORT datab (173:173:173) (234:234:234))
+        (PORT datac (149:149:149) (202:202:202))
+        (PORT datad (149:149:149) (194:194:194))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (115:115:115) (144:144:144))
+        (PORT datac (89:89:89) (111:111:111))
+        (PORT datad (990:990:990) (1122:1122:1122))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (173:173:173) (236:236:236))
+        (PORT datab (166:166:166) (227:227:227))
+        (PORT datac (156:156:156) (205:205:205))
+        (PORT datad (150:150:150) (197:197:197))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (116:116:116) (147:147:147))
+        (PORT datac (89:89:89) (111:111:111))
+        (PORT datad (988:988:988) (1118:1118:1118))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (168:168:168) (234:234:234))
+        (PORT datab (162:162:162) (218:218:218))
+        (PORT datac (155:155:155) (208:208:208))
+        (PORT datad (157:157:157) (206:206:206))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (116:116:116) (146:146:146))
+        (PORT datac (89:89:89) (110:110:110))
+        (PORT datad (987:987:987) (1116:1116:1116))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+)
diff --git a/stopClockVerilog/simulation/modelsim/stopclock_modelsim.xrf b/stopClockVerilog/simulation/modelsim/stopclock_modelsim.xrf
new file mode 100644
index 0000000..30daba8
--- /dev/null
+++ b/stopClockVerilog/simulation/modelsim/stopclock_modelsim.xrf
@@ -0,0 +1,192 @@
+vendor_name = ModelSim
+source_file = 1, C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v
+source_file = 1, stopClock.bdf
+source_file = 1, C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopClockBlock.bdf
+source_file = 1, C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/db/stopclock.cbx.xml
+design_name = stopclock
+instance = comp, \hex0[0]~output\, hex0[0]~output, stopclock, 1
+instance = comp, \hex0[1]~output\, hex0[1]~output, stopclock, 1
+instance = comp, \hex0[2]~output\, hex0[2]~output, stopclock, 1
+instance = comp, \hex0[3]~output\, hex0[3]~output, stopclock, 1
+instance = comp, \hex0[4]~output\, hex0[4]~output, stopclock, 1
+instance = comp, \hex0[5]~output\, hex0[5]~output, stopclock, 1
+instance = comp, \hex0[6]~output\, hex0[6]~output, stopclock, 1
+instance = comp, \hex1[0]~output\, hex1[0]~output, stopclock, 1
+instance = comp, \hex1[1]~output\, hex1[1]~output, stopclock, 1
+instance = comp, \hex1[2]~output\, hex1[2]~output, stopclock, 1
+instance = comp, \hex1[3]~output\, hex1[3]~output, stopclock, 1
+instance = comp, \hex1[4]~output\, hex1[4]~output, stopclock, 1
+instance = comp, \hex1[5]~output\, hex1[5]~output, stopclock, 1
+instance = comp, \hex1[6]~output\, hex1[6]~output, stopclock, 1
+instance = comp, \hex2[0]~output\, hex2[0]~output, stopclock, 1
+instance = comp, \hex2[1]~output\, hex2[1]~output, stopclock, 1
+instance = comp, \hex2[2]~output\, hex2[2]~output, stopclock, 1
+instance = comp, \hex2[3]~output\, hex2[3]~output, stopclock, 1
+instance = comp, \hex2[4]~output\, hex2[4]~output, stopclock, 1
+instance = comp, \hex2[5]~output\, hex2[5]~output, stopclock, 1
+instance = comp, \hex2[6]~output\, hex2[6]~output, stopclock, 1
+instance = comp, \hex3[0]~output\, hex3[0]~output, stopclock, 1
+instance = comp, \hex3[1]~output\, hex3[1]~output, stopclock, 1
+instance = comp, \hex3[2]~output\, hex3[2]~output, stopclock, 1
+instance = comp, \hex3[3]~output\, hex3[3]~output, stopclock, 1
+instance = comp, \hex3[4]~output\, hex3[4]~output, stopclock, 1
+instance = comp, \hex3[5]~output\, hex3[5]~output, stopclock, 1
+instance = comp, \hex3[6]~output\, hex3[6]~output, stopclock, 1
+instance = comp, \decimal_point~output\, decimal_point~output, stopclock, 1
+instance = comp, \button2~input\, button2~input, stopclock, 1
+instance = comp, \clk~input\, clk~input, stopclock, 1
+instance = comp, \clk~inputclkctrl\, clk~inputclkctrl, stopclock, 1
+instance = comp, \button1~input\, button1~input, stopclock, 1
+instance = comp, \clockConv|start~0\, clockConv|start~0, stopclock, 1
+instance = comp, \clockConv|start\, clockConv|start, stopclock, 1
+instance = comp, \clockConv|ctr[0]~18\, clockConv|ctr[0]~18, stopclock, 1
+instance = comp, \clockConv|ctr[0]\, clockConv|ctr[0], stopclock, 1
+instance = comp, \clockConv|ctr[1]~20\, clockConv|ctr[1]~20, stopclock, 1
+instance = comp, \clockConv|ctr[1]\, clockConv|ctr[1], stopclock, 1
+instance = comp, \clockConv|ctr[2]~22\, clockConv|ctr[2]~22, stopclock, 1
+instance = comp, \clockConv|ctr[2]\, clockConv|ctr[2], stopclock, 1
+instance = comp, \clockConv|ctr[3]~24\, clockConv|ctr[3]~24, stopclock, 1
+instance = comp, \clockConv|ctr[3]\, clockConv|ctr[3], stopclock, 1
+instance = comp, \clockConv|ctr[4]~26\, clockConv|ctr[4]~26, stopclock, 1
+instance = comp, \clockConv|ctr[4]\, clockConv|ctr[4], stopclock, 1
+instance = comp, \clockConv|ctr[5]~28\, clockConv|ctr[5]~28, stopclock, 1
+instance = comp, \clockConv|ctr[5]\, clockConv|ctr[5], stopclock, 1
+instance = comp, \clockConv|ctr[6]~30\, clockConv|ctr[6]~30, stopclock, 1
+instance = comp, \clockConv|ctr[6]\, clockConv|ctr[6], stopclock, 1
+instance = comp, \clockConv|ctr[7]~32\, clockConv|ctr[7]~32, stopclock, 1
+instance = comp, \clockConv|ctr[7]\, clockConv|ctr[7], stopclock, 1
+instance = comp, \clockConv|ctr[8]~34\, clockConv|ctr[8]~34, stopclock, 1
+instance = comp, \clockConv|ctr[8]\, clockConv|ctr[8], stopclock, 1
+instance = comp, \clockConv|ctr[9]~36\, clockConv|ctr[9]~36, stopclock, 1
+instance = comp, \clockConv|ctr[9]\, clockConv|ctr[9], stopclock, 1
+instance = comp, \clockConv|ctr[10]~38\, clockConv|ctr[10]~38, stopclock, 1
+instance = comp, \clockConv|ctr[10]\, clockConv|ctr[10], stopclock, 1
+instance = comp, \clockConv|ctr[11]~40\, clockConv|ctr[11]~40, stopclock, 1
+instance = comp, \clockConv|ctr[11]\, clockConv|ctr[11], stopclock, 1
+instance = comp, \clockConv|ctr[12]~42\, clockConv|ctr[12]~42, stopclock, 1
+instance = comp, \clockConv|ctr[12]\, clockConv|ctr[12], stopclock, 1
+instance = comp, \clockConv|ctr[13]~44\, clockConv|ctr[13]~44, stopclock, 1
+instance = comp, \clockConv|ctr[13]\, clockConv|ctr[13], stopclock, 1
+instance = comp, \clockConv|ctr[14]~46\, clockConv|ctr[14]~46, stopclock, 1
+instance = comp, \clockConv|ctr[14]\, clockConv|ctr[14], stopclock, 1
+instance = comp, \clockConv|ctr[15]~48\, clockConv|ctr[15]~48, stopclock, 1
+instance = comp, \clockConv|ctr[15]\, clockConv|ctr[15], stopclock, 1
+instance = comp, \clockConv|ctr[16]~50\, clockConv|ctr[16]~50, stopclock, 1
+instance = comp, \clockConv|ctr[16]\, clockConv|ctr[16], stopclock, 1
+instance = comp, \clockConv|ctr[17]~52\, clockConv|ctr[17]~52, stopclock, 1
+instance = comp, \clockConv|ctr[17]\, clockConv|ctr[17], stopclock, 1
+instance = comp, \clockConv|LessThan0~0\, clockConv|LessThan0~0, stopclock, 1
+instance = comp, \clockConv|LessThan0~3\, clockConv|LessThan0~3, stopclock, 1
+instance = comp, \clockConv|LessThan0~1\, clockConv|LessThan0~1, stopclock, 1
+instance = comp, \clockConv|LessThan0~2\, clockConv|LessThan0~2, stopclock, 1
+instance = comp, \clockConv|LessThan0~4\, clockConv|LessThan0~4, stopclock, 1
+instance = comp, \clockConv|LessThan0~5\, clockConv|LessThan0~5, stopclock, 1
+instance = comp, \clockConv|clock_out~0\, clockConv|clock_out~0, stopclock, 1
+instance = comp, \clockConv|clock_out~feeder\, clockConv|clock_out~feeder, stopclock, 1
+instance = comp, \clockConv|clock_out\, clockConv|clock_out, stopclock, 1
+instance = comp, \clockConv|clock_out~clkctrl\, clockConv|clock_out~clkctrl, stopclock, 1
+instance = comp, \button0~input\, button0~input, stopclock, 1
+instance = comp, \timeCount|en\, timeCount|en, stopclock, 1
+instance = comp, \timeCount|always0~0\, timeCount|always0~0, stopclock, 1
+instance = comp, \timeCount|c0~0\, timeCount|c0~0, stopclock, 1
+instance = comp, \timeCount|c0[0]\, timeCount|c0[0], stopclock, 1
+instance = comp, \timeCount|c0~1\, timeCount|c0~1, stopclock, 1
+instance = comp, \timeCount|c0[1]\, timeCount|c0[1], stopclock, 1
+instance = comp, \timeCount|c2[0]~0\, timeCount|c2[0]~0, stopclock, 1
+instance = comp, \timeCount|Add3~0\, timeCount|Add3~0, stopclock, 1
+instance = comp, \timeCount|c0~2\, timeCount|c0~2, stopclock, 1
+instance = comp, \timeCount|c0[2]\, timeCount|c0[2], stopclock, 1
+instance = comp, \timeCount|c0[3]~3\, timeCount|c0[3]~3, stopclock, 1
+instance = comp, \timeCount|c0~4\, timeCount|c0~4, stopclock, 1
+instance = comp, \timeCount|c0[3]\, timeCount|c0[3], stopclock, 1
+instance = comp, \dss0|out~0\, dss0|out~0, stopclock, 1
+instance = comp, \dss0|out[0]\, dss0|out[0], stopclock, 1
+instance = comp, \dss0|out~1\, dss0|out~1, stopclock, 1
+instance = comp, \dss0|out[1]\, dss0|out[1], stopclock, 1
+instance = comp, \dss0|WideOr4~0\, dss0|WideOr4~0, stopclock, 1
+instance = comp, \dss0|out[2]\, dss0|out[2], stopclock, 1
+instance = comp, \dss0|WideOr3~0\, dss0|WideOr3~0, stopclock, 1
+instance = comp, \dss0|out[3]\, dss0|out[3], stopclock, 1
+instance = comp, \dss0|WideOr2~0\, dss0|WideOr2~0, stopclock, 1
+instance = comp, \dss0|out[4]\, dss0|out[4], stopclock, 1
+instance = comp, \dss0|WideOr1~0\, dss0|WideOr1~0, stopclock, 1
+instance = comp, \dss0|out[5]\, dss0|out[5], stopclock, 1
+instance = comp, \dss0|WideOr0~0\, dss0|WideOr0~0, stopclock, 1
+instance = comp, \dss0|out[6]\, dss0|out[6], stopclock, 1
+instance = comp, \timeCount|c1~1\, timeCount|c1~1, stopclock, 1
+instance = comp, \timeCount|c1[1]\, timeCount|c1[1], stopclock, 1
+instance = comp, \timeCount|Add2~0\, timeCount|Add2~0, stopclock, 1
+instance = comp, \timeCount|c1~2\, timeCount|c1~2, stopclock, 1
+instance = comp, \timeCount|c1[2]\, timeCount|c1[2], stopclock, 1
+instance = comp, \timeCount|Add2~1\, timeCount|Add2~1, stopclock, 1
+instance = comp, \timeCount|c1~3\, timeCount|c1~3, stopclock, 1
+instance = comp, \timeCount|c1[3]\, timeCount|c1[3], stopclock, 1
+instance = comp, \timeCount|c2[0]~1\, timeCount|c2[0]~1, stopclock, 1
+instance = comp, \timeCount|c1~0\, timeCount|c1~0, stopclock, 1
+instance = comp, \timeCount|c1[0]\, timeCount|c1[0], stopclock, 1
+instance = comp, \dss1|out~0\, dss1|out~0, stopclock, 1
+instance = comp, \dss1|out[0]\, dss1|out[0], stopclock, 1
+instance = comp, \dss1|out~1\, dss1|out~1, stopclock, 1
+instance = comp, \dss1|out[1]\, dss1|out[1], stopclock, 1
+instance = comp, \dss1|WideOr4~0\, dss1|WideOr4~0, stopclock, 1
+instance = comp, \dss1|out[2]\, dss1|out[2], stopclock, 1
+instance = comp, \dss1|WideOr3~0\, dss1|WideOr3~0, stopclock, 1
+instance = comp, \dss1|out[3]\, dss1|out[3], stopclock, 1
+instance = comp, \dss1|WideOr2~0\, dss1|WideOr2~0, stopclock, 1
+instance = comp, \dss1|out[4]\, dss1|out[4], stopclock, 1
+instance = comp, \dss1|WideOr1~0\, dss1|WideOr1~0, stopclock, 1
+instance = comp, \dss1|out[5]\, dss1|out[5], stopclock, 1
+instance = comp, \dss1|WideOr0~0\, dss1|WideOr0~0, stopclock, 1
+instance = comp, \dss1|out[6]\, dss1|out[6], stopclock, 1
+instance = comp, \timeCount|c2~3\, timeCount|c2~3, stopclock, 1
+instance = comp, \timeCount|c2[0]~4\, timeCount|c2[0]~4, stopclock, 1
+instance = comp, \timeCount|c2[0]\, timeCount|c2[0], stopclock, 1
+instance = comp, \timeCount|c2~5\, timeCount|c2~5, stopclock, 1
+instance = comp, \timeCount|c2[1]\, timeCount|c2[1], stopclock, 1
+instance = comp, \timeCount|Add1~0\, timeCount|Add1~0, stopclock, 1
+instance = comp, \timeCount|c2~6\, timeCount|c2~6, stopclock, 1
+instance = comp, \timeCount|c2[2]\, timeCount|c2[2], stopclock, 1
+instance = comp, \timeCount|c2[0]~2\, timeCount|c2[0]~2, stopclock, 1
+instance = comp, \timeCount|Add1~1\, timeCount|Add1~1, stopclock, 1
+instance = comp, \timeCount|c2~7\, timeCount|c2~7, stopclock, 1
+instance = comp, \timeCount|c2[3]\, timeCount|c2[3], stopclock, 1
+instance = comp, \dss2|out~0\, dss2|out~0, stopclock, 1
+instance = comp, \dss2|out[0]\, dss2|out[0], stopclock, 1
+instance = comp, \dss2|out~1\, dss2|out~1, stopclock, 1
+instance = comp, \dss2|out[1]\, dss2|out[1], stopclock, 1
+instance = comp, \dss2|WideOr4~0\, dss2|WideOr4~0, stopclock, 1
+instance = comp, \dss2|out[2]\, dss2|out[2], stopclock, 1
+instance = comp, \dss2|WideOr3~0\, dss2|WideOr3~0, stopclock, 1
+instance = comp, \dss2|out[3]\, dss2|out[3], stopclock, 1
+instance = comp, \dss2|WideOr2~0\, dss2|WideOr2~0, stopclock, 1
+instance = comp, \dss2|out[4]\, dss2|out[4], stopclock, 1
+instance = comp, \dss2|WideOr1~0\, dss2|WideOr1~0, stopclock, 1
+instance = comp, \dss2|out[5]\, dss2|out[5], stopclock, 1
+instance = comp, \dss2|WideOr0~0\, dss2|WideOr0~0, stopclock, 1
+instance = comp, \dss2|out[6]\, dss2|out[6], stopclock, 1
+instance = comp, \timeCount|Add0~0\, timeCount|Add0~0, stopclock, 1
+instance = comp, \timeCount|c3~4\, timeCount|c3~4, stopclock, 1
+instance = comp, \timeCount|c3[1]~2\, timeCount|c3[1]~2, stopclock, 1
+instance = comp, \timeCount|c3[2]\, timeCount|c3[2], stopclock, 1
+instance = comp, \timeCount|c3[1]~0\, timeCount|c3[1]~0, stopclock, 1
+instance = comp, \timeCount|c3~1\, timeCount|c3~1, stopclock, 1
+instance = comp, \timeCount|c3[0]\, timeCount|c3[0], stopclock, 1
+instance = comp, \timeCount|c3~3\, timeCount|c3~3, stopclock, 1
+instance = comp, \timeCount|c3[1]\, timeCount|c3[1], stopclock, 1
+instance = comp, \timeCount|Add0~1\, timeCount|Add0~1, stopclock, 1
+instance = comp, \timeCount|c3~5\, timeCount|c3~5, stopclock, 1
+instance = comp, \timeCount|c3[3]\, timeCount|c3[3], stopclock, 1
+instance = comp, \dss3|out~0\, dss3|out~0, stopclock, 1
+instance = comp, \dss3|out[0]\, dss3|out[0], stopclock, 1
+instance = comp, \dss3|out~1\, dss3|out~1, stopclock, 1
+instance = comp, \dss3|out[1]\, dss3|out[1], stopclock, 1
+instance = comp, \dss3|WideOr4~0\, dss3|WideOr4~0, stopclock, 1
+instance = comp, \dss3|out[2]\, dss3|out[2], stopclock, 1
+instance = comp, \dss3|WideOr3~0\, dss3|WideOr3~0, stopclock, 1
+instance = comp, \dss3|out[3]\, dss3|out[3], stopclock, 1
+instance = comp, \dss3|WideOr2~0\, dss3|WideOr2~0, stopclock, 1
+instance = comp, \dss3|out[4]\, dss3|out[4], stopclock, 1
+instance = comp, \dss3|WideOr1~0\, dss3|WideOr1~0, stopclock, 1
+instance = comp, \dss3|out[5]\, dss3|out[5], stopclock, 1
+instance = comp, \dss3|WideOr0~0\, dss3|WideOr0~0, stopclock, 1
+instance = comp, \dss3|out[6]\, dss3|out[6], stopclock, 1
diff --git a/stopClockVerilog/simulation/modelsim/stopclock_vhd.sdo b/stopClockVerilog/simulation/modelsim/stopclock_vhd.sdo
new file mode 100644
index 0000000..17a6f79
--- /dev/null
+++ b/stopClockVerilog/simulation/modelsim/stopclock_vhd.sdo
@@ -0,0 +1,2657 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16U484C6 Package UFBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16U484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "stopclock")
+  (DATE "03/02/2016 15:24:50")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 64-Bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (936:936:936) (922:922:922))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1016:1016:1016) (985:985:985))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (507:507:507) (491:491:491))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (486:486:486) (472:472:472))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (705:705:705) (690:690:690))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (484:484:484) (472:472:472))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex0\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (697:697:697) (680:680:680))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (780:780:780) (774:774:774))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (813:813:813) (804:804:804))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (792:792:792) (785:785:785))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (786:786:786) (767:767:767))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1039:1039:1039) (1026:1026:1026))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (766:766:766) (750:750:750))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex1\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (740:740:740) (729:729:729))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (736:736:736) (717:717:717))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (655:655:655) (677:677:677))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (507:507:507) (501:501:501))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (755:755:755) (742:742:742))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (727:727:727) (713:713:713))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (772:772:772) (758:758:758))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex2\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1128:1128:1128) (1089:1089:1089))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[0\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (898:898:898) (861:861:861))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[1\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1275:1275:1275) (1223:1223:1223))
+        (IOPATH i o (2060:2060:2060) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[2\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (876:876:876) (841:841:841))
+        (IOPATH i o (2080:2080:2080) (2029:2029:2029))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[3\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (935:935:935) (901:901:901))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[4\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1103:1103:1103) (1056:1056:1056))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[5\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1103:1103:1103) (1053:1053:1053))
+        (IOPATH i o (2070:2070:2070) (2019:2019:2019))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE \\hex3\[6\]\~output\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1100:1100:1100) (1050:1050:1050))
+        (IOPATH i o (2050:2050:2050) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\button2\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (735:735:735) (896:896:896))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\clk\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (745:745:745) (906:906:906))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\clk\~inputclkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (163:163:163) (145:145:145))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\button1\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|start\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3396:3396:3396) (3721:3721:3721))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|start\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1847:1847:1847) (1883:1883:1883))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[0\]\~18\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (251:251:251) (336:336:336))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1847:1847:1847) (1882:1882:1882))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1159:1159:1159) (1150:1150:1150))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[1\]\~20\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (250:250:250) (336:336:336))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1847:1847:1847) (1882:1882:1882))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1159:1159:1159) (1150:1150:1150))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[2\]\~22\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (251:251:251) (337:337:337))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1186:1186:1186) (1183:1183:1183))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[3\]\~24\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (263:263:263) (346:346:346))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1186:1186:1186) (1183:1183:1183))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[4\]\~26\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (341:341:341))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1186:1186:1186) (1183:1183:1183))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[5\]\~28\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (408:408:408) (479:479:479))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1186:1186:1186) (1183:1183:1183))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[6\]\~30\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (341:341:341))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1186:1186:1186) (1183:1183:1183))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[7\]\~32\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (250:250:250) (334:334:334))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[7\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1847:1847:1847) (1882:1882:1882))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1159:1159:1159) (1150:1150:1150))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[8\]\~34\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (341:341:341))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[8\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (1056:1056:1056) (1092:1092:1092))
+        (PORT ena (1186:1186:1186) (1183:1183:1183))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[9\]\~36\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (261:261:261) (343:343:343))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[9\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[10\]\~38\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (262:262:262) (344:344:344))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[10\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[11\]\~40\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (262:262:262) (344:344:344))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[11\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[12\]\~42\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (343:343:343))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[12\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[13\]\~44\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (251:251:251) (336:336:336))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[13\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[14\]\~46\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (254:254:254) (345:345:345))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[14\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[15\]\~48\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (343:343:343))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[15\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[16\]\~50\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (252:252:252) (338:338:338))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[16\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|ctr\[17\]\~52\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (227:227:227) (299:299:299))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|ctr\[17\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (716:716:716) (737:737:737))
+        (PORT ena (1180:1180:1180) (1174:1174:1174))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (254:254:254) (346:346:346))
+        (PORT datab (251:251:251) (337:337:337))
+        (PORT datac (224:224:224) (305:305:305))
+        (PORT datad (226:226:226) (300:300:300))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (345:345:345))
+        (PORT datac (224:224:224) (305:305:305))
+        (PORT datad (239:239:239) (308:308:308))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (344:344:344))
+        (PORT datab (407:407:407) (476:476:476))
+        (PORT datac (561:561:561) (606:606:606))
+        (PORT datad (556:556:556) (603:603:603))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (409:409:409) (481:481:481))
+        (PORT datab (252:252:252) (338:338:338))
+        (PORT datac (224:224:224) (305:305:305))
+        (PORT datad (226:226:226) (299:299:299))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (201:201:201) (245:245:245))
+        (PORT datab (253:253:253) (339:339:339))
+        (PORT datac (172:172:172) (204:204:204))
+        (PORT datad (173:173:173) (199:199:199))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|LessThan0\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (254:254:254) (345:345:345))
+        (PORT datab (252:252:252) (337:337:337))
+        (PORT datac (314:314:314) (342:342:342))
+        (PORT datad (555:555:555) (567:567:567))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|clock_out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (245:245:245) (332:332:332))
+        (PORT datab (3396:3396:3396) (3721:3721:3721))
+        (PORT datac (1928:1928:1928) (2034:2034:2034))
+        (PORT datad (202:202:202) (229:229:229))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\clockConv\|clock_out\~feeder\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (173:173:173) (199:199:199))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\clockConv\|clock_out\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1847:1847:1847) (1883:1883:1883))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE \\clockConv\|clock_out\~clkctrl\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (780:780:780) (826:826:826))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE \\button0\~input\\)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (725:725:725) (886:886:886))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|en\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT asdata (955:955:955) (962:962:962))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|always0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3629:3629:3629) (3929:3929:3929))
+        (PORT datac (226:226:226) (306:306:306))
+        (PORT datad (3427:3427:3427) (3742:3742:3742))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (248:248:248) (290:290:290))
+        (PORT datad (631:631:631) (639:639:639))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (424:424:424) (506:506:506))
+        (PORT datab (668:668:668) (678:678:678))
+        (PORT datad (224:224:224) (253:253:253))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (309:309:309) (420:420:420))
+        (PORT datab (316:316:316) (407:407:407))
+        (PORT datac (276:276:276) (364:364:364))
+        (PORT datad (297:297:297) (380:380:380))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (342:342:342) (318:318:318))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (421:421:421) (496:496:496))
+        (PORT datac (387:387:387) (448:448:448))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (430:430:430) (457:457:457))
+        (PORT datab (664:664:664) (676:676:676))
+        (PORT datad (348:348:348) (370:370:370))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\[3\]\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3473:3473:3473) (3794:3794:3794))
+        (PORT datab (3629:3629:3629) (3929:3929:3929))
+        (PORT datac (223:223:223) (303:303:303))
+        (PORT datad (633:633:633) (641:641:641))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c0\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (446:446:446) (518:518:518))
+        (PORT datab (387:387:387) (413:413:413))
+        (PORT datad (589:589:589) (593:593:593))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c0\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (454:454:454) (514:514:514))
+        (PORT datab (412:412:412) (477:477:477))
+        (PORT datac (389:389:389) (459:459:459))
+        (PORT datad (414:414:414) (467:467:467))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (220:220:220) (258:258:258))
+        (PORT datac (1696:1696:1696) (1753:1753:1753))
+        (PORT datad (174:174:174) (198:198:198))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (314:314:314) (427:427:427))
+        (PORT datab (317:317:317) (412:412:412))
+        (PORT datac (277:277:277) (368:368:368))
+        (PORT datad (294:294:294) (377:377:377))
+        (IOPATH dataa combout (303:303:303) (299:299:299))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (199:199:199) (237:237:237))
+        (PORT datac (192:192:192) (225:225:225))
+        (PORT datad (1752:1752:1752) (1818:1818:1818))
+        (IOPATH datab combout (306:306:306) (311:311:311))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (313:313:313) (425:425:425))
+        (PORT datab (305:305:305) (402:402:402))
+        (PORT datac (411:411:411) (469:469:469))
+        (PORT datad (294:294:294) (376:376:376))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (260:260:260))
+        (PORT datac (172:172:172) (206:206:206))
+        (PORT datad (1748:1748:1748) (1816:1816:1816))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (311:311:311) (422:422:422))
+        (PORT datab (303:303:303) (399:399:399))
+        (PORT datac (412:412:412) (473:473:473))
+        (PORT datad (287:287:287) (368:368:368))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (260:260:260))
+        (PORT datac (173:173:173) (206:206:206))
+        (PORT datad (1748:1748:1748) (1817:1817:1817))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (311:311:311) (423:423:423))
+        (PORT datab (315:315:315) (411:411:411))
+        (PORT datac (276:276:276) (368:368:368))
+        (PORT datad (296:296:296) (379:379:379))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (219:219:219) (258:258:258))
+        (PORT datac (1684:1684:1684) (1752:1752:1752))
+        (PORT datad (175:175:175) (201:201:201))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (310:310:310) (423:423:423))
+        (PORT datab (322:322:322) (418:418:418))
+        (PORT datac (411:411:411) (469:469:469))
+        (PORT datad (395:395:395) (461:461:461))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (267:267:267))
+        (PORT datac (1696:1696:1696) (1755:1755:1755))
+        (PORT datad (327:327:327) (344:344:344))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (314:314:314) (426:426:426))
+        (PORT datab (318:318:318) (412:412:412))
+        (PORT datac (277:277:277) (369:369:369))
+        (PORT datad (293:293:293) (371:371:371))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss0\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (265:265:265))
+        (PORT datac (171:171:171) (204:204:204))
+        (PORT datad (1751:1751:1751) (1816:1816:1816))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (394:394:394) (433:433:433))
+        (PORT datab (457:457:457) (493:493:493))
+        (PORT datad (658:658:658) (712:712:712))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1036:1036:1036) (987:987:987))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (471:471:471) (540:540:540))
+        (PORT datab (474:474:474) (550:550:550))
+        (PORT datac (642:642:642) (693:693:693))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (399:399:399) (436:436:436))
+        (PORT datac (419:419:419) (454:454:454))
+        (PORT datad (311:311:311) (326:326:326))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1036:1036:1036) (987:987:987))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add2\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (720:720:720) (788:788:788))
+        (PORT datab (467:467:467) (533:533:533))
+        (PORT datac (642:642:642) (692:692:692))
+        (PORT datad (429:429:429) (492:492:492))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (395:395:395) (432:432:432))
+        (PORT datac (423:423:423) (460:460:460))
+        (PORT datad (330:330:330) (347:347:347))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1036:1036:1036) (987:987:987))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (335:335:335) (441:441:441))
+        (PORT datab (317:317:317) (418:418:418))
+        (PORT datac (287:287:287) (383:383:383))
+        (PORT datad (269:269:269) (349:349:349))
+        (IOPATH dataa combout (301:301:301) (299:299:299))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (399:399:399) (436:436:436))
+        (PORT datab (452:452:452) (486:486:486))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c1\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1036:1036:1036) (987:987:987))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (476:476:476) (548:548:548))
+        (PORT datab (311:311:311) (409:409:409))
+        (PORT datac (303:303:303) (398:398:398))
+        (PORT datad (404:404:404) (463:463:463))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1530:1530:1530) (1619:1619:1619))
+        (PORT datac (326:326:326) (348:348:348))
+        (PORT datad (173:173:173) (198:198:198))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (316:316:316) (416:416:416))
+        (PORT datab (316:316:316) (416:416:416))
+        (PORT datac (298:298:298) (393:393:393))
+        (PORT datad (269:269:269) (349:349:349))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (342:342:342) (318:318:318))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1531:1531:1531) (1620:1620:1620))
+        (PORT datac (170:170:170) (203:203:203))
+        (PORT datad (194:194:194) (219:219:219))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (469:469:469) (541:541:541))
+        (PORT datab (457:457:457) (521:521:521))
+        (PORT datac (441:441:441) (516:516:516))
+        (PORT datad (428:428:428) (491:491:491))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1530:1530:1530) (1610:1610:1610))
+        (PORT datac (192:192:192) (225:225:225))
+        (PORT datad (172:172:172) (197:197:197))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (317:317:317) (420:420:420))
+        (PORT datab (313:313:313) (411:411:411))
+        (PORT datac (301:301:301) (397:397:397))
+        (PORT datad (268:268:268) (347:347:347))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1530:1530:1530) (1610:1610:1610))
+        (PORT datac (193:193:193) (226:226:226))
+        (PORT datad (314:314:314) (332:332:332))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (475:475:475) (548:548:548))
+        (PORT datab (311:311:311) (410:410:410))
+        (PORT datac (303:303:303) (399:399:399))
+        (PORT datad (404:404:404) (463:463:463))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1534:1534:1534) (1624:1624:1624))
+        (PORT datac (327:327:327) (349:349:349))
+        (PORT datad (173:173:173) (198:198:198))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (316:316:316) (418:418:418))
+        (PORT datab (311:311:311) (410:410:410))
+        (PORT datac (303:303:303) (398:398:398))
+        (PORT datad (263:263:263) (342:342:342))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1531:1531:1531) (1619:1619:1619))
+        (PORT datac (172:172:172) (205:205:205))
+        (PORT datad (195:195:195) (220:220:220))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (317:317:317) (421:421:421))
+        (PORT datab (313:313:313) (414:414:414))
+        (PORT datac (302:302:302) (399:399:399))
+        (PORT datad (266:266:266) (345:345:345))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss1\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1531:1531:1531) (1624:1624:1624))
+        (PORT datac (172:172:172) (206:206:206))
+        (PORT datad (195:195:195) (221:221:221))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (249:249:249) (306:306:306))
+        (PORT datad (241:241:241) (278:278:278))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (399:399:399) (426:426:426))
+        (PORT datac (612:612:612) (621:621:621))
+        (PORT datad (635:635:635) (643:643:643))
+        (IOPATH datab combout (304:304:304) (311:311:311))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (790:790:790) (783:783:783))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (247:247:247) (303:303:303))
+        (PORT datab (314:314:314) (414:414:414))
+        (PORT datad (237:237:237) (273:273:273))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (790:790:790) (783:783:783))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (309:309:309) (419:419:419))
+        (PORT datab (316:316:316) (412:412:412))
+        (PORT datad (273:273:273) (352:352:352))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~6\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (250:250:250) (308:308:308))
+        (PORT datac (565:565:565) (578:578:578))
+        (PORT datad (243:243:243) (279:279:279))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (790:790:790) (783:783:783))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\[0\]\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (306:306:306) (416:416:416))
+        (PORT datab (316:316:316) (418:418:418))
+        (PORT datac (269:269:269) (358:358:358))
+        (PORT datad (276:276:276) (358:358:358))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (342:342:342) (318:318:318))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add1\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (309:309:309) (419:419:419))
+        (PORT datab (317:317:317) (418:418:418))
+        (PORT datac (270:270:270) (359:359:359))
+        (PORT datad (275:275:275) (357:357:357))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c2\~7\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (249:249:249) (306:306:306))
+        (PORT datab (266:266:266) (314:314:314))
+        (PORT datac (316:316:316) (336:336:336))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c2\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (790:790:790) (783:783:783))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (435:435:435) (511:511:511))
+        (PORT datab (434:434:434) (501:501:501))
+        (PORT datac (405:405:405) (467:467:467))
+        (PORT datad (417:417:417) (479:479:479))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1529:1529:1529) (1605:1605:1605))
+        (PORT datac (193:193:193) (226:226:226))
+        (PORT datad (175:175:175) (200:200:200))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (431:431:431) (515:515:515))
+        (PORT datab (433:433:433) (504:504:504))
+        (PORT datac (404:404:404) (469:469:469))
+        (PORT datad (419:419:419) (482:482:482))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (304:304:304) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1531:1531:1531) (1606:1606:1606))
+        (PORT datac (192:192:192) (225:225:225))
+        (PORT datad (173:173:173) (199:199:199))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (432:432:432) (515:515:515))
+        (PORT datab (434:434:434) (504:504:504))
+        (PORT datac (405:405:405) (468:468:468))
+        (PORT datad (418:418:418) (478:478:478))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1529:1529:1529) (1606:1606:1606))
+        (PORT datac (192:192:192) (225:225:225))
+        (PORT datad (174:174:174) (201:201:201))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (432:432:432) (510:510:510))
+        (PORT datab (429:429:429) (498:498:498))
+        (PORT datac (404:404:404) (467:467:467))
+        (PORT datad (422:422:422) (480:480:480))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1530:1530:1530) (1606:1606:1606))
+        (PORT datac (192:192:192) (225:225:225))
+        (PORT datad (175:175:175) (201:201:201))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (301:301:301) (409:409:409))
+        (PORT datab (311:311:311) (410:410:410))
+        (PORT datac (265:265:265) (352:352:352))
+        (PORT datad (271:271:271) (353:353:353))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1474:1474:1474) (1564:1564:1564))
+        (PORT datac (171:171:171) (203:203:203))
+        (PORT datad (194:194:194) (219:219:219))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (308:308:308) (418:418:418))
+        (PORT datab (315:315:315) (410:410:410))
+        (PORT datac (268:268:268) (357:357:357))
+        (PORT datad (273:273:273) (351:351:351))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1471:1471:1471) (1560:1560:1560))
+        (PORT datac (171:171:171) (204:204:204))
+        (PORT datad (195:195:195) (220:220:220))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (302:302:302) (410:410:410))
+        (PORT datab (311:311:311) (410:410:410))
+        (PORT datac (266:266:266) (352:352:352))
+        (PORT datad (272:272:272) (353:353:353))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss2\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1471:1471:1471) (1565:1565:1565))
+        (PORT datac (172:172:172) (206:206:206))
+        (PORT datad (196:196:196) (221:221:221))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (485:485:485) (558:558:558))
+        (PORT datac (432:432:432) (504:504:504))
+        (PORT datad (405:405:405) (472:472:472))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~4\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (670:670:670) (683:683:683))
+        (PORT datac (172:172:172) (205:205:205))
+        (PORT datad (196:196:196) (220:220:220))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\[1\]\~2\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (654:654:654) (682:682:682))
+        (PORT datab (605:605:605) (623:623:623))
+        (PORT datac (394:394:394) (421:421:421))
+        (PORT datad (566:566:566) (571:571:571))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT asdata (655:655:655) (670:670:670))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\[1\]\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (482:482:482) (562:562:562))
+        (PORT datab (432:432:432) (515:515:515))
+        (PORT datac (432:432:432) (505:505:505))
+        (PORT datad (419:419:419) (489:489:489))
+        (IOPATH dataa combout (304:304:304) (299:299:299))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (661:661:661) (690:690:690))
+        (PORT datad (365:365:365) (382:382:382))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~3\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (656:656:656) (683:683:683))
+        (PORT datab (318:318:318) (418:418:418))
+        (PORT datad (366:366:366) (387:387:387))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (304:304:304) (308:308:308))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|Add0\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (479:479:479) (556:556:556))
+        (PORT datab (432:432:432) (509:509:509))
+        (PORT datac (435:435:435) (508:508:508))
+        (PORT datad (417:417:417) (485:485:485))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (333:333:333) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\timeCount\|c3\~5\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (369:369:369) (390:390:390))
+        (PORT datac (623:623:623) (644:644:644))
+        (PORT datad (365:365:365) (387:387:387))
+        (IOPATH datab combout (304:304:304) (311:311:311))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE \\timeCount\|c3\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1489:1489:1489))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (303:303:303) (404:404:404))
+        (PORT datab (300:300:300) (395:395:395))
+        (PORT datac (270:270:270) (367:367:367))
+        (PORT datad (287:287:287) (374:374:374))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[0\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (200:200:200) (240:240:240))
+        (PORT datac (1691:1691:1691) (1757:1757:1757))
+        (PORT datad (196:196:196) (221:221:221))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\~1\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (309:309:309) (416:416:416))
+        (PORT datab (304:304:304) (401:401:401))
+        (PORT datac (278:278:278) (371:371:371))
+        (PORT datad (279:279:279) (365:365:365))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[1\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (615:615:615) (634:634:634))
+        (PORT datab (200:200:200) (240:240:240))
+        (PORT datad (1710:1710:1710) (1789:1789:1789))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (306:306:306) (311:311:311))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr4\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (480:480:480) (559:559:559))
+        (PORT datab (454:454:454) (527:527:527))
+        (PORT datac (431:431:431) (504:504:504))
+        (PORT datad (403:403:403) (473:473:473))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[2\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (220:220:220) (260:260:260))
+        (PORT datac (1696:1696:1696) (1758:1758:1758))
+        (PORT datad (174:174:174) (200:200:200))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr3\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (305:305:305) (413:413:413))
+        (PORT datab (307:307:307) (406:406:406))
+        (PORT datac (274:274:274) (366:366:366))
+        (PORT datad (274:274:274) (355:355:355))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[3\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (260:260:260))
+        (PORT datac (173:173:173) (207:207:207))
+        (PORT datad (1711:1711:1711) (1791:1791:1791))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr2\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (302:302:302) (408:408:408))
+        (PORT datab (314:314:314) (414:414:414))
+        (PORT datac (271:271:271) (364:364:364))
+        (PORT datad (273:273:273) (355:355:355))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[4\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (220:220:220) (260:260:260))
+        (PORT datac (172:172:172) (205:205:205))
+        (PORT datad (1710:1710:1710) (1790:1790:1790))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr1\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (304:304:304) (415:415:415))
+        (PORT datab (307:307:307) (406:406:406))
+        (PORT datac (273:273:273) (366:366:366))
+        (PORT datad (273:273:273) (356:356:356))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[5\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (266:266:266))
+        (PORT datac (171:171:171) (205:205:205))
+        (PORT datad (1710:1710:1710) (1790:1790:1790))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|WideOr0\~0\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (305:305:305) (414:414:414))
+        (PORT datab (302:302:302) (398:398:398))
+        (PORT datac (275:275:275) (367:367:367))
+        (PORT datad (283:283:283) (370:370:370))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE \\dss3\|out\[6\]\\)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (221:221:221) (264:264:264))
+        (PORT datac (172:172:172) (203:203:203))
+        (PORT datad (1710:1710:1710) (1786:1786:1786))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+)
diff --git a/stopClockVerilog/stopClockBlock.bdf b/stopClockVerilog/stopClockBlock.bdf
new file mode 100644
index 0000000..50e8bff
--- /dev/null
+++ b/stopClockVerilog/stopClockBlock.bdf
@@ -0,0 +1,236 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 512 152 680 168)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLK" (rect 5 0 27 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 512 168 680 184)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "BUTTON0" (rect 5 0 55 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 512 184 680 200)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "BUTTON1" (rect 5 0 55 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 520 200 688 216)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "BUTTON2" (rect 5 0 55 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(output)
+	(rect 864 152 1040 168)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HEX0[6..0]" (rect 90 0 143 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 864 168 1040 184)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HEX1[6..0]" (rect 90 0 143 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 864 184 1040 200)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HEX2[6..0]" (rect 90 0 143 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 864 200 1040 216)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HEX3[6..0]" (rect 90 0 143 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 864 216 1040 232)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DECP" (rect 90 0 120 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(symbol
+	(rect 680 128 864 272)
+	(text "stopclock" (rect 5 0 52 12)(font "Arial" ))
+	(text "inst" (rect 8 128 25 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 27 35 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "button0" (rect 0 0 36 12)(font "Arial" ))
+		(text "button0" (rect 21 43 57 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "button1" (rect 0 0 36 12)(font "Arial" ))
+		(text "button1" (rect 21 59 57 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "button2" (rect 0 0 36 12)(font "Arial" ))
+		(text "button2" (rect 21 75 57 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 184 32)
+		(output)
+		(text "hex0[6..0]" (rect 0 0 49 12)(font "Arial" ))
+		(text "hex0[6..0]" (rect 122 27 171 39)(font "Arial" ))
+		(line (pt 184 32)(pt 168 32)(line_width 3))
+	)
+	(port
+		(pt 184 48)
+		(output)
+		(text "hex1[6..0]" (rect 0 0 49 12)(font "Arial" ))
+		(text "hex1[6..0]" (rect 122 43 171 55)(font "Arial" ))
+		(line (pt 184 48)(pt 168 48)(line_width 3))
+	)
+	(port
+		(pt 184 64)
+		(output)
+		(text "hex2[6..0]" (rect 0 0 49 12)(font "Arial" ))
+		(text "hex2[6..0]" (rect 122 59 171 71)(font "Arial" ))
+		(line (pt 184 64)(pt 168 64)(line_width 3))
+	)
+	(port
+		(pt 184 80)
+		(output)
+		(text "hex3[6..0]" (rect 0 0 49 12)(font "Arial" ))
+		(text "hex3[6..0]" (rect 122 75 171 87)(font "Arial" ))
+		(line (pt 184 80)(pt 168 80)(line_width 3))
+	)
+	(port
+		(pt 184 96)
+		(output)
+		(text "decimal_point" (rect 0 0 67 12)(font "Arial" ))
+		(text "decimal_point" (rect 107 91 174 103)(font "Arial" ))
+		(line (pt 184 96)(pt 168 96))
+	)
+	(drawing
+		(rectangle (rect 16 16 168 128))
+	)
+)
diff --git a/stopClockVerilog/stopclock.bsf b/stopClockVerilog/stopclock.bsf
new file mode 100644
index 0000000..612c07c
--- /dev/null
+++ b/stopClockVerilog/stopclock.bsf
@@ -0,0 +1,92 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 200 160)
+	(text "stopclock" (rect 5 0 41 12)(font "Arial" ))
+	(text "inst" (rect 8 128 20 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "button0" (rect 0 0 28 12)(font "Arial" ))
+		(text "button0" (rect 21 43 49 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "button1" (rect 0 0 27 12)(font "Arial" ))
+		(text "button1" (rect 21 59 48 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "button2" (rect 0 0 28 12)(font "Arial" ))
+		(text "button2" (rect 21 75 49 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 184 32)
+		(output)
+		(text "hex0[6..0]" (rect 0 0 38 12)(font "Arial" ))
+		(text "hex0[6..0]" (rect 125 27 163 39)(font "Arial" ))
+		(line (pt 184 32)(pt 168 32)(line_width 3))
+	)
+	(port
+		(pt 184 48)
+		(output)
+		(text "hex1[6..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "hex1[6..0]" (rect 126 43 163 55)(font "Arial" ))
+		(line (pt 184 48)(pt 168 48)(line_width 3))
+	)
+	(port
+		(pt 184 64)
+		(output)
+		(text "hex2[6..0]" (rect 0 0 38 12)(font "Arial" ))
+		(text "hex2[6..0]" (rect 125 59 163 71)(font "Arial" ))
+		(line (pt 184 64)(pt 168 64)(line_width 3))
+	)
+	(port
+		(pt 184 80)
+		(output)
+		(text "hex3[6..0]" (rect 0 0 38 12)(font "Arial" ))
+		(text "hex3[6..0]" (rect 125 75 163 87)(font "Arial" ))
+		(line (pt 184 80)(pt 168 80)(line_width 3))
+	)
+	(port
+		(pt 184 96)
+		(output)
+		(text "decimal_point" (rect 0 0 53 12)(font "Arial" ))
+		(text "decimal_point" (rect 110 91 163 103)(font "Arial" ))
+		(line (pt 184 96)(pt 168 96)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 168 128)(line_width 1))
+	)
+)
diff --git a/stopClockVerilog/stopclock.qpf b/stopClockVerilog/stopclock.qpf
new file mode 100644
index 0000000..ac235cd
--- /dev/null
+++ b/stopClockVerilog/stopclock.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 15:17:01  March 02, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "15:17:01  March 02, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "stopclock"
diff --git a/stopClockVerilog/stopclock.qsf b/stopClockVerilog/stopclock.qsf
new file mode 100644
index 0000000..52b3672
--- /dev/null
+++ b/stopClockVerilog/stopclock.qsf
@@ -0,0 +1,92 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 15:17:01  March 02, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		stopclock_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16U484C6
+set_global_assignment -name TOP_LEVEL_ENTITY stopclock
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:17:01  MARCH 02, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name VERILOG_FILE stopclock.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name BDF_FILE stopClock.bdf
+set_global_assignment -name BDF_FILE stopClockBlock.bdf
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_H2 -to button0
+set_location_assignment PIN_G3 -to button1
+set_location_assignment PIN_F1 -to button2
+set_location_assignment PIN_G21 -to clk
+set_location_assignment PIN_A18 -to decimal_point
+set_location_assignment PIN_E11 -to hex0[0]
+set_location_assignment PIN_F11 -to hex0[1]
+set_location_assignment PIN_H12 -to hex0[2]
+set_location_assignment PIN_H13 -to hex0[3]
+set_location_assignment PIN_G12 -to hex0[4]
+set_location_assignment PIN_F12 -to hex0[5]
+set_location_assignment PIN_F13 -to hex0[6]
+set_location_assignment PIN_A13 -to hex1[0]
+set_location_assignment PIN_B13 -to hex1[1]
+set_location_assignment PIN_C13 -to hex1[2]
+set_location_assignment PIN_A14 -to hex1[3]
+set_location_assignment PIN_B14 -to hex1[4]
+set_location_assignment PIN_E14 -to hex1[5]
+set_location_assignment PIN_A15 -to hex1[6]
+set_location_assignment PIN_D15 -to hex2[0]
+set_location_assignment PIN_A16 -to hex2[1]
+set_location_assignment PIN_B16 -to hex2[2]
+set_location_assignment PIN_E15 -to hex2[3]
+set_location_assignment PIN_A17 -to hex2[4]
+set_location_assignment PIN_B17 -to hex2[5]
+set_location_assignment PIN_F14 -to hex2[6]
+set_location_assignment PIN_B18 -to hex3[0]
+set_location_assignment PIN_F15 -to hex3[1]
+set_location_assignment PIN_A19 -to hex3[2]
+set_location_assignment PIN_B19 -to hex3[3]
+set_location_assignment PIN_C19 -to hex3[4]
+set_location_assignment PIN_D19 -to hex3[5]
+set_location_assignment PIN_G15 -to hex3[6]
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/stopClockVerilog/stopclock.qws b/stopClockVerilog/stopclock.qws
new file mode 100644
index 0000000..5182105
--- /dev/null
+++ b/stopClockVerilog/stopclock.qws
diff --git a/stopClockVerilog/stopclock.v b/stopClockVerilog/stopclock.v
new file mode 100644
index 0000000..a2b4249
--- /dev/null
+++ b/stopClockVerilog/stopclock.v
@@ -0,0 +1,140 @@
+module hundred_hertz_clock(clock_in, b1, clock_out);
+	input clock_in;
+	input b1;
+	reg start;
+	output reg clock_out;
+	
+	initial start = 1'b0;
+	reg [17:0] ctr;
+	//1 hertz clock generator]
+	
+	always @ (posedge clock_in)
+		begin
+			if (b1 == 0)
+				start = 1;
+			if (start == 1)
+				begin
+					if (ctr < 18'd249999)
+						begin
+							ctr <= ctr + 18'b1;
+						end
+					else
+						begin
+							ctr <= 18'b0;
+							clock_out <= ~clock_out;
+						end
+				end
+		end
+endmodule
+
+
+module counter(clock, b0, b1, c0, c1, c2, c3);
+	input clock;
+	input b0, b1;
+	reg en;
+	
+	initial en = 1'b1;
+	
+	output reg [3:0] c0, c1, c2, c3;
+	
+	always @ (posedge clock)
+		begin
+			if (b1 == 0)
+				en = 1'b1;
+			if (b0 & en)
+				begin
+					if (c0 == 4'd9)
+						begin
+							c0 <= 0;
+							if (c1 == 4'd9)
+								begin
+									c1 <= 0;
+									if (c2 == 4'd9)
+										begin
+											c2 <= 0;
+											if (c3 == 4'd9)
+												c3 <= 0;
+											else
+												c3 <= c3 + 4'b1;
+										end
+									else
+										c2 <= c2 + 4'b1;
+								end
+							else
+								c1 <= c1 + 4'b1;
+						end
+					else
+						c0 <= c0 + 4'b1;
+				end
+			else	
+				begin
+					en <= 1'b0;
+					c0 <= 1'b0;
+					c1 <= 1'b0;
+					c2 <= 1'b0;
+					c3 <= 1'b0;
+				end
+		end
+endmodule
+
+module dec_to_seven_segment (in, b2, out);
+	output [6:0] out; //in this program we are using active low
+	input [3:0] in;
+	input b2;
+
+	reg [6:0] out; //make out a variable
+
+	always @ (in, b2)
+		begin
+			if (b2)
+				begin
+					case (in)
+						/*
+						--0--
+						|	 |
+						5	 1
+						|	 |
+						--6--
+						|   |
+						4	 2
+						|   |
+						--3--
+
+						*/
+						//<size>'<base><value>
+						//NB: output is [6:0] (not [0:6])
+						4'h0: out = 7'b1000000;
+						4'h1: out = 7'b1111001;
+						4'h2: out = 7'b0100100;
+						4'h3: out = 7'b0110000;
+						4'h4: out = 7'b0011001;
+						4'h5: out = 7'b0010010;
+						4'h6: out = 7'b0000010;
+						4'h7: out = 7'b1111000;
+						4'h8: out = 7'b0000000;
+						4'h9: out = 7'b0010000;
+						default: out = 7'b0000100;
+					endcase
+				end
+		end
+endmodule
+
+module stopclock (clk, button0, button1, button2, hex0, hex1, hex2, hex3, decimal_point);
+	input clk, button0, button1, button2;
+	output decimal_point;
+	output [6:0] hex0, hex1, hex2, hex3;
+
+	wire clk, button0, button1, button2;
+	wire [3:0] count0, count1, count2, count3;
+	wire [6:0] hex0, hex1, hex2, hex3;
+	wire one_hertz_clock;
+
+	assign decimal_point = 1'b0;
+	hundred_hertz_clock clockConv (.clock_in(clk), .b1(button1), .clock_out(one_hertz_clock));
+	counter timeCount (.clock(one_hertz_clock), .b0(button0), .b1(button1), .c0(count0), .c1(count1), .c2(count2), .c3(count3));
+	dec_to_seven_segment dss0 (.in(count0), .b2(button2), .out(hex0));
+	dec_to_seven_segment dss1 (.in(count1), .b2(button2), .out(hex1));
+	dec_to_seven_segment dss2 (.in(count2), .b2(button2), .out(hex2));
+	dec_to_seven_segment dss3 (.in(count3), .b2(button2), .out(hex3));
+
+endmodule
\ No newline at end of file