diff options
Diffstat (limited to 'stopClockVerilog/db/prev_cmp_stopclock.qmsg')
| -rw-r--r-- | stopClockVerilog/db/prev_cmp_stopclock.qmsg | 146 |
1 files changed, 146 insertions, 0 deletions
diff --git a/stopClockVerilog/db/prev_cmp_stopclock.qmsg b/stopClockVerilog/db/prev_cmp_stopclock.qmsg new file mode 100644 index 0000000..5d97003 --- /dev/null +++ b/stopClockVerilog/db/prev_cmp_stopclock.qmsg @@ -0,0 +1,146 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456932057549 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932057549 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:20:57 2016 " "Processing started: Wed Mar 02 15:20:57 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932057549 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456932057549 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off stopclock -c stopclock " "Command: quartus_map --read_settings_files=on --write_settings_files=off stopclock -c stopclock" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456932057549 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1456932057960 ""} +{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "stopclock.v(11) " "Verilog HDL information at stopclock.v(11): always construct contains both blocking and non-blocking assignments" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 11 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1456932058014 ""} +{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "stopclock.v(40) " "Verilog HDL information at stopclock.v(40): always construct contains both blocking and non-blocking assignments" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 40 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1456932058015 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stopclock.v 4 4 " "Found 4 design units, including 4 entities, in source file stopclock.v" { { "Info" "ISGN_ENTITY_NAME" "1 hundred_hertz_clock " "Found entity 1: hundred_hertz_clock" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932058016 ""} { "Info" "ISGN_ENTITY_NAME" "2 counter " "Found entity 2: counter" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932058016 ""} { "Info" "ISGN_ENTITY_NAME" "3 dec_to_seven_segment " "Found entity 3: dec_to_seven_segment" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 80 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932058016 ""} { "Info" "ISGN_ENTITY_NAME" "4 stopclock " "Found entity 4: stopclock" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 122 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932058016 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456932058016 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "stopClock.bdf " "Can't analyze file -- file stopClock.bdf is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1456932058025 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stopclockblock.bdf 1 1 " "Found 1 design units, including 1 entities, in source file stopclockblock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 stopClockBlock " "Found entity 1: stopClockBlock" { } { { "stopClockBlock.bdf" "" { Schematic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopClockBlock.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456932058028 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456932058028 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "stopclock " "Elaborating entity \"stopclock\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456932058073 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hundred_hertz_clock hundred_hertz_clock:clockConv " "Elaborating entity \"hundred_hertz_clock\" for hierarchy \"hundred_hertz_clock:clockConv\"" { } { { "stopclock.v" "clockConv" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 133 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456932058076 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:timeCount " "Elaborating entity \"counter\" for hierarchy \"counter:timeCount\"" { } { { "stopclock.v" "timeCount" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456932058078 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dec_to_seven_segment dec_to_seven_segment:dss0 " "Elaborating entity \"dec_to_seven_segment\" for hierarchy \"dec_to_seven_segment:dss0\"" { } { { "stopclock.v" "dss0" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456932058080 ""} +{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "out stopclock.v(87) " "Verilog HDL Always Construct warning at stopclock.v(87): inferring latch(es) for variable \"out\", which holds its previous value in one or more paths through the always construct" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 87 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[0\] stopclock.v(89) " "Inferred latch for \"out\[0\]\" at stopclock.v(89)" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[1\] stopclock.v(89) " "Inferred latch for \"out\[1\]\" at stopclock.v(89)" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[2\] stopclock.v(89) " "Inferred latch for \"out\[2\]\" at stopclock.v(89)" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[3\] stopclock.v(89) " "Inferred latch for \"out\[3\]\" at stopclock.v(89)" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[4\] stopclock.v(89) " "Inferred latch for \"out\[4\]\" at stopclock.v(89)" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[5\] stopclock.v(89) " "Inferred latch for \"out\[5\]\" at stopclock.v(89)" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "out\[6\] stopclock.v(89) " "Inferred latch for \"out\[6\]\" at stopclock.v(89)" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 89 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456932058081 "|stopclock|dec_to_seven_segment:dss0"} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "decimal_point GND " "Pin \"decimal_point\" is stuck at GND" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 124 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456932058587 "|stopclock|decimal_point"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1456932058587 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1456932058723 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.map.smsg " "Generated suppressed messages file C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1456932058926 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1456932059026 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456932059026 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "148 " "Implemented 148 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1456932059101 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1456932059101 ""} { "Info" "ICUT_CUT_TM_LCELLS" "115 " "Implemented 115 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1456932059101 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1456932059101 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "506 " "Peak virtual memory: 506 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932059125 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:20:59 2016 " "Processing ended: Wed Mar 02 15:20:59 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932059125 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932059125 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932059125 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456932059125 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456932061249 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932061251 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:21:00 2016 " "Processing started: Wed Mar 02 15:21:00 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932061251 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1456932061251 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off stopclock -c stopclock " "Command: quartus_fit --read_settings_files=off --write_settings_files=off stopclock -c stopclock" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1456932061251 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1456932061367 ""} +{ "Info" "0" "" "Project = stopclock" { } { } 0 0 "Project = stopclock" 0 0 "Fitter" 0 0 1456932061367 ""} +{ "Info" "0" "" "Revision = stopclock" { } { } 0 0 "Revision = stopclock" 0 0 "Fitter" 0 0 1456932061368 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1456932061432 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "stopclock EP3C16U484C6 " "Selected device EP3C16U484C6 for design \"stopclock\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1456932061439 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456932061494 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456932061495 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456932061495 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1456932061585 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1456932061599 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40U484C6 " "Device EP3C40U484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456932061894 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55U484C6 " "Device EP3C55U484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456932061894 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80U484C6 " "Device EP3C80U484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456932061894 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1456932061894 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 287 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932061896 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 289 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932061896 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 291 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932061896 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 293 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932061896 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 295 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456932061896 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1456932061896 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1456932061897 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "33 33 " "No exact pin location assignment(s) for 33 pins of 33 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[0\] " "Pin hex0\[0\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[0] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 13 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[1\] " "Pin hex0\[1\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[1] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 14 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[2\] " "Pin hex0\[2\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[2] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 15 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[3\] " "Pin hex0\[3\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[3] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 16 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[4\] " "Pin hex0\[4\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[4] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 17 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[5\] " "Pin hex0\[5\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[5] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 18 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex0\[6\] " "Pin hex0\[6\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex0[6] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex0[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 19 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[0\] " "Pin hex1\[0\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[0] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 20 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[1\] " "Pin hex1\[1\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[1] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 21 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[2\] " "Pin hex1\[2\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[2] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 22 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[3\] " "Pin hex1\[3\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[3] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 23 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[4\] " "Pin hex1\[4\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[4] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 24 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[5\] " "Pin hex1\[5\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[5] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 25 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex1\[6\] " "Pin hex1\[6\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex1[6] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 26 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[0\] " "Pin hex2\[0\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[0] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 27 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[1\] " "Pin hex2\[1\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[1] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 28 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[2\] " "Pin hex2\[2\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[2] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 29 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[3\] " "Pin hex2\[3\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[3] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 30 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[4\] " "Pin hex2\[4\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[4] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 31 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[5\] " "Pin hex2\[5\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[5] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 32 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex2\[6\] " "Pin hex2\[6\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex2[6] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex2[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 33 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[0\] " "Pin hex3\[0\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[0] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 34 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[1\] " "Pin hex3\[1\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[1] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 35 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[2\] " "Pin hex3\[2\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[2] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 36 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[3\] " "Pin hex3\[3\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[3] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 37 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[4\] " "Pin hex3\[4\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[4] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 38 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[5\] " "Pin hex3\[5\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[5] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 39 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hex3\[6\] " "Pin hex3\[6\] not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { hex3[6] } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 125 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hex3[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 40 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "decimal_point " "Pin decimal_point not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { decimal_point } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 124 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { decimal_point } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 45 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "button2 " "Pin button2 not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { button2 } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { button2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 44 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "button0 " "Pin button0 not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { button0 } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { button0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 42 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "button1 " "Pin button1 not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { button1 } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { button1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 43 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Pin clk not assigned to an exact location on the device" { } { { "c:/program files/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/program files/quartus/bin64/pin_planner.ppl" { clk } } } { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 41 9662 10382 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456932062894 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1456932062894 ""} +{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "28 " "TimeQuest Timing Analyzer is analyzing 28 combinational loops as latches." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Fitter" 0 -1 1456932063063 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "stopclock.sdc " "Synopsys Design Constraints File file not found: 'stopclock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1456932063063 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1456932063064 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1456932063066 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1456932063067 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1456932063067 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "button2~input (placed in PIN G2 (CLK0, DIFFCLK_0p)) " "Automatically promoted node button2~input (placed in PIN G2 (CLK0, DIFFCLK_0p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456932063092 ""} } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { button2~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 279 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456932063092 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN G1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk~input (placed in PIN G1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456932063092 ""} } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 123 0 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 282 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456932063092 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "hundred_hertz_clock:clockConv\|clock_out " "Automatically promoted node hundred_hertz_clock:clockConv\|clock_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456932063092 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "hundred_hertz_clock:clockConv\|clock_out~0 " "Destination node hundred_hertz_clock:clockConv\|clock_out~0" { } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 5 -1 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hundred_hertz_clock:clockConv|clock_out~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 211 9662 10382 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456932063092 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1456932063092 ""} } { { "stopclock.v" "" { Text "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/stopclock.v" 5 -1 0 } } { "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/program files/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hundred_hertz_clock:clockConv|clock_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 0 { 0 ""} 0 104 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456932063092 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1456932063273 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456932063274 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456932063274 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456932063275 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456932063275 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1456932063275 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1456932063276 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1456932063276 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1456932063276 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1456932063276 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1456932063276 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "31 unused 2.5V 2 29 0 " "Number of I/O pins in group: 31 (unused VREF, 2.5V VCCIO, 2 input, 29 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1456932063279 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1456932063279 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1456932063279 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 6 27 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 6 total pin(s) used -- 27 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 47 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1456932063280 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1456932063280 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1456932063280 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932063305 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1456932064388 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932064479 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1456932064486 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1456932065575 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932065575 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1456932065803 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X21_Y20 X30_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29" { } { { "loc" "" { Generic "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29"} 21 20 10 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1456932066472 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1456932066472 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932067565 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1456932067565 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1456932067565 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.33 " "Total time spent on timing analysis during the Fitter is 0.33 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1456932067575 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456932067612 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456932067940 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456932067972 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456932068134 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456932068561 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.fit.smsg " "Generated suppressed messages file C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/output_files/stopclock.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1456932069645 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "846 " "Peak virtual memory: 846 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932069911 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:21:09 2016 " "Processing ended: Wed Mar 02 15:21:09 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932069911 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932069911 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932069911 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1456932069911 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1456932071867 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932071867 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:21:11 2016 " "Processing started: Wed Mar 02 15:21:11 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932071867 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1456932071867 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off stopclock -c stopclock " "Command: quartus_asm --read_settings_files=off --write_settings_files=off stopclock -c stopclock" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1456932071868 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1456932072765 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1456932072797 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "465 " "Peak virtual memory: 465 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932073227 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:21:13 2016 " "Processing ended: Wed Mar 02 15:21:13 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932073227 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932073227 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932073227 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1456932073227 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1456932073848 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1456932075398 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932075399 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:21:14 2016 " "Processing started: Wed Mar 02 15:21:14 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932075399 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456932075399 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta stopclock -c stopclock " "Command: quartus_sta stopclock -c stopclock" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456932075399 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1456932075595 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1456932075922 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456932075922 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456932076029 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456932076029 ""} +{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "28 " "TimeQuest Timing Analyzer is analyzing 28 combinational loops as latches." { } { } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches." 0 0 "Quartus II" 0 -1 1456932076264 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "stopclock.sdc " "Synopsys Design Constraints File file not found: 'stopclock.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1456932076356 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456932076359 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076361 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name hundred_hertz_clock:clockConv\|clock_out hundred_hertz_clock:clockConv\|clock_out " "create_clock -period 1.000 -name hundred_hertz_clock:clockConv\|clock_out hundred_hertz_clock:clockConv\|clock_out" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076361 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name button2 button2 " "create_clock -period 1.000 -name button2 button2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076361 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076361 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1456932076529 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076530 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1456932076531 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1456932076548 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456932076567 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456932076567 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.274 " "Worst-case setup slack is -2.274" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076576 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076576 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.274 -38.401 clk " " -2.274 -38.401 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076576 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.840 -24.288 hundred_hertz_clock:clockConv\|clock_out " " -1.840 -24.288 hundred_hertz_clock:clockConv\|clock_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076576 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.700 -41.655 button2 " " -1.700 -41.655 button2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076576 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932076576 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.515 " "Worst-case hold slack is -0.515" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076581 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076581 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.515 -0.515 clk " " -0.515 -0.515 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076581 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.359 0.000 hundred_hertz_clock:clockConv\|clock_out " " 0.359 0.000 hundred_hertz_clock:clockConv\|clock_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076581 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.753 0.000 button2 " " 0.753 0.000 button2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076581 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932076581 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932076591 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932076595 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -23.000 clk " " -3.000 -23.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 button2 " " -3.000 -3.000 button2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -17.000 hundred_hertz_clock:clockConv\|clock_out " " -1.000 -17.000 hundred_hertz_clock:clockConv\|clock_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932076599 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932076599 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456932076759 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1456932076782 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1456932077260 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077314 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456932077328 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456932077328 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.965 " "Worst-case setup slack is -1.965" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077333 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077333 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.965 -33.022 clk " " -1.965 -33.022 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077333 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.582 -20.441 hundred_hertz_clock:clockConv\|clock_out " " -1.582 -20.441 hundred_hertz_clock:clockConv\|clock_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077333 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.392 -33.987 button2 " " -1.392 -33.987 button2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077333 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932077333 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.478 " "Worst-case hold slack is -0.478" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.478 -0.478 clk " " -0.478 -0.478 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.313 0.000 hundred_hertz_clock:clockConv\|clock_out " " 0.313 0.000 hundred_hertz_clock:clockConv\|clock_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.665 0.000 button2 " " 0.665 0.000 button2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077343 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932077343 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932077350 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932077356 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077362 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077362 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -23.000 clk " " -3.000 -23.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077362 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 button2 " " -3.000 -3.000 button2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077362 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -17.000 hundred_hertz_clock:clockConv\|clock_out " " -1.000 -17.000 hundred_hertz_clock:clockConv\|clock_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077362 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932077362 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456932077489 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077683 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456932077684 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456932077684 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.818 " "Worst-case setup slack is -0.818" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077700 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077700 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.818 -12.743 clk " " -0.818 -12.743 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077700 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.554 -6.490 hundred_hertz_clock:clockConv\|clock_out " " -0.554 -6.490 hundred_hertz_clock:clockConv\|clock_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077700 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.441 -8.576 button2 " " -0.441 -8.576 button2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077700 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932077700 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.331 " "Worst-case hold slack is -0.331" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.331 -0.331 clk " " -0.331 -0.331 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.188 0.000 hundred_hertz_clock:clockConv\|clock_out " " 0.188 0.000 hundred_hertz_clock:clockConv\|clock_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.311 0.000 button2 " " 0.311 0.000 button2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077722 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932077722 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932077742 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456932077759 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077769 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077769 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -24.282 clk " " -3.000 -24.282 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077769 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 button2 " " -3.000 -3.000 button2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077769 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -17.000 hundred_hertz_clock:clockConv\|clock_out " " -1.000 -17.000 hundred_hertz_clock:clockConv\|clock_out " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456932077769 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456932077769 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456932078126 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456932078127 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "505 " "Peak virtual memory: 505 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932078265 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:21:18 2016 " "Processing ended: Wed Mar 02 15:21:18 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932078265 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932078265 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932078265 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456932078265 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456932080290 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456932080290 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 02 15:21:20 2016 " "Processing started: Wed Mar 02 15:21:20 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456932080290 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456932080290 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off stopclock -c stopclock " "Command: quartus_eda --read_settings_files=off --write_settings_files=off stopclock -c stopclock" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456932080291 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_6_1200mv_85c_slow.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_6_1200mv_85c_slow.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932080888 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_6_1200mv_0c_slow.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_6_1200mv_0c_slow.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932080948 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_min_1200mv_0c_fast.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_min_1200mv_0c_fast.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932080991 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock.vho C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock.vho in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932081043 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_6_1200mv_85c_vhd_slow.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_6_1200mv_85c_vhd_slow.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932081079 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_6_1200mv_0c_vhd_slow.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_6_1200mv_0c_vhd_slow.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932081124 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_min_1200mv_0c_vhd_fast.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_min_1200mv_0c_vhd_fast.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932081166 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "stopclock_vhd.sdo C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/ simulation " "Generated file stopclock_vhd.sdo in folder \"C:/Users/Asus/OneDrive - Imperial College London/Documents/Verilog/stopclockVerilog/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1456932081204 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "431 " "Peak virtual memory: 431 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456932081278 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 02 15:21:21 2016 " "Processing ended: Wed Mar 02 15:21:21 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456932081278 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456932081278 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456932081278 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456932081278 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 17 s " "Quartus II Full Compilation was successful. 0 errors, 17 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456932081898 ""} |