| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | counter.bsf | 2460 | logstatsplain |
| d--------- | db | 3298 | logstatsplain |
| -rw-r--r-- | dec_to_seven_segment.bsf | 1745 | logstatsplain |
| -rw-r--r-- | hundred_hertz_clock.bsf | 1743 | logstatsplain |
| d--------- | incremental_db | 80 | logstatsplain |
| d--------- | output_files | 716 | logstatsplain |
| d--------- | simulation / modelsim | 35 | logstatsplain |
| -rw-r--r-- | stopClockBlock.bdf | 6380 | logstatsplain |
| -rw-r--r-- | stopclock.bsf | 2877 | logstatsplain |
| -rw-r--r-- | stopclock.qpf | 1245 | logstatsplain |
| -rw-r--r-- | stopclock.qsf | 4392 | logstatsplain |
| -rw-r--r-- | stopclock.qws | 2508 | logstatsplain |
| -rw-r--r-- | stopclock.v | 2911 | logstatsplain |
 |
index : FPGA-2015 | |
| A collection of Quartus projects to learn FPGA design. |
| aboutsummaryrefslogtreecommitdiffstats |
path: root/stopClockVerilog