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Diffstat (limited to 'dot_product/dot_product/dot_product/dot_product.v10/rtl.rpt')
| -rw-r--r-- | dot_product/dot_product/dot_product/dot_product.v10/rtl.rpt | 291 |
1 files changed, 291 insertions, 0 deletions
diff --git a/dot_product/dot_product/dot_product/dot_product.v10/rtl.rpt b/dot_product/dot_product/dot_product/dot_product.v10/rtl.rpt new file mode 100644 index 0000000..d3305da --- /dev/null +++ b/dot_product/dot_product/dot_product/dot_product.v10/rtl.rpt @@ -0,0 +1,291 @@ +-- Catapult University Version: Report +-- ---------------------------- --------------------------------------------------- +-- Version: 2011a.126 Production Release +-- Build Date: Wed Aug 8 00:52:07 PDT 2012 + +-- Generated by: mg3115@EEWS104A-015 +-- Generated date: Tue Mar 01 15:39:39 +0000 2016 + +Solution Settings: dot_product.v10 + Current state: extract + Project: dot_product + + Design Input Files Specified + $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp + $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h + $MGC_HOME/shared/include/ac_int.h + $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp + $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h + $MGC_HOME/shared/include/ac_int.h + $MGC_HOME/shared/include/mc_scverify.h + + Processes/Blocks in Design + Process Real Operation(s) count Latency Throughput Reset Length II Comments + ----------------- ----------------------- ------- ---------- ------------ -- -------- + /dot_product/core 12 5 5 0 1 + Design Total: 12 5 5 0 1 + + Bill Of Materials (Datapath) + Component Name Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign + --------------------------------------- ---------- --------------------------- ---------- ----- ---------- ----------- + [Lib: mgc_Altera-Cyclone-III-6_beh_psr] + mgc_add(3,0,2,0,3) 4.306 0.000 4.306 0.764 0 1 + mgc_add(3,0,2,1,3) 4.000 0.000 4.000 0.764 1 1 + mgc_add(4,0,3,0,4) 5.297 0.000 5.297 0.856 1 0 + mgc_add(8,0,8,0,8) 9.259 0.000 9.259 1.163 1 1 + mgc_and(3,2) 2.189 0.000 2.189 0.263 1 1 + mgc_and(8,2) 5.839 0.000 5.839 0.263 1 1 + mgc_mul(8,0,8,0,8) 330.250 2.000 10.250 2.659 1 1 + mgc_mux(8,1,2) 7.355 0.000 7.355 0.369 0 1 + mgc_not(1) 0.000 0.000 0.000 0.000 0 3 + mgc_reg_pos(1,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 + mgc_reg_pos(3,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 + mgc_reg_pos(8,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 2 + [Lib: mgc_ioport] + mgc_in_wire(1,8) 0.000 0.000 0.000 0.000 1 1 + mgc_in_wire(2,8) 0.000 0.000 0.000 0.000 1 1 + mgc_out_stdreg(3,8) 0.000 0.000 0.000 0.000 1 1 + + TOTAL AREA (After Assignment): 363.198 2.000 43.000 + + Area Scores + Post-Scheduling Post-DP & FSM Post-Assignment + ----------------- --------------- -------------- --------------- + Total Area Score: 356.8 364.2 363.2 + Total Reg: 0.0 0.0 0.0 + + DataPath: 356.8 (100%) 364.2 (100%) 363.2 (100%) + MUX: 0.0 7.4 (2%) 7.4 (2%) + FUNC: 348.8 (98%) 348.8 (96%) 347.8 (96%) + LOGIC: 8.0 (2%) 8.0 (2%) 8.0 (2%) + BUFFER: 0.0 0.0 0.0 + MEM: 0.0 0.0 0.0 + ROM: 0.0 0.0 0.0 + REG: 0.0 0.0 0.0 + + + FSM: 0.0 0.0 0.0 + FSM-REG: 0.0 0.0 0.0 + FSM-COMB: 0.0 0.0 0.0 + + + Register-to-Variable Mappings + Register Size(bits) Gated Register CG Opt Done Variables + --------------------------- ---------- -------------- ----------- ----------------------------------------------------- + acc.sva#1 8 Y acc.sva#1 + output:rsc:mgc_out_stdreg.d 8 Y output:rsc:mgc_out_stdreg.d + i#1.sva#1 3 Y i#1.sva#1 + exit:MAC.lpi 1 Y exit:MAC.lpi + + Total: 20 20 0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) + + Timing Report + Critical Path + Max Delay: 4.191306 + Slack: 15.808694 + + Path Startpoint Endpoint Delay Slack + --------------------------------------------------- ------------------------------------------ ------------------------------------------------- ------ ------- + 1 dot_product:core/input_a:rsc:mgc_in_wire.d dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 4.1913 15.8087 + + Instance Component Delta Delay + -------- --------- ----- ----- + dot_product:core/input_a:rsc:mgc_in_wire.d 0.0000 0.0000 + dot_product:core/MAC:mul mgc_mul_8_0_8_0_8 2.6592 2.6592 + dot_product:core/MAC:mul.itm 0.0000 2.6592 + dot_product:core/MAC:acc#3 mgc_add_8_0_8_0_8 1.1631 3.8223 + dot_product:core/acc.sva#2 0.0000 3.8223 + dot_product:core/mux mgc_mux_8_1_2 0.3690 4.1913 + dot_product:core/mux.itm 0.0000 4.1913 + dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1 0.0000 4.1913 + + 2 dot_product:core/input_b:rsc:mgc_in_wire.d dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 4.1913 15.8087 + + Instance Component Delta Delay + -------- --------- ----- ----- + dot_product:core/input_b:rsc:mgc_in_wire.d 0.0000 0.0000 + dot_product:core/MAC:mul mgc_mul_8_0_8_0_8 2.6592 2.6592 + dot_product:core/MAC:mul.itm 0.0000 2.6592 + dot_product:core/MAC:acc#3 mgc_add_8_0_8_0_8 1.1631 3.8223 + dot_product:core/acc.sva#2 0.0000 3.8223 + dot_product:core/mux mgc_mux_8_1_2 0.3690 4.1913 + dot_product:core/mux.itm 0.0000 4.1913 + dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1 0.0000 4.1913 + + 3 dot_product:core/input_a:rsc:mgc_in_wire.d dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 3.8223 16.1777 + + Instance Component Delta Delay + -------- --------- ----- ----- + dot_product:core/input_a:rsc:mgc_in_wire.d 0.0000 0.0000 + dot_product:core/MAC:mul mgc_mul_8_0_8_0_8 2.6592 2.6592 + dot_product:core/MAC:mul.itm 0.0000 2.6592 + dot_product:core/MAC:acc#3 mgc_add_8_0_8_0_8 1.1631 3.8223 + dot_product:core/acc.sva#2 0.0000 3.8223 + dot_product:core/mux mgc_mux_8_1_2 0.3690 4.1913 + dot_product:core/mux.itm 0.0000 4.1913 + dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1 0.0000 4.1913 + + 4 dot_product:core/input_b:rsc:mgc_in_wire.d dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 3.8223 16.1777 + + Instance Component Delta Delay + -------- --------- ----- ----- + dot_product:core/input_b:rsc:mgc_in_wire.d 0.0000 0.0000 + dot_product:core/MAC:mul mgc_mul_8_0_8_0_8 2.6592 2.6592 + dot_product:core/MAC:mul.itm 0.0000 2.6592 + dot_product:core/MAC:acc#3 mgc_add_8_0_8_0_8 1.1631 3.8223 + dot_product:core/acc.sva#2 0.0000 3.8223 + dot_product:core/mux mgc_mux_8_1_2 0.3690 4.1913 + dot_product:core/mux.itm 0.0000 4.1913 + dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1 0.0000 4.1913 + + 5 dot_product:core/reg(i#1.sva#1) dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 2.1603 17.8397 + + Instance Component Delta Delay + -------- --------- ----- ----- + dot_product:core/reg(i#1.sva#1) mgc_reg_pos_3_1_0_0_0_1_1 0.0000 0.0000 + dot_product:core/i#1.sva#1 0.0000 0.0000 + dot_product:core/MAC:and#1 mgc_and_3_2 0.2625 0.2625 + dot_product:core/MAC:and#1.itm 0.0000 0.2625 + dot_product:core/MAC:acc#4 mgc_add_3_0_2_1_3 0.7644 1.0269 + dot_product:core/i#1.sva#2 0.0000 1.0269 + dot_product:core/MAC:acc mgc_add_3_0_2_0_3 0.7644 1.7913 + dot_product:core/MAC:acc.itm 0.0000 1.7913 + dot_product:core/MAC:slc 0.0000 1.7913 + dot_product:core/MAC:slc.itm 0.0000 1.7913 + dot_product:core/mux mgc_mux_8_1_2 0.3690 2.1603 + dot_product:core/mux.itm 0.0000 2.1603 + dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1 0.0000 2.1603 + + 6 dot_product:core/reg(exit:MAC.lpi) dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 2.1603 17.8397 + + Instance Component Delta Delay + -------- --------- ----- ----- + dot_product:core/reg(exit:MAC.lpi) mgc_reg_pos_1_1_0_0_0_1_1 0.0000 0.0000 + dot_product:core/exit:MAC.lpi 0.0000 0.0000 + dot_product:core/MAC:not#5 mgc_not_1 0.0000 0.0000 + dot_product:core/MAC:not#5.itm 0.0000 0.0000 + dot_product:core/MAC:exs#1 0.0000 0.0000 + dot_product:core/MAC:exs#1.itm 0.0000 0.0000 + dot_product:core/MAC:and#1 mgc_and_3_2 0.2625 0.2625 + dot_product:core/MAC:and#1.itm 0.0000 0.2625 + dot_product:core/MAC:acc#4 mgc_add_3_0_2_1_3 0.7644 1.0269 + dot_product:core/i#1.sva#2 0.0000 1.0269 + dot_product:core/MAC:acc mgc_add_3_0_2_0_3 0.7644 1.7913 + dot_product:core/MAC:acc.itm 0.0000 1.7913 + dot_product:core/MAC:slc 0.0000 1.7913 + dot_product:core/MAC:slc.itm 0.0000 1.7913 + dot_product:core/mux mgc_mux_8_1_2 0.3690 2.1603 + dot_product:core/mux.itm 0.0000 2.1603 + dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1 0.0000 2.1603 + + 7 dot_product:core/reg(i#1.sva#1) dot_product:core/reg(exit:MAC.lpi) 1.7913 18.2087 + + Instance Component Delta Delay + -------- --------- ----- ----- + dot_product:core/reg(i#1.sva#1) mgc_reg_pos_3_1_0_0_0_1_1 0.0000 0.0000 + dot_product:core/i#1.sva#1 0.0000 0.0000 + dot_product:core/MAC:and#1 mgc_and_3_2 0.2625 0.2625 + dot_product:core/MAC:and#1.itm 0.0000 0.2625 + dot_product:core/MAC:acc#4 mgc_add_3_0_2_1_3 0.7644 1.0269 + dot_product:core/i#1.sva#2 0.0000 1.0269 + dot_product:core/MAC:acc mgc_add_3_0_2_0_3 0.7644 1.7913 + dot_product:core/MAC:acc.itm 0.0000 1.7913 + dot_product:core/MAC:slc#1 0.0000 1.7913 + dot_product:core/MAC:slc#1.itm 0.0000 1.7913 + dot_product:core/MAC:not mgc_not_1 0.0000 1.7913 + dot_product:core/MAC:not.itm 0.0000 1.7913 + dot_product:core/reg(exit:MAC.lpi) mgc_reg_pos_1_1_0_0_0_1_1 0.0000 1.7913 + + 8 dot_product:core/reg(exit:MAC.lpi) dot_product:core/reg(exit:MAC.lpi) 1.7913 18.2087 + + Instance Component Delta Delay + -------- --------- ----- ----- + dot_product:core/reg(exit:MAC.lpi) mgc_reg_pos_1_1_0_0_0_1_1 0.0000 0.0000 + dot_product:core/exit:MAC.lpi 0.0000 0.0000 + dot_product:core/MAC:not#5 mgc_not_1 0.0000 0.0000 + dot_product:core/MAC:not#5.itm 0.0000 0.0000 + dot_product:core/MAC:exs#1 0.0000 0.0000 + dot_product:core/MAC:exs#1.itm 0.0000 0.0000 + dot_product:core/MAC:and#1 mgc_and_3_2 0.2625 0.2625 + dot_product:core/MAC:and#1.itm 0.0000 0.2625 + dot_product:core/MAC:acc#4 mgc_add_3_0_2_1_3 0.7644 1.0269 + dot_product:core/i#1.sva#2 0.0000 1.0269 + dot_product:core/MAC:acc mgc_add_3_0_2_0_3 0.7644 1.7913 + dot_product:core/MAC:acc.itm 0.0000 1.7913 + dot_product:core/MAC:slc#1 0.0000 1.7913 + dot_product:core/MAC:slc#1.itm 0.0000 1.7913 + dot_product:core/MAC:not mgc_not_1 0.0000 1.7913 + dot_product:core/MAC:not.itm 0.0000 1.7913 + dot_product:core/reg(exit:MAC.lpi) mgc_reg_pos_1_1_0_0_0_1_1 0.0000 1.7913 + + 9 dot_product:core/reg(acc.sva#1) dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 1.4256 18.5744 + + Instance Component Delta Delay + -------- --------- ----- ----- + dot_product:core/reg(acc.sva#1) mgc_reg_pos_8_1_0_0_0_1_1 0.0000 0.0000 + dot_product:core/acc.sva#1 0.0000 0.0000 + dot_product:core/MAC:and mgc_and_8_2 0.2625 0.2625 + dot_product:core/MAC:and.itm 0.0000 0.2625 + dot_product:core/MAC:acc#3 mgc_add_8_0_8_0_8 1.1631 1.4256 + dot_product:core/acc.sva#2 0.0000 1.4256 + dot_product:core/mux mgc_mux_8_1_2 0.3690 1.7946 + dot_product:core/mux.itm 0.0000 1.7946 + dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1 0.0000 1.7946 + + 10 dot_product:core/reg(exit:MAC.lpi) dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 1.4256 18.5744 + + Instance Component Delta Delay + -------- --------- ----- ----- + dot_product:core/reg(exit:MAC.lpi) mgc_reg_pos_1_1_0_0_0_1_1 0.0000 0.0000 + dot_product:core/exit:MAC.lpi 0.0000 0.0000 + dot_product:core/MAC:not#3 mgc_not_1 0.0000 0.0000 + dot_product:core/MAC:not#3.itm 0.0000 0.0000 + dot_product:core/MAC:exs 0.0000 0.0000 + dot_product:core/MAC:exs.itm 0.0000 0.0000 + dot_product:core/MAC:and mgc_and_8_2 0.2625 0.2625 + dot_product:core/MAC:and.itm 0.0000 0.2625 + dot_product:core/MAC:acc#3 mgc_add_8_0_8_0_8 1.1631 1.4256 + dot_product:core/acc.sva#2 0.0000 1.4256 + dot_product:core/mux mgc_mux_8_1_2 0.3690 1.7946 + dot_product:core/mux.itm 0.0000 1.7946 + dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1 0.0000 1.7946 + + + Register Input and Register-to-Output Slack + Clock period or pin-to-reg delay constraint (clk): 20.0 + Clock uncertainty constraint (clk) : 0.0 + + Instance Port Slack (Delay) Messages + ------------------------------------------------- ------------ ------- ------- -------- + dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mux.itm 15.8087 4.1913 + dot_product:core/reg(acc.sva#1) acc.sva#2 15.8087 4.1913 + dot_product:core/reg(i#1.sva#1) i#1.sva#2 17.8397 2.1603 + dot_product:core/reg(exit:MAC.lpi) MAC:not.itm 18.2087 1.7913 + dot_product output:rsc.z 20.0000 0.0000 + + Operator Bitwidth Summary + Operation Size (bits) Count + ---------- ----------- ----- + add + - 8 1 + - 3 2 + and + - 2 2 + mul + - 8 1 + mux + - 1 1 + not + - 1 3 + read_port + - 8 2 + reg + - 8 2 + - 3 1 + - 1 1 + write_port + - 8 1 + + End of Report |