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diff --git a/dot_product/dot_product/dot_product/dot_product.v9/cycle_mgc_ioport_v2001.v b/dot_product/dot_product/dot_product/dot_product.v9/cycle_mgc_ioport_v2001.v
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--- a/dot_product/dot_product/dot_product/dot_product.v9/cycle_mgc_ioport_v2001.v
+++ /dev/null
@@ -1,700 +0,0 @@
-//------------------------------------------------------------------
-
-module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
-
- parameter integer rscid = 1;
- parameter integer width = 8;
- parameter ph_en = 1'b1;
- parameter ph_arst = 1'b1;
- parameter ph_srst = 1'b1;
-
- input clk;
- input en;
- input arst;
- input srst;
- input ld;
- input [width-1:0] d;
- output lz;
- output [width-1:0] z;
-
- reg lz;
- reg [width-1:0] z;
-
- generate
- if (ph_arst == 1'b0)
- begin: NEG_ARST
- always @(posedge clk or negedge arst)
- if (arst == 1'b0)
- begin: B1
- lz <= 1'b0;
- z <= {width{1'b0}};
- end
- else if (srst == ph_srst)
- begin: B2
- lz <= 1'b0;
- z <= {width{1'b0}};
- end
- else if (en == ph_en)
- begin: B3
- lz <= ld;
- z <= (ld) ? d : z;
- end
- end
- else
- begin: POS_ARST
- always @(posedge clk or posedge arst)
- if (arst == 1'b1)
- begin: B1
- lz <= 1'b0;
- z <= {width{1'b0}};
- end
- else if (srst == ph_srst)
- begin: B2
- lz <= 1'b0;
- z <= {width{1'b0}};
- end
- else if (en == ph_en)
- begin: B3
- lz <= ld;
- z <= (ld) ? d : z;
- end
- end
- endgenerate
-
-endmodule
-
-//------------------------------------------------------------------
-
-module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
-
- parameter integer rscid = 1;
- parameter integer width = 8;
- parameter ph_en = 1'b1;
- parameter ph_arst = 1'b1;
- parameter ph_srst = 1'b1;
-
- input clk;
- input en;
- input arst;
- input srst;
- input ld;
- input [width-1:0] d;
- output lz;
- output [width-1:0] z;
-
- reg lz;
- reg [width-1:0] z;
-
- generate
- if (ph_arst == 1'b0)
- begin: NEG_ARST
- always @(negedge clk or negedge arst)
- if (arst == 1'b0)
- begin: B1
- lz <= 1'b0;
- z <= {width{1'b0}};
- end
- else if (srst == ph_srst)
- begin: B2
- lz <= 1'b0;
- z <= {width{1'b0}};
- end
- else if (en == ph_en)
- begin: B3
- lz <= ld;
- z <= (ld) ? d : z;
- end
- end
- else
- begin: POS_ARST
- always @(negedge clk or posedge arst)
- if (arst == 1'b1)
- begin: B1
- lz <= 1'b0;
- z <= {width{1'b0}};
- end
- else if (srst == ph_srst)
- begin: B2
- lz <= 1'b0;
- z <= {width{1'b0}};
- end
- else if (en == ph_en)
- begin: B3
- lz <= ld;
- z <= (ld) ? d : z;
- end
- end
- endgenerate
-
-endmodule
-
-//------------------------------------------------------------------
-
-module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
-
- parameter integer rscid = 1;
- parameter integer width = 8;
- parameter ph_clk = 1'b1;
- parameter ph_en = 1'b1;
- parameter ph_arst = 1'b1;
- parameter ph_srst = 1'b1;
-
- input clk;
- input en;
- input arst;
- input srst;
- input ld;
- input [width-1:0] d;
- output lz;
- output [width-1:0] z;
-
-
- generate
- if (ph_clk == 1'b0)
- begin: NEG_EDGE
-
- mgc_out_reg_neg
- #(
- .rscid (rscid),
- .width (width),
- .ph_en (ph_en),
- .ph_arst (ph_arst),
- .ph_srst (ph_srst)
- )
- mgc_out_reg_neg_inst
- (
- .clk (clk),
- .en (en),
- .arst (arst),
- .srst (srst),
- .ld (ld),
- .d (d),
- .lz (lz),
- .z (z)
- );
-
- end
- else
- begin: POS_EDGE
-
- mgc_out_reg_pos
- #(
- .rscid (rscid),
- .width (width),
- .ph_en (ph_en),
- .ph_arst (ph_arst),
- .ph_srst (ph_srst)
- )
- mgc_out_reg_pos_inst
- (
- .clk (clk),
- .en (en),
- .arst (arst),
- .srst (srst),
- .ld (ld),
- .d (d),
- .lz (lz),
- .z (z)
- );
-
- end
- endgenerate
-
-endmodule
-
-
-
-
-//------------------------------------------------------------------
-
-module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
-
- parameter integer rscid = 1;
- parameter integer width = 8;
- parameter ph_clk = 1'b1;
- parameter ph_en = 1'b1;
- parameter ph_arst = 1'b1;
- parameter ph_srst = 1'b1;
-
- input clk;
- input en;
- input arst;
- input srst;
- input ld;
- output vd;
- input [width-1:0] d;
- output lz;
- input vz;
- output [width-1:0] z;
-
- wire filled;
- wire filled_next;
- wire [width-1:0] abuf;
- wire lbuf;
-
-
- assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
-
- assign lbuf = ld & ~(filled ^ vz);
-
- assign vd = vz | ~filled;
-
- assign lz = ld | filled;
-
- assign z = (filled) ? abuf : d;
-
- wire dummy;
- wire dummy_bufreg_lz;
-
- // Output registers:
- mgc_out_reg
- #(
- .rscid (rscid),
- .width (1'b1),
- .ph_clk (ph_clk),
- .ph_en (ph_en),
- .ph_arst (ph_arst),
- .ph_srst (ph_srst)
- )
- STATREG
- (
- .clk (clk),
- .en (en),
- .arst (arst),
- .srst (srst),
- .ld (filled_next),
- .d (1'b0), // input d is unused
- .lz (filled),
- .z (dummy) // output z is unused
- );
-
- mgc_out_reg
- #(
- .rscid (rscid),
- .width (width),
- .ph_clk (ph_clk),
- .ph_en (ph_en),
- .ph_arst (ph_arst),
- .ph_srst (ph_srst)
- )
- BUFREG
- (
- .clk (clk),
- .en (en),
- .arst (arst),
- .srst (srst),
- .ld (lbuf),
- .d (d),
- .lz (dummy_bufreg_lz),
- .z (abuf)
- );
-
-endmodule
-
-//------------------------------------------------------------------
-
-module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz, z);
-
- parameter integer rscid = 0; // resource ID
- parameter integer width = 8; // fifo width
- parameter integer fifo_sz = 8; // fifo depth
- parameter ph_clk = 1'b1; // clock polarity 1=rising edge, 0=falling edge
- parameter ph_en = 1'b1; // clock enable polarity
- parameter ph_arst = 1'b1; // async reset polarity
- parameter ph_srst = 1'b1; // sync reset polarity
- parameter integer ph_log2 = 3; // log2(fifo_sz)
- parameter integer pwropt = 0; // pwropt
-
-
- input clk;
- input en;
- input arst;
- input srst;
- input ld; // load data
- output vd; // fifo full active low
- input [width-1:0] d;
- output lz; // fifo ready to send
- input vz; // dest ready for data
- output [width-1:0] z;
-
- wire [31:0] size;
-
-
- // Output registers:
- mgc_out_fifo_wait_core#(
- .rscid (rscid),
- .width (width),
- .sz_width (32),
- .fifo_sz (fifo_sz),
- .ph_clk (ph_clk),
- .ph_en (ph_en),
- .ph_arst (ph_arst),
- .ph_srst (ph_srst),
- .ph_log2 (ph_log2),
- .pwropt (pwropt)
- ) CORE (
- .clk (clk),
- .en (en),
- .arst (arst),
- .srst (srst),
- .ld (ld),
- .vd (vd),
- .d (d),
- .lz (lz),
- .vz (vz),
- .z (z),
- .size (size)
- );
-
-endmodule
-
-
-
-module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz, z, size);
-
- parameter integer rscid = 0; // resource ID
- parameter integer width = 8; // fifo width
- parameter integer sz_width = 8; // size of port for elements in fifo
- parameter integer fifo_sz = 8; // fifo depth
- parameter ph_clk = 1'b1; // clock polarity 1=rising edge, 0=falling edge
- parameter ph_en = 1'b1; // clock enable polarity
- parameter ph_arst = 1'b1; // async reset polarity
- parameter ph_srst = 1'b1; // sync reset polarity
- parameter integer ph_log2 = 3; // log2(fifo_sz)
- parameter integer pwropt = 0; // pwropt
-
- localparam integer fifo_b = width * fifo_sz;
-
- input clk;
- input en;
- input arst;
- input srst;
- input ld; // load data
- output vd; // fifo full active low
- input [width-1:0] d;
- output lz; // fifo ready to send
- input vz; // dest ready for data
- output [width-1:0] z;
- output [sz_width-1:0] size;
-
- reg [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
- wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
- reg [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
- wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
- reg [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
- reg [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
-
- reg [width-1:0] buff_nxt;
-
- reg stat_nxt;
- reg stat_before;
- reg stat_after;
- reg en_l_var;
-
- integer i;
- genvar eni;
-
- wire [32:0] size_t;
- reg [31:0] count;
- reg [31:0] count_t;
- reg [32:0] n_elem;
-// pragma translate_off
- reg [31:0] peak;
-// pragma translate_on
-
- wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
- wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
-
- generate
- if ( fifo_sz > 0 )
- begin: FIFO_REG
- assign vd = vz | ~stat[0];
- assign lz = ld | stat[fifo_sz-1];
- assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
- assign size = size_t[sz_width-1:0];
- assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
-
- always @(*)
- begin: FIFOPROC
- n_elem = 33'b0;
- for (i = fifo_sz-1; i >= 0; i = i - 1)
- begin
- if (i != 0)
- stat_before = stat[i-1];
- else
- stat_before = 1'b0;
-
- if (i != (fifo_sz-1))
- stat_after = stat[i+1];
- else
- stat_after = 1'b1;
-
- stat_nxt = stat_after &
- (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
-
- stat_pre[i] = stat_nxt;
- en_l_var = 1'b1;
- if (!stat_nxt)
- begin
- buff_nxt = {width{1'b0}};
- en_l_var = 1'b0;
- end
- else if (vz && stat_before)
- buff_nxt[0+:width] = buff[width*(i-1)+:width];
- else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
- buff_nxt = d;
- else
- begin
- if (pwropt == 0)
- buff_nxt[0+:width] = buff[width*i+:width];
- else
- buff_nxt = {width{1'b0}};
- en_l_var = 1'b0;
- end
-
- if (ph_en != 0)
- en_l[i] = en & en_l_var;
- else
- en_l[i] = en | ~en_l_var;
-
- buff_pre[width*i+:width] = buff_nxt[0+:width];
-
- if ((stat_after == 1'b1) && (stat[i] == 1'b0))
- n_elem = ($unsigned(fifo_sz) - 1) - i;
- end
-
- if (ph_en != 0)
- en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
- else
- en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
-
- for (i = fifo_sz-1; i >= 7; i = i - 1)
- begin
- if ((i%'d2) == 0)
- begin
- if (ph_en != 0)
- en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
- else
- en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
- end
- end
-
- if ( stat[fifo_sz-1] == 1'b0 )
- count_t = 32'b0;
- else if ( stat[0] == 1'b1 )
- count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
- else
- count_t = n_elem[31:0];
- count = count_t;
-// pragma translate_off
- if ( peak < count )
- peak = count;
-// pragma translate_on
- end
-
- if (pwropt == 0)
- begin: NOCGFIFO
- // Output registers:
- mgc_out_reg
- #(
- .rscid (rscid),
- .width (fifo_sz),
- .ph_clk (ph_clk),
- .ph_en (ph_en),
- .ph_arst (ph_arst),
- .ph_srst (ph_srst)
- )
- STATREG
- (
- .clk (clk),
- .en (en),
- .arst (arst),
- .srst (srst),
- .ld (1'b1),
- .d (stat_pre),
- .lz (dummy_statreg_lz[0]),
- .z (stat)
- );
- mgc_out_reg
- #(
- .rscid (rscid),
- .width (fifo_b),
- .ph_clk (ph_clk),
- .ph_en (ph_en),
- .ph_arst (ph_arst),
- .ph_srst (ph_srst)
- )
- BUFREG
- (
- .clk (clk),
- .en (en),
- .arst (arst),
- .srst (srst),
- .ld (1'b1),
- .d (buff_pre),
- .lz (dummy_bufreg_lz[0]),
- .z (buff)
- );
- end
- else
- begin: CGFIFO
- // Output registers:
- if ( pwropt > 1)
- begin: CGSTATFIFO2
- for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
- begin: pwroptGEN1
- mgc_out_reg
- #(
- .rscid (rscid),
- .width (1),
- .ph_clk (ph_clk),
- .ph_en (ph_en),
- .ph_arst (ph_arst),
- .ph_srst (ph_srst)
- )
- STATREG
- (
- .clk (clk),
- .en (en_l_s[eni/8]),
- .arst (arst),
- .srst (srst),
- .ld (1'b1),
- .d (stat_pre[eni]),
- .lz (dummy_statreg_lz[eni]),
- .z (stat[eni])
- );
- end
- end
- else
- begin: CGSTATFIFO
- mgc_out_reg
- #(
- .rscid (rscid),
- .width (fifo_sz),
- .ph_clk (ph_clk),
- .ph_en (ph_en),
- .ph_arst (ph_arst),
- .ph_srst (ph_srst)
- )
- STATREG
- (
- .clk (clk),
- .en (en),
- .arst (arst),
- .srst (srst),
- .ld (1'b1),
- .d (stat_pre),
- .lz (dummy_statreg_lz[0]),
- .z (stat)
- );
- end
- for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
- begin: pwroptGEN2
- mgc_out_reg
- #(
- .rscid (rscid),
- .width (width),
- .ph_clk (ph_clk),
- .ph_en (ph_en),
- .ph_arst (ph_arst),
- .ph_srst (ph_srst)
- )
- BUFREG
- (
- .clk (clk),
- .en (en_l[eni]),
- .arst (arst),
- .srst (srst),
- .ld (1'b1),
- .d (buff_pre[width*eni+:width]),
- .lz (dummy_bufreg_lz[eni]),
- .z (buff[width*eni+:width])
- );
- end
- end
- end
- else
- begin: FEED_THRU
- assign vd = vz;
- assign lz = ld;
- assign z = d;
- assign size = ld && !vz;
- end
- endgenerate
-
-endmodule
-
-//------------------------------------------------------------------
-//-- PIPE ENTITIES
-//------------------------------------------------------------------
-/*
- *
- * _______________________________________________
- * WRITER | | READER
- * | MGC_PIPE |
- * | __________________________ |
- * --<| vdout --<| vd --------------- vz<|-----ldin<|---
- * | | FIFO | |
- * ---|>ldout ---|>ld ---------------- lz |> ---vdin |>--
- * ---|>dout -----|>d ---------------- dz |> ----din |>--
- * | |________________________| |
- * |_______________________________________________|
- */
-// two clock pipe
-module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
-
- parameter integer rscid = 0; // resource ID
- parameter integer width = 8; // fifo width
- parameter integer sz_width = 8; // width of size of elements in fifo
- parameter integer fifo_sz = 8; // fifo depth
- parameter integer log2_sz = 3; // log2(fifo_sz)
- parameter ph_clk = 1'b1; // clock polarity 1=rising edge, 0=falling edge
- parameter ph_en = 1'b1; // clock enable polarity
- parameter ph_arst = 1'b1; // async reset polarity
- parameter ph_srst = 1'b1; // sync reset polarity
- parameter integer pwropt = 0; // pwropt
-
- input clk;
- input en;
- input arst;
- input srst;
- input ldin;
- output vdin;
- output [width-1:0] din;
- input ldout;
- output vdout;
- input [width-1:0] dout;
- output [sz_width-1:0] size;
- input req_size;
-
-
- mgc_out_fifo_wait_core
- #(
- .rscid (rscid),
- .width (width),
- .sz_width (sz_width),
- .fifo_sz (fifo_sz),
- .ph_clk (ph_clk),
- .ph_en (ph_en),
- .ph_arst (ph_arst),
- .ph_srst (ph_srst),
- .ph_log2 (log2_sz),
- .pwropt (pwropt)
- )
- FIFO
- (
- .clk (clk),
- .en (en),
- .arst (arst),
- .srst (srst),
- .ld (ldout),
- .vd (vdout),
- .d (dout),
- .lz (vdin),
- .vz (ldin),
- .z (din),
- .size (size)
- );
-
-endmodule
-
generated by cgit (git 2.34.1) at 2024-06-01 00:18:16 +0000