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Diffstat (limited to 'dot_product/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.rpt')
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1 files changed, 0 insertions, 2369 deletions
diff --git a/dot_product/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.rpt b/dot_product/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.rpt deleted file mode 100644 index 11e69ce..0000000 --- a/dot_product/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.rpt +++ /dev/null @@ -1,2369 +0,0 @@ -Fitter report for ise_proj -Tue Mar 01 16:05:11 2016 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. I/O Assignment Warnings - 6. Ignored Assignments - 7. Incremental Compilation Preservation Summary - 8. Incremental Compilation Partition Settings - 9. Incremental Compilation Placement Preservation - 10. Pin-Out File - 11. Fitter Resource Usage Summary - 12. Fitter Partition Statistics - 13. Input Pins - 14. Output Pins - 15. Dual Purpose and Dedicated Pins - 16. I/O Bank Usage - 17. All Package Pins - 18. Fitter Resource Utilization by Entity - 19. Delay Chain Summary - 20. Pad To Core Delay Chain Fanout - 21. Other Routing Usage Summary - 22. I/O Rules Summary - 23. I/O Rules Details - 24. I/O Rules Matrix - 25. Fitter Device Options - 26. Operating Settings and Conditions - 27. Fitter Messages - 28. Fitter Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+--------------------------------------------------+ -; Fitter Status ; Successful - Tue Mar 01 16:05:11 2016 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ; -; Revision Name ; ise_proj ; -; Top-level Entity Name ; ise_proj ; -; Family ; Cyclone III ; -; Device ; EP3C16F484C6 ; -; Timing Models ; Final ; -; Total logic elements ; 0 / 15,408 ( 0 % ) ; -; Total combinational functions ; 0 / 15,408 ( 0 % ) ; -; Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; -; Total registers ; 0 ; -; Total pins ; 51 / 347 ( 15 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 516,096 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; -; Total PLLs ; 0 / 4 ( 0 % ) ; -+------------------------------------+--------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ -; Device ; EP3C16F484C6 ; ; -; Nominal Core Supply Voltage ; 1.2V ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Device I/O Standard ; 2.5 V ; ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Auto Merge PLLs ; On ; On ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Perform Clocking Topology Analysis During Routing ; Off ; Off ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Optimize Hold Timing ; All Paths ; All Paths ; -; Optimize Multi-Corner Timing ; On ; On ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; SSN Optimization ; Off ; Off ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate full fit report during ECO compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; Normal ; Normal ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Packed Registers ; Auto ; Auto ; -; Auto Delay Chains ; On ; On ; -; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; -; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; -; Treat Bidirectional Pin as Output Pin ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; -; Auto Register Duplication ; Auto ; Auto ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; -; Synchronizer Identification ; Off ; Off ; -; Enable Beneficial Skew Optimization ; On ; On ; -; Optimize Design for Metastability ; On ; On ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -; RAM Bit Reservation (Cyclone III) ; Off ; Off ; -; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 8 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 4 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processors 2-4 ; < 0.1% ; -; Processors 5-8 ; 0.0% ; -+----------------------------+-------------+ - - -+--------------------------------------------------+ -; I/O Assignment Warnings ; -+-----------+--------------------------------------+ -; Pin Name ; Reason ; -+-----------+--------------------------------------+ -; VGA_CLK ; Missing drive strength and slew rate ; -; VGA_SYNC ; Missing drive strength and slew rate ; -; VGA_BLANK ; Missing drive strength and slew rate ; -; VGA_VS ; Missing drive strength ; -; VGA_HS ; Missing drive strength ; -; HEX0_D[6] ; Missing drive strength ; -; HEX0_D[5] ; Missing drive strength ; -; HEX0_D[4] ; Missing drive strength ; -; HEX0_D[3] ; Missing drive strength ; -; HEX0_D[2] ; Missing drive strength ; -; HEX0_D[1] ; Missing drive strength ; -; HEX0_D[0] ; Missing drive strength ; -; LEDG[9] ; Missing drive strength ; -; LEDG[8] ; Missing drive strength ; -; LEDG[7] ; Missing drive strength ; -; LEDG[6] ; Missing drive strength ; -; LEDG[5] ; Missing drive strength ; -; LEDG[4] ; Missing drive strength ; -; LEDG[3] ; Missing drive strength ; -; LEDG[2] ; Missing drive strength ; -; LEDG[1] ; Missing drive strength ; -; LEDG[0] ; Missing drive strength ; -; VGA_B[3] ; Missing drive strength ; -; VGA_B[2] ; Missing drive strength ; -; VGA_B[1] ; Missing drive strength ; -; VGA_B[0] ; Missing drive strength ; -; VGA_G[3] ; Missing drive strength ; -; VGA_G[2] ; Missing drive strength ; -; VGA_G[1] ; Missing drive strength ; -; VGA_G[0] ; Missing drive strength ; -; VGA_R[3] ; Missing drive strength ; -; VGA_R[2] ; Missing drive strength ; -; VGA_R[1] ; Missing drive strength ; -; VGA_R[0] ; Missing drive strength ; -+-----------+--------------------------------------+ - - -+-------------------------------------------------------------------------------------------------+ -; Ignored Assignments ; -+--------------+----------------+--------------+-----------------+---------------+----------------+ -; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; -+--------------+----------------+--------------+-----------------+---------------+----------------+ -; Location ; ; ; DRAM_ADDR[0] ; PIN_C4 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[10] ; PIN_B4 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[11] ; PIN_A7 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[12] ; PIN_C8 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[1] ; PIN_A3 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[2] ; PIN_B3 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[3] ; PIN_C3 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[4] ; PIN_A5 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[5] ; PIN_C6 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[6] ; PIN_B6 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[7] ; PIN_A6 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[8] ; PIN_C7 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[9] ; PIN_B7 ; QSF Assignment ; -; Location ; ; ; DRAM_BA[0] ; PIN_B5 ; QSF Assignment ; -; Location ; ; ; DRAM_BA[1] ; PIN_A4 ; QSF Assignment ; -; Location ; ; ; DRAM_BA_0 ; PIN_B5 ; QSF Assignment ; -; Location ; ; ; DRAM_BA_1 ; PIN_A4 ; QSF Assignment ; -; Location ; ; ; DRAM_CAS_N ; PIN_G8 ; QSF Assignment ; -; Location ; ; ; DRAM_CKE ; PIN_E6 ; QSF Assignment ; -; Location ; ; ; DRAM_CLK ; PIN_E5 ; QSF Assignment ; -; Location ; ; ; DRAM_CS_N ; PIN_G7 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[0] ; PIN_D10 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[10] ; PIN_A9 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[11] ; PIN_C10 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[12] ; PIN_B10 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[13] ; PIN_A10 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[14] ; PIN_E10 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[15] ; PIN_F10 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[1] ; PIN_G10 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[2] ; PIN_H10 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[3] ; PIN_E9 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[4] ; PIN_F9 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[5] ; PIN_G9 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[6] ; PIN_H9 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[7] ; PIN_F8 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[8] ; PIN_A8 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[9] ; PIN_B9 ; QSF Assignment ; -; Location ; ; ; DRAM_LDQM ; PIN_E7 ; QSF Assignment ; -; Location ; ; ; DRAM_RAS_N ; PIN_F7 ; QSF Assignment ; -; Location ; ; ; DRAM_UDQM ; PIN_B8 ; QSF Assignment ; -; Location ; ; ; DRAM_WE_N ; PIN_D6 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[0] ; PIN_P7 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[10] ; PIN_N1 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[11] ; PIN_M3 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[12] ; PIN_M2 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[13] ; PIN_M1 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[14] ; PIN_L7 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[15] ; PIN_L6 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[16] ; PIN_AA2 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[17] ; PIN_M5 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[18] ; PIN_M6 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[19] ; PIN_P1 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[1] ; PIN_P5 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[20] ; PIN_P3 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[21] ; PIN_R2 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[2] ; PIN_P6 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[3] ; PIN_N7 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[4] ; PIN_N5 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[5] ; PIN_N6 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[6] ; PIN_M8 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[7] ; PIN_M4 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[8] ; PIN_P2 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[9] ; PIN_N2 ; QSF Assignment ; -; Location ; ; ; FL_BYTE_N ; PIN_AA1 ; QSF Assignment ; -; Location ; ; ; FL_CE_N ; PIN_N8 ; QSF Assignment ; -; Location ; ; ; FL_DQ15_AM1 ; PIN_Y2 ; QSF Assignment ; -; Location ; ; ; FL_DQ[0] ; PIN_R7 ; QSF Assignment ; -; Location ; ; ; FL_DQ[10] ; PIN_T4 ; QSF Assignment ; -; Location ; ; ; FL_DQ[11] ; PIN_U2 ; QSF Assignment ; -; Location ; ; ; FL_DQ[12] ; PIN_V1 ; QSF Assignment ; -; Location ; ; ; FL_DQ[13] ; PIN_V4 ; QSF Assignment ; -; Location ; ; ; FL_DQ[14] ; PIN_W2 ; QSF Assignment ; -; Location ; ; ; FL_DQ[1] ; PIN_P8 ; QSF Assignment ; -; Location ; ; ; FL_DQ[2] ; PIN_R8 ; QSF Assignment ; -; Location ; ; ; FL_DQ[3] ; PIN_U1 ; QSF Assignment ; -; Location ; ; ; FL_DQ[4] ; PIN_V2 ; QSF Assignment ; -; Location ; ; ; FL_DQ[5] ; PIN_V3 ; QSF Assignment ; -; Location ; ; ; FL_DQ[6] ; PIN_W1 ; QSF Assignment ; -; Location ; ; ; FL_DQ[7] ; PIN_Y1 ; QSF Assignment ; -; Location ; ; ; FL_DQ[8] ; PIN_T5 ; QSF Assignment ; -; Location ; ; ; FL_DQ[9] ; PIN_T7 ; QSF Assignment ; -; Location ; ; ; FL_OE_N ; PIN_R6 ; QSF Assignment ; -; Location ; ; ; FL_RST_N ; PIN_R1 ; QSF Assignment ; -; Location ; ; ; FL_RY ; PIN_M7 ; QSF Assignment ; -; Location ; ; ; FL_WE_N ; PIN_P4 ; QSF Assignment ; -; Location ; ; ; FL_WP_N ; PIN_T3 ; QSF Assignment ; -; Location ; ; ; GPIO0_CLKIN[0] ; PIN_AB12 ; QSF Assignment ; -; Location ; ; ; GPIO0_CLKIN[1] ; PIN_AA12 ; QSF Assignment ; -; Location ; ; ; GPIO0_CLKOUT[0] ; PIN_AB3 ; QSF Assignment ; -; Location ; ; ; GPIO0_CLKOUT[1] ; PIN_AA3 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[0] ; PIN_AB16 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[10] ; PIN_AB8 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[11] ; PIN_AA8 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[12] ; PIN_AB5 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[13] ; PIN_AA5 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[14] ; PIN_AB4 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[15] ; PIN_AA4 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[16] ; PIN_V14 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[17] ; PIN_U14 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[18] ; PIN_Y13 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[19] ; PIN_W13 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[1] ; PIN_AA16 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[20] ; PIN_U13 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[21] ; PIN_V12 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[22] ; PIN_R10 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[23] ; PIN_V11 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[24] ; PIN_Y10 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[25] ; PIN_W10 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[26] ; PIN_T8 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[27] ; PIN_V8 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[28] ; PIN_W7 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[29] ; PIN_W6 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[2] ; PIN_AA15 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[30] ; PIN_V5 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[31] ; PIN_U7 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[3] ; PIN_AB15 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[4] ; PIN_AA14 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[5] ; PIN_AB14 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[6] ; PIN_AB13 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[7] ; PIN_AA13 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[8] ; PIN_AB10 ; QSF Assignment ; -; Location ; ; ; GPIO0_D[9] ; PIN_AA10 ; QSF Assignment ; -; Location ; ; ; GPIO1_CLKIN[0] ; PIN_AB11 ; QSF Assignment ; -; Location ; ; ; GPIO1_CLKIN[1] ; PIN_AA11 ; QSF Assignment ; -; Location ; ; ; GPIO1_CLKOUT[0] ; PIN_R16 ; QSF Assignment ; -; Location ; ; ; GPIO1_CLKOUT[1] ; PIN_T16 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[0] ; PIN_AA20 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[10] ; PIN_U15 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[11] ; PIN_T15 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[12] ; PIN_W15 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[13] ; PIN_V15 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[14] ; PIN_AB9 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[15] ; PIN_AA9 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[16] ; PIN_AA7 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[17] ; PIN_AB7 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[18] ; PIN_T14 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[19] ; PIN_R14 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[1] ; PIN_AB20 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[20] ; PIN_U12 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[21] ; PIN_T12 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[22] ; PIN_R11 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[23] ; PIN_R12 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[24] ; PIN_U10 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[25] ; PIN_T10 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[26] ; PIN_U9 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[27] ; PIN_T9 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[28] ; PIN_Y7 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[29] ; PIN_U8 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[2] ; PIN_AA19 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[30] ; PIN_V6 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[31] ; PIN_V7 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[3] ; PIN_AB19 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[4] ; PIN_AB18 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[5] ; PIN_AA18 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[6] ; PIN_AA17 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[7] ; PIN_AB17 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[8] ; PIN_Y17 ; QSF Assignment ; -; Location ; ; ; GPIO1_D[9] ; PIN_W17 ; QSF Assignment ; -; Location ; ; ; GPIO_0[0] ; PIN_AB16 ; QSF Assignment ; -; Location ; ; ; GPIO_0[10] ; PIN_AB8 ; QSF Assignment ; -; Location ; ; ; GPIO_0[11] ; PIN_AA8 ; QSF Assignment ; -; Location ; ; ; GPIO_0[12] ; PIN_AB5 ; QSF Assignment ; -; Location ; ; ; GPIO_0[13] ; PIN_AA5 ; QSF Assignment ; -; Location ; ; ; GPIO_0[14] ; PIN_AB4 ; QSF Assignment ; -; Location ; ; ; GPIO_0[15] ; PIN_AA4 ; QSF Assignment ; -; Location ; ; ; GPIO_0[16] ; PIN_V14 ; QSF Assignment ; -; Location ; ; ; GPIO_0[17] ; PIN_U14 ; QSF Assignment ; -; Location ; ; ; GPIO_0[18] ; PIN_Y13 ; QSF Assignment ; -; Location ; ; ; GPIO_0[19] ; PIN_W13 ; QSF Assignment ; -; Location ; ; ; GPIO_0[1] ; PIN_AA16 ; QSF Assignment ; -; Location ; ; ; GPIO_0[20] ; PIN_U13 ; QSF Assignment ; -; Location ; ; ; GPIO_0[21] ; PIN_V12 ; QSF Assignment ; -; Location ; ; ; GPIO_0[22] ; PIN_R10 ; QSF Assignment ; -; Location ; ; ; GPIO_0[23] ; PIN_V11 ; QSF Assignment ; -; Location ; ; ; GPIO_0[24] ; PIN_Y10 ; QSF Assignment ; -; Location ; ; ; GPIO_0[25] ; PIN_W10 ; QSF Assignment ; -; Location ; ; ; GPIO_0[26] ; PIN_T8 ; QSF Assignment ; -; Location ; ; ; GPIO_0[27] ; PIN_V8 ; QSF Assignment ; -; Location ; ; ; GPIO_0[28] ; PIN_W7 ; QSF Assignment ; -; Location ; ; ; GPIO_0[29] ; PIN_W6 ; QSF Assignment ; -; Location ; ; ; GPIO_0[2] ; PIN_AA15 ; QSF Assignment ; -; Location ; ; ; GPIO_0[30] ; PIN_V5 ; QSF Assignment ; -; Location ; ; ; GPIO_0[31] ; PIN_U7 ; QSF Assignment ; -; Location ; ; ; GPIO_0[3] ; PIN_AB15 ; QSF Assignment ; -; Location ; ; ; GPIO_0[4] ; PIN_AA14 ; QSF Assignment ; -; Location ; ; ; GPIO_0[5] ; PIN_AB14 ; QSF Assignment ; -; Location ; ; ; GPIO_0[6] ; PIN_AB13 ; QSF Assignment ; -; Location ; ; ; GPIO_0[7] ; PIN_AA13 ; QSF Assignment ; -; Location ; ; ; GPIO_0[8] ; PIN_AB10 ; QSF Assignment ; -; Location ; ; ; GPIO_0[9] ; PIN_AA10 ; QSF Assignment ; -; Location ; ; ; GPIO_1[0] ; PIN_AA20 ; QSF Assignment ; -; Location ; ; ; GPIO_1[10] ; PIN_U15 ; QSF Assignment ; -; Location ; ; ; GPIO_1[11] ; PIN_T15 ; QSF Assignment ; -; Location ; ; ; GPIO_1[12] ; PIN_W15 ; QSF Assignment ; -; Location ; ; ; GPIO_1[13] ; PIN_V15 ; QSF Assignment ; -; Location ; ; ; GPIO_1[14] ; PIN_AB9 ; QSF Assignment ; -; Location ; ; ; GPIO_1[15] ; PIN_AA9 ; QSF Assignment ; -; Location ; ; ; GPIO_1[16] ; PIN_AA7 ; QSF Assignment ; -; Location ; ; ; GPIO_1[17] ; PIN_AB7 ; QSF Assignment ; -; Location ; ; ; GPIO_1[18] ; PIN_T14 ; QSF Assignment ; -; Location ; ; ; GPIO_1[19] ; PIN_R14 ; QSF Assignment ; -; Location ; ; ; GPIO_1[1] ; PIN_AB20 ; QSF Assignment ; -; Location ; ; ; GPIO_1[20] ; PIN_U12 ; QSF Assignment ; -; Location ; ; ; GPIO_1[21] ; PIN_T12 ; QSF Assignment ; -; Location ; ; ; GPIO_1[22] ; PIN_R11 ; QSF Assignment ; -; Location ; ; ; GPIO_1[23] ; PIN_R12 ; QSF Assignment ; -; Location ; ; ; GPIO_1[24] ; PIN_U10 ; QSF Assignment ; -; Location ; ; ; GPIO_1[25] ; PIN_T10 ; QSF Assignment ; -; Location ; ; ; GPIO_1[26] ; PIN_U9 ; QSF Assignment ; -; Location ; ; ; GPIO_1[27] ; PIN_T9 ; QSF Assignment ; -; Location ; ; ; GPIO_1[28] ; PIN_Y7 ; QSF Assignment ; -; Location ; ; ; GPIO_1[29] ; PIN_U8 ; QSF Assignment ; -; Location ; ; ; GPIO_1[2] ; PIN_AA19 ; QSF Assignment ; -; Location ; ; ; GPIO_1[30] ; PIN_V6 ; QSF Assignment ; -; Location ; ; ; GPIO_1[31] ; PIN_V7 ; QSF Assignment ; -; Location ; ; ; GPIO_1[3] ; PIN_AB19 ; QSF Assignment ; -; Location ; ; ; GPIO_1[4] ; PIN_AB18 ; QSF Assignment ; -; Location ; ; ; GPIO_1[5] ; PIN_AA18 ; QSF Assignment ; -; Location ; ; ; GPIO_1[6] ; PIN_AA17 ; QSF Assignment ; -; Location ; ; ; GPIO_1[7] ; PIN_AB17 ; QSF Assignment ; -; Location ; ; ; GPIO_1[8] ; PIN_Y17 ; QSF Assignment ; -; Location ; ; ; GPIO_1[9] ; PIN_W17 ; QSF Assignment ; -; Location ; ; ; GPIO_CLKIN_N0 ; PIN_AB12 ; QSF Assignment ; -; Location ; ; ; GPIO_CLKIN_N1 ; PIN_AB11 ; QSF Assignment ; -; Location ; ; ; GPIO_CLKIN_P0 ; PIN_AA12 ; QSF Assignment ; -; Location ; ; ; GPIO_CLKIN_P1 ; PIN_AA11 ; QSF Assignment ; -; Location ; ; ; GPIO_CLKOUT_N0 ; PIN_AB3 ; QSF Assignment ; -; Location ; ; ; GPIO_CLKOUT_N1 ; PIN_R16 ; QSF Assignment ; -; Location ; ; ; GPIO_CLKOUT_P0 ; PIN_AA3 ; QSF Assignment ; -; Location ; ; ; GPIO_CLKOUT_P1 ; PIN_T16 ; QSF Assignment ; -; Location ; ; ; HEX0[0] ; PIN_E11 ; QSF Assignment ; -; Location ; ; ; HEX0[1] ; PIN_F11 ; QSF Assignment ; -; Location ; ; ; HEX0[2] ; PIN_H12 ; QSF Assignment ; -; Location ; ; ; HEX0[3] ; PIN_H13 ; QSF Assignment ; -; Location ; ; ; HEX0[4] ; PIN_G12 ; QSF Assignment ; -; Location ; ; ; HEX0[5] ; PIN_F12 ; QSF Assignment ; -; Location ; ; ; HEX0[6] ; PIN_F13 ; QSF Assignment ; -; Location ; ; ; HEX0[7] ; PIN_D13 ; QSF Assignment ; -; Location ; ; ; HEX0_DP ; PIN_D13 ; QSF Assignment ; -; Location ; ; ; HEX1[0] ; PIN_A13 ; QSF Assignment ; -; Location ; ; ; HEX1[1] ; PIN_B13 ; QSF Assignment ; -; Location ; ; ; HEX1[2] ; PIN_C13 ; QSF Assignment ; -; Location ; ; ; HEX1[3] ; PIN_A14 ; QSF Assignment ; -; Location ; ; ; HEX1[4] ; PIN_B14 ; QSF Assignment ; -; Location ; ; ; HEX1[5] ; PIN_E14 ; QSF Assignment ; -; Location ; ; ; HEX1[6] ; PIN_A15 ; QSF Assignment ; -; Location ; ; ; HEX1[7] ; PIN_B15 ; QSF Assignment ; -; Location ; ; ; HEX1_DP ; PIN_B15 ; QSF Assignment ; -; Location ; ; ; HEX1_D[0] ; PIN_A13 ; QSF Assignment ; -; Location ; ; ; HEX1_D[1] ; PIN_B13 ; QSF Assignment ; -; Location ; ; ; HEX1_D[2] ; PIN_C13 ; QSF Assignment ; -; Location ; ; ; HEX1_D[3] ; PIN_A14 ; QSF Assignment ; -; Location ; ; ; HEX1_D[4] ; PIN_B14 ; QSF Assignment ; -; Location ; ; ; HEX1_D[5] ; PIN_E14 ; QSF Assignment ; -; Location ; ; ; HEX1_D[6] ; PIN_A15 ; QSF Assignment ; -; Location ; ; ; HEX2[0] ; PIN_D15 ; QSF Assignment ; -; Location ; ; ; HEX2[1] ; PIN_A16 ; QSF Assignment ; -; Location ; ; ; HEX2[2] ; PIN_B16 ; QSF Assignment ; -; Location ; ; ; HEX2[3] ; PIN_E15 ; QSF Assignment ; -; Location ; ; ; HEX2[4] ; PIN_A17 ; QSF Assignment ; -; Location ; ; ; HEX2[5] ; PIN_B17 ; QSF Assignment ; -; Location ; ; ; HEX2[6] ; PIN_F14 ; QSF Assignment ; -; Location ; ; ; HEX2[7] ; PIN_A18 ; QSF Assignment ; -; Location ; ; ; HEX2_DP ; PIN_A18 ; QSF Assignment ; -; Location ; ; ; HEX2_D[0] ; PIN_D15 ; QSF Assignment ; -; Location ; ; ; HEX2_D[1] ; PIN_A16 ; QSF Assignment ; -; Location ; ; ; HEX2_D[2] ; PIN_B16 ; QSF Assignment ; -; Location ; ; ; HEX2_D[3] ; PIN_E15 ; QSF Assignment ; -; Location ; ; ; HEX2_D[4] ; PIN_A17 ; QSF Assignment ; -; Location ; ; ; HEX2_D[5] ; PIN_B17 ; QSF Assignment ; -; Location ; ; ; HEX2_D[6] ; PIN_F14 ; QSF Assignment ; -; Location ; ; ; HEX3[0] ; PIN_B18 ; QSF Assignment ; -; Location ; ; ; HEX3[1] ; PIN_F15 ; QSF Assignment ; -; Location ; ; ; HEX3[2] ; PIN_A19 ; QSF Assignment ; -; Location ; ; ; HEX3[3] ; PIN_B19 ; QSF Assignment ; -; Location ; ; ; HEX3[4] ; PIN_C19 ; QSF Assignment ; -; Location ; ; ; HEX3[5] ; PIN_D19 ; QSF Assignment ; -; Location ; ; ; HEX3[6] ; PIN_G15 ; QSF Assignment ; -; Location ; ; ; HEX3[7] ; PIN_G16 ; QSF Assignment ; -; Location ; ; ; HEX3_DP ; PIN_G16 ; QSF Assignment ; -; Location ; ; ; HEX3_D[0] ; PIN_B18 ; QSF Assignment ; -; Location ; ; ; HEX3_D[1] ; PIN_F15 ; QSF Assignment ; -; Location ; ; ; HEX3_D[2] ; PIN_A19 ; QSF Assignment ; -; Location ; ; ; HEX3_D[3] ; PIN_B19 ; QSF Assignment ; -; Location ; ; ; HEX3_D[4] ; PIN_C19 ; QSF Assignment ; -; Location ; ; ; HEX3_D[5] ; PIN_D19 ; QSF Assignment ; -; Location ; ; ; HEX3_D[6] ; PIN_G15 ; QSF Assignment ; -; Location ; ; ; KEY[0] ; PIN_H2 ; QSF Assignment ; -; Location ; ; ; KEY[1] ; PIN_G3 ; QSF Assignment ; -; Location ; ; ; KEY[2] ; PIN_F1 ; QSF Assignment ; -; Location ; ; ; LCD_BLON ; PIN_F21 ; QSF Assignment ; -; Location ; ; ; LCD_DATA[0] ; PIN_D22 ; QSF Assignment ; -; Location ; ; ; LCD_DATA[1] ; PIN_D21 ; QSF Assignment ; -; Location ; ; ; LCD_DATA[2] ; PIN_C22 ; QSF Assignment ; -; Location ; ; ; LCD_DATA[3] ; PIN_C21 ; QSF Assignment ; -; Location ; ; ; LCD_DATA[4] ; PIN_B22 ; QSF Assignment ; -; Location ; ; ; LCD_DATA[5] ; PIN_B21 ; QSF Assignment ; -; Location ; ; ; LCD_DATA[6] ; PIN_D20 ; QSF Assignment ; -; Location ; ; ; LCD_DATA[7] ; PIN_C20 ; QSF Assignment ; -; Location ; ; ; LCD_EN ; PIN_E21 ; QSF Assignment ; -; Location ; ; ; LCD_RS ; PIN_F22 ; QSF Assignment ; -; Location ; ; ; LCD_RW ; PIN_E22 ; QSF Assignment ; -; Location ; ; ; PS2_KBCLK ; PIN_P22 ; QSF Assignment ; -; Location ; ; ; PS2_KBDAT ; PIN_P21 ; QSF Assignment ; -; Location ; ; ; SD_CLK ; PIN_Y21 ; QSF Assignment ; -; Location ; ; ; SD_CMD ; PIN_Y22 ; QSF Assignment ; -; Location ; ; ; SD_DAT0 ; PIN_AA22 ; QSF Assignment ; -; Location ; ; ; SD_DAT3 ; PIN_W21 ; QSF Assignment ; -; Location ; ; ; SD_WP_N ; PIN_W20 ; QSF Assignment ; -; Location ; ; ; UART_CTS ; PIN_V21 ; QSF Assignment ; -; Location ; ; ; UART_RTS ; PIN_V22 ; QSF Assignment ; -; Location ; ; ; UART_RXD ; PIN_U22 ; QSF Assignment ; -; Location ; ; ; UART_TXD ; PIN_U21 ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_BA_0 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_BA_1 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_CAS_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_CKE ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_CLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_CS_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_LDQM ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_RAS_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_UDQM ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_WE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[16] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[17] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[18] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[19] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[20] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[21] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_BYTE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_CE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ15_AM1 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_OE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_RST_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_RY ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_WE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_WP_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_CLKIN[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_CLKIN[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_CLKOUT[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_CLKOUT[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[16] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[17] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[18] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[19] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[20] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[21] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[22] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[23] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[24] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[25] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[26] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[27] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[28] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[29] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[30] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[31] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO0_D[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_CLKIN[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_CLKIN[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_CLKOUT[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_CLKOUT[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[16] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[17] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[18] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[19] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[20] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[21] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[22] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[23] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[24] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[25] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[26] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[27] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[28] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[29] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[30] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[31] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO1_D[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX0_DP ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX1_DP ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX1_D[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX1_D[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX1_D[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX1_D[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX1_D[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX1_D[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX1_D[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX2_DP ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX2_D[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX2_D[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX2_D[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX2_D[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX2_D[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX2_D[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX2_D[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX3_DP ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX3_D[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX3_D[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX3_D[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX3_D[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX3_D[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX3_D[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HEX3_D[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LCD_BLON ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LCD_DATA[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LCD_DATA[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LCD_DATA[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LCD_DATA[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LCD_DATA[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LCD_DATA[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LCD_DATA[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LCD_DATA[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LCD_EN ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LCD_RS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LCD_RW ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; PS2_KBCLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; PS2_KBDAT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_CLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_CMD ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_DAT0 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_DAT3 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_WP_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; UART_CTS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; UART_RTS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; UART_RXD ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; UART_TXD ; 3.3-V LVTTL ; QSF Assignment ; -+--------------+----------------+--------------+-----------------+---------------+----------------+ - - -+----------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+---------------------+------------------------+ -; Type ; Value ; -+---------------------+------------------------+ -; Placement (by node) ; ; -; -- Requested ; 0 / 111 ( 0.00 % ) ; -; -- Achieved ; 0 / 111 ( 0.00 % ) ; -; ; ; -; Routing (by net) ; ; -; -- Requested ; 0 / 0 ( 0.00 % ) ; -; -- Achieved ; 0 / 0 ( 0.00 % ) ; -+---------------------+------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Partition Settings ; -+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ -; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; -+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ -; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; -; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; -+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ - - -+------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Placement Preservation ; -+--------------------------------+---------+-------------------+-------------------------+-------------------+ -; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; -+--------------------------------+---------+-------------------+-------------------------+-------------------+ -; Top ; 103 ; 0 ; N/A ; Source File ; -; hard_block:auto_generated_inst ; 8 ; 0 ; N/A ; Source File ; -+--------------------------------+---------+-------------------+-------------------------+-------------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.pin. - - -+-------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+---------------------+ -; Resource ; Usage ; -+---------------------------------------------+---------------------+ -; Total logic elements ; 0 / 15,408 ( 0 % ) ; -; -- Combinational with no register ; 0 ; -; -- Register only ; 0 ; -; -- Combinational with a register ; 0 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 0 ; -; -- 3 input functions ; 0 ; -; -- <=2 input functions ; 0 ; -; -- Register only ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 0 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers* ; 0 / 17,068 ( 0 % ) ; -; -- Dedicated logic registers ; 0 / 15,408 ( 0 % ) ; -; -- I/O registers ; 0 / 1,660 ( 0 % ) ; -; ; ; -; Total LABs: partially or completely used ; 0 / 963 ( 0 % ) ; -; Virtual pins ; 0 ; -; I/O pins ; 51 / 347 ( 15 % ) ; -; -- Clock pins ; 2 / 8 ( 25 % ) ; -; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; -; ; ; -; Global signals ; 0 ; -; M9Ks ; 0 / 56 ( 0 % ) ; -; Total block memory bits ; 0 / 516,096 ( 0 % ) ; -; Total block memory implementation bits ; 0 / 516,096 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; -; PLLs ; 0 / 4 ( 0 % ) ; -; Global clocks ; 0 / 20 ( 0 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; Impedance control blocks ; 0 / 4 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Maximum fan-out ; 1 ; -; Highest non-global fan-out ; 1 ; -; Total fan-out ; 55 ; -; Average fan-out ; 0.50 ; -+---------------------------------------------+---------------------+ -* Register count does not include registers inside RAM blocks or DSP blocks. - - - -+--------------------------------------------------------------------------------------------------+ -; Fitter Partition Statistics ; -+---------------------------------------------+-------------------+--------------------------------+ -; Statistic ; Top ; hard_block:auto_generated_inst ; -+---------------------------------------------+-------------------+--------------------------------+ -; Difficulty Clustering Region ; Low ; Low ; -; ; ; ; -; Total logic elements ; 0 / 15408 ( 0 % ) ; 0 / 15408 ( 0 % ) ; -; -- Combinational with no register ; 0 ; 0 ; -; -- Register only ; 0 ; 0 ; -; -- Combinational with a register ; 0 ; 0 ; -; ; ; ; -; Logic element usage by number of LUT inputs ; ; ; -; -- 4 input functions ; 0 ; 0 ; -; -- 3 input functions ; 0 ; 0 ; -; -- <=2 input functions ; 0 ; 0 ; -; -- Register only ; 0 ; 0 ; -; ; ; ; -; Logic elements by mode ; ; ; -; -- normal mode ; 0 ; 0 ; -; -- arithmetic mode ; 0 ; 0 ; -; ; ; ; -; Total registers ; 0 ; 0 ; -; -- Dedicated logic registers ; 0 / 15408 ( 0 % ) ; 0 / 15408 ( 0 % ) ; -; ; ; ; -; Total LABs: partially or completely used ; 0 / 963 ( 0 % ) ; 0 / 963 ( 0 % ) ; -; ; ; ; -; Virtual pins ; 0 ; 0 ; -; I/O pins ; 51 ; 0 ; -; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ; 0 / 112 ( 0 % ) ; -; Total memory bits ; 0 ; 0 ; -; Total RAM block bits ; 0 ; 0 ; -; ; ; ; -; Connections ; ; ; -; -- Input Connections ; 0 ; 0 ; -; -- Registered Input Connections ; 0 ; 0 ; -; -- Output Connections ; 0 ; 0 ; -; -- Registered Output Connections ; 0 ; 0 ; -; ; ; ; -; Internal Connections ; ; ; -; -- Total Connections ; 51 ; 4 ; -; -- Registered Connections ; 0 ; 0 ; -; ; ; ; -; External Connections ; ; ; -; -- Top ; 0 ; 0 ; -; -- hard_block:auto_generated_inst ; 0 ; 0 ; -; ; ; ; -; Partition Interface ; ; ; -; -- Input Ports ; 17 ; 0 ; -; -- Output Ports ; 34 ; 0 ; -; -- Bidir Ports ; 0 ; 0 ; -; ; ; ; -; Registered Ports ; ; ; -; -- Registered Input Ports ; 0 ; 0 ; -; -- Registered Output Ports ; 0 ; 0 ; -; ; ; ; -; Port Connectivity ; ; ; -; -- Input Ports driven by GND ; 0 ; 0 ; -; -- Output Ports driven by GND ; 0 ; 0 ; -; -- Input Ports driven by VCC ; 0 ; 0 ; -; -- Output Ports driven by VCC ; 0 ; 0 ; -; -- Input Ports with no Source ; 0 ; 0 ; -; -- Output Ports with no Source ; 0 ; 0 ; -; -- Input Ports with no Fanout ; 0 ; 0 ; -; -- Output Ports with no Fanout ; 0 ; 0 ; -+---------------------------------------------+-------------------+--------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; -+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ -; BUTTON[0] ; H2 ; 1 ; 0 ; 21 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; BUTTON[1] ; G3 ; 1 ; 0 ; 23 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; BUTTON[2] ; F1 ; 1 ; 0 ; 23 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; CLOCK_50 ; G21 ; 6 ; 41 ; 15 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; CLOCK_50_2 ; B12 ; 7 ; 19 ; 29 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; PS2_MSCLK ; R21 ; 5 ; 41 ; 10 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; PS2_MSDAT ; R22 ; 5 ; 41 ; 10 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SW[0] ; J6 ; 1 ; 0 ; 24 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SW[1] ; H5 ; 1 ; 0 ; 27 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SW[2] ; H6 ; 1 ; 0 ; 25 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SW[3] ; G4 ; 1 ; 0 ; 23 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SW[4] ; G5 ; 1 ; 0 ; 27 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SW[5] ; J7 ; 1 ; 0 ; 22 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SW[6] ; H7 ; 1 ; 0 ; 25 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SW[7] ; E3 ; 1 ; 0 ; 26 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SW[8] ; E4 ; 1 ; 0 ; 26 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SW[9] ; D2 ; 1 ; 0 ; 25 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; -+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ -; HEX0_D[0] ; E11 ; 7 ; 21 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[1] ; F11 ; 7 ; 21 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[2] ; H12 ; 7 ; 26 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[3] ; H13 ; 7 ; 28 ; 29 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[4] ; G12 ; 7 ; 26 ; 29 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[5] ; F12 ; 7 ; 28 ; 29 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX0_D[6] ; F13 ; 7 ; 26 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LEDG[0] ; J1 ; 1 ; 0 ; 20 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LEDG[1] ; J2 ; 1 ; 0 ; 20 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LEDG[2] ; J3 ; 1 ; 0 ; 21 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LEDG[3] ; H1 ; 1 ; 0 ; 21 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LEDG[4] ; F2 ; 1 ; 0 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LEDG[5] ; E1 ; 1 ; 0 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LEDG[6] ; C1 ; 1 ; 0 ; 26 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LEDG[7] ; C2 ; 1 ; 0 ; 26 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LEDG[8] ; B2 ; 1 ; 0 ; 27 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LEDG[9] ; B1 ; 1 ; 0 ; 27 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_BLANK ; AA15 ; 4 ; 26 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; VGA_B[0] ; K22 ; 6 ; 41 ; 19 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_B[1] ; K21 ; 6 ; 41 ; 19 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_B[2] ; J22 ; 6 ; 41 ; 19 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_B[3] ; K18 ; 6 ; 41 ; 21 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_CLK ; AB9 ; 3 ; 16 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; VGA_G[0] ; H22 ; 6 ; 41 ; 20 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_G[1] ; J17 ; 6 ; 41 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_G[2] ; K17 ; 6 ; 41 ; 21 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_G[3] ; J21 ; 6 ; 41 ; 20 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_HS ; L21 ; 6 ; 41 ; 18 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_R[0] ; H19 ; 6 ; 41 ; 23 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_R[1] ; H17 ; 6 ; 41 ; 25 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_R[2] ; H20 ; 6 ; 41 ; 22 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_R[3] ; H21 ; 6 ; 41 ; 21 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; VGA_SYNC ; A10 ; 8 ; 16 ; 29 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; -; VGA_VS ; L22 ; 6 ; 41 ; 18 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Dual Purpose and Dedicated Pins ; -+----------+---------------------------------------+--------------------------+-------------------------+---------------------------+ -; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; -+----------+---------------------------------------+--------------------------+-------------------------+---------------------------+ -; E4 ; DIFFIO_L2p, nRESET ; Use as regular IO ; SW[8] ; Dual Purpose Pin ; -; D1 ; DIFFIO_L4n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; -; E2 ; DIFFIO_L6p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; -; K6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; -; K2 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; -; K1 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; -; K5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; -; L3 ; nCE ; - ; - ; Dedicated Programming Pin ; -; M18 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; -; M17 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; -; L18 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; -; L17 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; -; K20 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; -; L22 ; DIFFIO_R17n, INIT_DONE ; Use as regular IO ; VGA_VS ; Dual Purpose Pin ; -; L21 ; DIFFIO_R17p, CRC_ERROR ; Use as regular IO ; VGA_HS ; Dual Purpose Pin ; -; K22 ; DIFFIO_R16n, nCEO ; Use as programming pin ; VGA_B[0] ; Dual Purpose Pin ; -; K21 ; DIFFIO_R16p, CLKUSR ; Use as regular IO ; VGA_B[1] ; Dual Purpose Pin ; -; F13 ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8 ; Use as regular IO ; HEX0_D[6] ; Dual Purpose Pin ; -; E11 ; DIFFIO_T16n, PADD13 ; Use as regular IO ; HEX0_D[0] ; Dual Purpose Pin ; -; F11 ; DIFFIO_T16p, PADD14 ; Use as regular IO ; HEX0_D[1] ; Dual Purpose Pin ; -+----------+---------------------------------------+--------------------------+-------------------------+---------------------------+ - - -+------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+------------------+---------------+--------------+ -; 1 ; 27 / 33 ( 82 % ) ; 3.3V ; -- ; -; 2 ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; -; 3 ; 1 / 46 ( 2 % ) ; 2.5V ; -- ; -; 4 ; 1 / 41 ( 2 % ) ; 2.5V ; -- ; -; 5 ; 2 / 46 ( 4 % ) ; 3.3V ; -- ; -; 6 ; 15 / 43 ( 35 % ) ; 3.3V ; -- ; -; 7 ; 8 / 47 ( 17 % ) ; 3.3V ; -- ; -; 8 ; 1 / 43 ( 2 % ) ; 2.5V ; -- ; -+----------+------------------+---------------+--------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A3 ; 354 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A4 ; 350 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A5 ; 345 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A6 ; 336 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A7 ; 334 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A8 ; 332 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A9 ; 328 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A10 ; 326 ; 8 ; VGA_SYNC ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; A11 ; 321 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; A12 ; 319 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; A13 ; 314 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A14 ; 312 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A15 ; 307 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A16 ; 298 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A17 ; 296 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A18 ; 291 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A19 ; 290 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A20 ; 284 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA1 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA3 ; 102 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA4 ; 106 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA5 ; 108 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AA7 ; 115 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA8 ; 123 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA9 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA10 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA11 ; 134 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AA12 ; 136 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AA13 ; 138 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA14 ; 140 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA15 ; 145 ; 4 ; VGA_BLANK ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AA16 ; 149 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA17 ; 151 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA18 ; 163 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA19 ; 164 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA20 ; 169 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA21 ; 179 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA22 ; 178 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AB2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AB3 ; 103 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB4 ; 107 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB5 ; 109 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AB7 ; 116 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB8 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB9 ; 127 ; 3 ; VGA_CLK ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; -; AB10 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB11 ; 135 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AB12 ; 137 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AB13 ; 139 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB14 ; 141 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB15 ; 146 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB16 ; 150 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB17 ; 152 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB18 ; 162 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB19 ; 165 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB20 ; 170 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB21 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B1 ; 2 ; 1 ; LEDG[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; B2 ; 1 ; 1 ; LEDG[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; B3 ; 355 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B4 ; 351 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B5 ; 346 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B6 ; 337 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B7 ; 335 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B8 ; 333 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B9 ; 329 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B10 ; 327 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B11 ; 322 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; B12 ; 320 ; 7 ; CLOCK_50_2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B13 ; 315 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B14 ; 313 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B15 ; 308 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B16 ; 299 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B17 ; 297 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B18 ; 292 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B19 ; 289 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B20 ; 285 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B21 ; 269 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; B22 ; 268 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; C1 ; 7 ; 1 ; LEDG[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; C2 ; 6 ; 1 ; LEDG[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; C3 ; 358 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C4 ; 359 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C6 ; 349 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C7 ; 340 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C8 ; 339 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C10 ; 330 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C13 ; 309 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C15 ; 300 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C17 ; 286 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C19 ; 282 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C20 ; 270 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; C21 ; 267 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; C22 ; 266 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; D1 ; 9 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; D2 ; 8 ; 1 ; SW[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; D4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; D6 ; 356 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; D8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; D9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; D10 ; 324 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; D12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D13 ; 310 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D15 ; 293 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D17 ; 281 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; D18 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D19 ; 283 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D20 ; 271 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; D21 ; 261 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; D22 ; 260 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E1 ; 14 ; 1 ; LEDG[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; E2 ; 13 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; E3 ; 5 ; 1 ; SW[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; E4 ; 4 ; 1 ; SW[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; E5 ; 363 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E6 ; 362 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E7 ; 357 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E8 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E9 ; 338 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; E10 ; 325 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E11 ; 317 ; 7 ; HEX0_D[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; E12 ; 316 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E13 ; 311 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E14 ; 301 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E15 ; 294 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E16 ; 275 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; E18 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; -; E19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; E20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; E21 ; 256 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E22 ; 255 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F1 ; 16 ; 1 ; BUTTON[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; F2 ; 15 ; 1 ; LEDG[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; F5 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; -; F6 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; F7 ; 360 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F8 ; 352 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F9 ; 347 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F10 ; 348 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F11 ; 318 ; 7 ; HEX0_D[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; F12 ; 302 ; 7 ; HEX0_D[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; F13 ; 306 ; 7 ; HEX0_D[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; F14 ; 279 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F15 ; 276 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F16 ; 274 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F17 ; 272 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F18 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; F19 ; 263 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F20 ; 262 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F21 ; 251 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F22 ; 250 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G1 ; 39 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; G2 ; 38 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; G3 ; 18 ; 1 ; BUTTON[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; G4 ; 17 ; 1 ; SW[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; G5 ; 3 ; 1 ; SW[4] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; G6 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; G7 ; 361 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G8 ; 353 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G9 ; 342 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G10 ; 341 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G11 ; 331 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G12 ; 305 ; 7 ; HEX0_D[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; G13 ; 295 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G14 ; 280 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G15 ; 278 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G16 ; 277 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G17 ; 273 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G18 ; 264 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; G20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; G21 ; 226 ; 6 ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; G22 ; 225 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; H1 ; 26 ; 1 ; LEDG[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H2 ; 25 ; 1 ; BUTTON[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; H4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; H5 ; 0 ; 1 ; SW[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H6 ; 11 ; 1 ; SW[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H7 ; 10 ; 1 ; SW[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; H9 ; 344 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H10 ; 343 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H11 ; 323 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H12 ; 304 ; 7 ; HEX0_D[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; H13 ; 303 ; 7 ; HEX0_D[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; H14 ; 288 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H15 ; 287 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H16 ; 259 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H17 ; 265 ; 6 ; VGA_R[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H18 ; 257 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; H19 ; 254 ; 6 ; VGA_R[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H20 ; 253 ; 6 ; VGA_R[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H21 ; 246 ; 6 ; VGA_R[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H22 ; 245 ; 6 ; VGA_G[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J1 ; 29 ; 1 ; LEDG[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J2 ; 28 ; 1 ; LEDG[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J3 ; 27 ; 1 ; LEDG[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J4 ; 24 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J6 ; 12 ; 1 ; SW[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J7 ; 22 ; 1 ; SW[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J15 ; 238 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J16 ; 243 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J17 ; 258 ; 6 ; VGA_G[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J18 ; 249 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; J21 ; 242 ; 6 ; VGA_G[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J22 ; 241 ; 6 ; VGA_B[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K1 ; 31 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; K2 ; 30 ; 1 ; ~ALTERA_DCLK~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; K5 ; 32 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; K6 ; 19 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; -; K7 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K8 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K15 ; 236 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K16 ; 244 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K17 ; 247 ; 6 ; VGA_G[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K18 ; 248 ; 6 ; VGA_B[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K19 ; 237 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; K20 ; 231 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; -; K21 ; 240 ; 6 ; VGA_B[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K22 ; 239 ; 6 ; VGA_B[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L1 ; 35 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; L2 ; 34 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; L3 ; 37 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -; L4 ; 36 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; L5 ; 33 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; L6 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L7 ; 50 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L8 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L15 ; 233 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L16 ; 232 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L17 ; 230 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; -; L18 ; 229 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; -; L19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; L20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L21 ; 235 ; 6 ; VGA_HS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L22 ; 234 ; 6 ; VGA_VS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M1 ; 45 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M2 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M3 ; 47 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M4 ; 46 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M5 ; 51 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; M6 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M7 ; 65 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M8 ; 66 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M15 ; 195 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M16 ; 222 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M17 ; 228 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; M18 ; 227 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; -; M19 ; 221 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M20 ; 220 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M21 ; 219 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M22 ; 218 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N1 ; 49 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N2 ; 48 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; N5 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N6 ; 64 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N7 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N8 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N14 ; 189 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N15 ; 196 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N16 ; 205 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N17 ; 214 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N18 ; 215 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N19 ; 213 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N20 ; 212 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N21 ; 217 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N22 ; 216 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P1 ; 53 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P2 ; 52 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P3 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P4 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P5 ; 63 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P6 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P7 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P8 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P14 ; 180 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P15 ; 192 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P16 ; 193 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P17 ; 197 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P18 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P20 ; 208 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; P21 ; 211 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P22 ; 210 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R1 ; 55 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R2 ; 54 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; R5 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R6 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R7 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R8 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R9 ; 88 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R10 ; 90 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R11 ; 97 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R12 ; 98 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R13 ; 153 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R14 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R15 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R16 ; 172 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R17 ; 194 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; R18 ; 203 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R19 ; 204 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R20 ; 200 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R21 ; 207 ; 5 ; PS2_MSCLK ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; R22 ; 206 ; 5 ; PS2_MSDAT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; T1 ; 41 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; T2 ; 40 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; T3 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; T4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T5 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T6 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; T7 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T8 ; 89 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T9 ; 91 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T10 ; 121 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T11 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T12 ; 148 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T14 ; 160 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T15 ; 161 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T16 ; 171 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T17 ; 181 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T18 ; 182 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T21 ; 224 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; T22 ; 223 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; U1 ; 60 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U2 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; U5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; -; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U7 ; 94 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U8 ; 95 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U9 ; 112 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U10 ; 122 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U11 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U12 ; 147 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U13 ; 156 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U14 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U15 ; 173 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U18 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; U19 ; 188 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U20 ; 187 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U21 ; 202 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U22 ; 201 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V1 ; 62 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V2 ; 61 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V3 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V4 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V5 ; 93 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V6 ; 92 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V7 ; 105 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V8 ; 113 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V9 ; 119 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; V10 ; 120 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V11 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V12 ; 142 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V13 ; 154 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V14 ; 157 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V15 ; 158 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V16 ; 168 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; V17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V18 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; -; V19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V21 ; 199 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V22 ; 198 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W1 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W2 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W4 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W6 ; 104 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W7 ; 110 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W8 ; 114 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W10 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W13 ; 143 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W14 ; 155 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; W15 ; 159 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W17 ; 166 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; W18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W19 ; 184 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W20 ; 183 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W21 ; 191 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W22 ; 190 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y1 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y2 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y3 ; 99 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y4 ; 96 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y6 ; 101 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y7 ; 111 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y8 ; 117 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y10 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y13 ; 144 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y17 ; 167 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y21 ; 186 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y22 ; 185 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -; |ise_proj ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 51 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |ise_proj ; work ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+--------------------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+------------+----------+---------------+---------------+-----------------------+-----+------+ -; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; -+------------+----------+---------------+---------------+-----------------------+-----+------+ -; VGA_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_SYNC ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_BLANK ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_VS ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_HS ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0_D[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0_D[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0_D[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0_D[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0_D[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0_D[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0_D[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_B[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_B[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_B[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_B[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_G[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_G[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_G[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_G[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_R[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_R[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_R[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VGA_R[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; PS2_MSDAT ; Input ; -- ; -- ; -- ; -- ; -- ; -; PS2_MSCLK ; Input ; -- ; -- ; -- ; -- ; -- ; -; CLOCK_50 ; Input ; -- ; -- ; -- ; -- ; -- ; -; CLOCK_50_2 ; Input ; -- ; -- ; -- ; -- ; -- ; -; BUTTON[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -; BUTTON[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -; BUTTON[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -; SW[9] ; Input ; -- ; -- ; -- ; -- ; -- ; -; SW[8] ; Input ; -- ; -- ; -- ; -- ; -- ; -; SW[7] ; Input ; -- ; -- ; -- ; -- ; -- ; -; SW[6] ; Input ; -- ; -- ; -- ; -- ; -- ; -; SW[5] ; Input ; -- ; -- ; -- ; -- ; -- ; -; SW[4] ; Input ; -- ; -- ; -- ; -- ; -- ; -; SW[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -; SW[2] ; Input ; -- ; -- ; -- ; -- ; -- ; -; SW[1] ; Input ; -- ; -- ; -- ; -- ; -- ; -; SW[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -+------------+----------+---------------+---------------+-----------------------+-----+------+ - - -+---------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+---------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+---------------------+-------------------+---------+ -; PS2_MSDAT ; ; ; -; PS2_MSCLK ; ; ; -; CLOCK_50 ; ; ; -; CLOCK_50_2 ; ; ; -; BUTTON[2] ; ; ; -; BUTTON[1] ; ; ; -; BUTTON[0] ; ; ; -; SW[9] ; ; ; -; SW[8] ; ; ; -; SW[7] ; ; ; -; SW[6] ; ; ; -; SW[5] ; ; ; -; SW[4] ; ; ; -; SW[3] ; ; ; -; SW[2] ; ; ; -; SW[1] ; ; ; -; SW[0] ; ; ; -+---------------------+-------------------+---------+ - - -+--------------------------------------------------+ -; Other Routing Usage Summary ; -+-----------------------------+--------------------+ -; Other Routing Resource Type ; Usage ; -+-----------------------------+--------------------+ -; Block interconnects ; 0 / 47,787 ( 0 % ) ; -; C16 interconnects ; 0 / 1,804 ( 0 % ) ; -; C4 interconnects ; 0 / 31,272 ( 0 % ) ; -; Global clocks ; 0 / 20 ( 0 % ) ; -; Local interconnects ; 0 / 15,408 ( 0 % ) ; -; R24 interconnects ; 0 / 1,775 ( 0 % ) ; -; R4 interconnects ; 0 / 41,310 ( 0 % ) ; -+-----------------------------+--------------------+ - - -+------------------------------------------+ -; I/O Rules Summary ; -+----------------------------------+-------+ -; I/O Rules Statistic ; Total ; -+----------------------------------+-------+ -; Total I/O Rules ; 30 ; -; Number of I/O Rules Passed ; 12 ; -; Number of I/O Rules Failed ; 0 ; -; Number of I/O Rules Unchecked ; 0 ; -; Number of I/O Rules Inapplicable ; 18 ; -+----------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Details ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; -; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; -; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; -; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; -; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; -; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; -; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; -; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Matrix ; -+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ -; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; -+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ -; Total Pass ; 48 ; 0 ; 48 ; 0 ; 0 ; 51 ; 48 ; 0 ; 51 ; 51 ; 0 ; 3 ; 0 ; 0 ; 17 ; 0 ; 3 ; 17 ; 0 ; 0 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 51 ; 0 ; 0 ; -; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 3 ; 51 ; 3 ; 51 ; 51 ; 0 ; 3 ; 51 ; 0 ; 0 ; 51 ; 48 ; 51 ; 51 ; 34 ; 51 ; 48 ; 34 ; 51 ; 51 ; 51 ; 48 ; 51 ; 51 ; 51 ; 51 ; 51 ; 0 ; 51 ; 51 ; -; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; VGA_CLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_SYNC ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_BLANK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_VS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_HS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0_D[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0_D[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0_D[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0_D[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0_D[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0_D[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0_D[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_B[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_B[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_B[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_B[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_G[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_G[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_G[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_G[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_R[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_R[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_R[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VGA_R[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; PS2_MSDAT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; PS2_MSCLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; CLOCK_50_2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; BUTTON[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; BUTTON[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; BUTTON[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ - - -+---------------------------------------------------------------------------------------------+ -; Fitter Device Options ; -+------------------------------------------------------------------+--------------------------+ -; Option ; Setting ; -+------------------------------------------------------------------+--------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Active Serial ; -; Error detection CRC ; Off ; -; Enable open drain on CRC_ERROR pin ; Off ; -; Enable input tri-state on active configuration pins in user mode ; Off ; -; Configuration Voltage Level ; Auto ; -; Force Configuration Voltage Level ; On ; -; nCEO ; Unreserved ; -; Data[0] ; As input tri-stated ; -; Data[1]/ASDO ; As input tri-stated ; -; Data[7..2] ; Unreserved ; -; FLASH_nCE/nCSO ; As input tri-stated ; -; Other Active Parallel pins ; Unreserved ; -; DCLK ; As output driving ground ; -; Base pin-out file on sameframe device ; Off ; -+------------------------------------------------------------------+--------------------------+ - - -+------------------------------------+ -; Operating Settings and Conditions ; -+---------------------------+--------+ -; Setting ; Value ; -+---------------------------+--------+ -; Nominal Core Voltage ; 1.20 V ; -; Low Junction Temperature ; 0 °C ; -; High Junction Temperature ; 85 °C ; -+---------------------------+--------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. -Info (119006): Selected device EP3C16F484C6 for design "ise_proj" -Info (21077): Core supply voltage is 1.2V -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 85 degrees C -Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info (176445): Device EP3C40F484C6 is compatible - Info (176445): Device EP3C55F484C6 is compatible - Info (176445): Device EP3C80F484C6 is compatible -Info (169124): Fitter converted 4 user pins into dedicated programming pins - Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 - Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 - Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2 - Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1 -Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details -Critical Warning (169085): No exact pin location assignment(s) for 3 pins of 51 total pins - Info (169086): Pin VGA_CLK not assigned to an exact location on the device - Info (169086): Pin VGA_SYNC not assigned to an exact location on the device - Info (169086): Pin VGA_BLANK not assigned to an exact location on the device -Critical Warning (332012): Synopsys Design Constraints File file not found: 'ise_proj.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. -Info (332144): No user constrained base clocks found in the design -Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. -Warning (332068): No clocks defined in design. -Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" -Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. -Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. -Info (176233): Starting register packing -Info (176235): Finished register packing - Extra Info (176219): No registers were packed into other blocks -Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement - Info (176211): Number of I/O pins in group: 3 (unused VREF, 2.5V VCCIO, 0 input, 3 output, 0 bidirectional) - Info (176212): I/O standards used: 2.5 V. -Info (176215): I/O bank details before I/O pin placement - Info (176214): Statistics of I/O banks - Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used -- 6 pins available - Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available - Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available - Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available - Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 44 pins available - Info (176213): I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used -- 28 pins available - Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used -- 39 pins available - Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available -Warning (15709): Ignored I/O standard assignments to the following nodes - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[0]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[10]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[11]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[12]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[1]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[2]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[3]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[4]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[5]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[6]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[7]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[8]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[9]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_BA_0" - Warning (15710): Ignored I/O standard assignment to node "DRAM_BA_1" - Warning (15710): Ignored I/O standard assignment to node "DRAM_CAS_N" - Warning (15710): Ignored I/O standard assignment to node "DRAM_CKE" - Warning (15710): Ignored I/O standard assignment to node "DRAM_CLK" - Warning (15710): Ignored I/O standard assignment to node "DRAM_CS_N" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[0]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[10]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[11]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[12]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[13]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[14]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[15]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[1]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[2]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[3]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[4]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[5]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[6]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[7]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[8]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[9]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_LDQM" - Warning (15710): Ignored I/O standard assignment to node "DRAM_RAS_N" - Warning (15710): Ignored I/O standard assignment to node "DRAM_UDQM" - Warning (15710): Ignored I/O standard assignment to node "DRAM_WE_N" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[0]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[10]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[11]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[12]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[13]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[14]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[15]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[16]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[17]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[18]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[19]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[1]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[20]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[21]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[2]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[3]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[4]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[5]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[6]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[7]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[8]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[9]" - Warning (15710): Ignored I/O standard assignment to node "FL_BYTE_N" - Warning (15710): Ignored I/O standard assignment to node "FL_CE_N" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ15_AM1" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[0]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[10]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[11]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[12]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[13]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[14]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[1]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[2]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[3]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[4]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[5]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[6]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[7]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[8]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[9]" - Warning (15710): Ignored I/O standard assignment to node "FL_OE_N" - Warning (15710): Ignored I/O standard assignment to node "FL_RST_N" - Warning (15710): Ignored I/O standard assignment to node "FL_RY" - Warning (15710): Ignored I/O standard assignment to node "FL_WE_N" - Warning (15710): Ignored I/O standard assignment to node "FL_WP_N" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKIN[0]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKIN[1]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKOUT[0]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKOUT[1]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[0]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[10]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[11]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[12]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[13]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[14]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[15]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[16]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[17]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[18]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[19]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[1]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[20]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[21]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[22]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[23]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[24]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[25]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[26]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[27]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[28]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[29]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[2]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[30]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[31]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[3]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[4]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[5]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[6]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[7]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[8]" - Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[9]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKIN[0]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKIN[1]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKOUT[0]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKOUT[1]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[0]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[10]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[11]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[12]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[13]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[14]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[15]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[16]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[17]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[18]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[19]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[1]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[20]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[21]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[22]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[23]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[24]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[25]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[26]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[27]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[28]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[29]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[2]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[30]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[31]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[3]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[4]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[5]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[6]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[7]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[8]" - Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[9]" - Warning (15710): Ignored I/O standard assignment to node "HEX0_DP" - Warning (15710): Ignored I/O standard assignment to node "HEX1_DP" - Warning (15710): Ignored I/O standard assignment to node "HEX1_D[0]" - Warning (15710): Ignored I/O standard assignment to node "HEX1_D[1]" - Warning (15710): Ignored I/O standard assignment to node "HEX1_D[2]" - Warning (15710): Ignored I/O standard assignment to node "HEX1_D[3]" - Warning (15710): Ignored I/O standard assignment to node "HEX1_D[4]" - Warning (15710): Ignored I/O standard assignment to node "HEX1_D[5]" - Warning (15710): Ignored I/O standard assignment to node "HEX1_D[6]" - Warning (15710): Ignored I/O standard assignment to node "HEX2_DP" - Warning (15710): Ignored I/O standard assignment to node "HEX2_D[0]" - Warning (15710): Ignored I/O standard assignment to node "HEX2_D[1]" - Warning (15710): Ignored I/O standard assignment to node "HEX2_D[2]" - Warning (15710): Ignored I/O standard assignment to node "HEX2_D[3]" - Warning (15710): Ignored I/O standard assignment to node "HEX2_D[4]" - Warning (15710): Ignored I/O standard assignment to node "HEX2_D[5]" - Warning (15710): Ignored I/O standard assignment to node "HEX2_D[6]" - Warning (15710): Ignored I/O standard assignment to node "HEX3_DP" - Warning (15710): Ignored I/O standard assignment to node "HEX3_D[0]" - Warning (15710): Ignored I/O standard assignment to node "HEX3_D[1]" - Warning (15710): Ignored I/O standard assignment to node "HEX3_D[2]" - Warning (15710): Ignored I/O standard assignment to node "HEX3_D[3]" - Warning (15710): Ignored I/O standard assignment to node "HEX3_D[4]" - Warning (15710): Ignored I/O standard assignment to node "HEX3_D[5]" - Warning (15710): Ignored I/O standard assignment to node "HEX3_D[6]" - Warning (15710): Ignored I/O standard assignment to node "LCD_BLON" - Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[4]" - Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[5]" - Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[6]" - Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[7]" - Warning (15710): Ignored I/O standard assignment to node "LCD_EN" - Warning (15710): Ignored I/O standard assignment to node "LCD_RS" - Warning (15710): Ignored I/O standard assignment to node "LCD_RW" - Warning (15710): Ignored I/O standard assignment to node "PS2_KBCLK" - Warning (15710): Ignored I/O standard assignment to node "PS2_KBDAT" - Warning (15710): Ignored I/O standard assignment to node "SD_CLK" - Warning (15710): Ignored I/O standard assignment to node "SD_CMD" - Warning (15710): Ignored I/O standard assignment to node "SD_DAT0" - Warning (15710): Ignored I/O standard assignment to node "SD_DAT3" - Warning (15710): Ignored I/O standard assignment to node "SD_WP_N" - Warning (15710): Ignored I/O standard assignment to node "UART_CTS" - Warning (15710): Ignored I/O standard assignment to node "UART_RTS" - Warning (15710): Ignored I/O standard assignment to node "UART_RXD" - Warning (15710): Ignored I/O standard assignment to node "UART_TXD" -Warning (15705): Ignored locations or region assignments to the following nodes - Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_BA_0" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_BA_1" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_LDQM" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_UDQM" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_BYTE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ15_AM1" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_CLKIN[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_CLKIN[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_CLKOUT[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_CLKOUT[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[22]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[23]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[24]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[25]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[26]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[27]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[28]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[29]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[30]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[31]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO0_D[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_CLKIN[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_CLKIN[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_CLKOUT[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_CLKOUT[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[22]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[23]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[24]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[25]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[26]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[27]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[28]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[29]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[30]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[31]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO1_D[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[22]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[23]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[24]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[25]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[26]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[27]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[28]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[29]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[30]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[31]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_0[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[22]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[23]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[24]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[25]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[26]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[27]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[28]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[29]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[30]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[31]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_1[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_CLKIN_N0" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_CLKIN_N1" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_CLKIN_P0" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_CLKIN_P1" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_CLKOUT_N0" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_CLKOUT_N1" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_CLKOUT_P0" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO_CLKOUT_P1" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX0[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX0_DP" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1_DP" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1_D[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1_D[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1_D[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1_D[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1_D[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1_D[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX1_D[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2_DP" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2_D[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2_D[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2_D[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2_D[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2_D[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2_D[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX2_D[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3_DP" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3_D[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3_D[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3_D[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3_D[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3_D[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3_D[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HEX3_D[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design - Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design - Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design - Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design - Warning (15706): Node "PS2_KBCLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "PS2_KBDAT" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_DAT0" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_DAT3" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design - Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design - Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design - Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 -Info (170189): Fitter placement preparation operations beginning -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info (170191): Fitter placement operations beginning -Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 -Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 0% of the available device resources - Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29 -Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. - Info (170201): Optimizations that may affect the design's routability were skipped - Info (170200): Optimizations that may affect the design's timing were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds. -Info (334003): Started post-fitting delay annotation -Info (334004): Delay annotation completed successfully -Info (334003): Started post-fitting delay annotation -Info (334004): Delay annotation completed successfully -Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 -Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. -Warning (169177): 17 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. - Info (169178): Pin PS2_MSDAT uses I/O standard 3.3-V LVTTL at R22 - Info (169178): Pin PS2_MSCLK uses I/O standard 3.3-V LVTTL at R21 - Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21 - Info (169178): Pin CLOCK_50_2 uses I/O standard 3.3-V LVTTL at B12 - Info (169178): Pin BUTTON[2] uses I/O standard 3.3-V LVTTL at F1 - Info (169178): Pin BUTTON[1] uses I/O standard 3.3-V LVTTL at G3 - Info (169178): Pin BUTTON[0] uses I/O standard 3.3-V LVTTL at H2 - Info (169178): Pin SW[9] uses I/O standard 3.3-V LVTTL at D2 - Info (169178): Pin SW[8] uses I/O standard 3.3-V LVTTL at E4 - Info (169178): Pin SW[7] uses I/O standard 3.3-V LVTTL at E3 - Info (169178): Pin SW[6] uses I/O standard 3.3-V LVTTL at H7 - Info (169178): Pin SW[5] uses I/O standard 3.3-V LVTTL at J7 - Info (169178): Pin SW[4] uses I/O standard 3.3-V LVTTL at G5 - Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at G4 - Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at H6 - Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at H5 - Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at J6 -Info (144001): Generated suppressed messages file C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg -Info: Quartus II 64-Bit Fitter was successful. 0 errors, 525 warnings - Info: Peak virtual memory: 1054 megabytes - Info: Processing ended: Tue Mar 01 16:05:11 2016 - Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:05 - - -+----------------------------+ -; Fitter Suppressed Messages ; -+----------------------------+ -The suppressed messages can be found in C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg. - - |