1 files changed, 429 insertions, 0 deletions
diff --git a/dot_product/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v b/dot_product/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v
new file mode 100644
index 0000000..9ff387e
--- /dev/null
+++ b/dot_product/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v
@@ -0,0 +1,429 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   rad09@EE-RAD09-02
+//  Generated date: Wed Mar 06 21:47:19 2013
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    mean_vga_core
+// ------------------------------------------------------------------
+
+
+module mean_vga_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] slc_regs_regs_2_1_itm;
+  reg [9:0] slc_regs_regs_2_2_itm;
+  reg [9:0] slc_regs_regs_2_itm;
+  reg [9:0] slc_regs_regs_2_4_itm;
+  reg [9:0] slc_regs_regs_2_5_itm;
+  reg [9:0] slc_regs_regs_2_3_itm;
+  reg [9:0] slc_regs_regs_2_7_itm;
+  reg [9:0] slc_regs_regs_2_8_itm;
+  reg [9:0] slc_regs_regs_2_6_itm;
+  reg [89:0] reg_regs_regs_0_sva_cse;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  wire [11:0] nl_reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_1;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_2;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_3;
+  wire [13:0] ACC_acc_psp_sva;
+  wire [14:0] nl_ACC_acc_psp_sva;
+  wire [5:0] acc_imod_sva;
+  wire [6:0] nl_acc_imod_sva;
+  wire [11:0] acc_9_psp_sva;
+  wire [12:0] nl_acc_9_psp_sva;
+  wire [11:0] acc_14_psp_sva;
+  wire [12:0] nl_acc_14_psp_sva;
+  wire [13:0] ACC_acc_21_psp_sva;
+  wire [14:0] nl_ACC_acc_21_psp_sva;
+  wire [5:0] acc_imod_4_sva;
+  wire [6:0] nl_acc_imod_4_sva;
+  wire [3:0] acc_29_sdt;
+  wire [4:0] nl_acc_29_sdt;
+  wire [13:0] ACC_acc_20_psp_sva;
+  wire [14:0] nl_ACC_acc_20_psp_sva;
+  wire [5:0] acc_imod_2_sva;
+  wire [6:0] nl_acc_imod_2_sva;
+  wire [3:0] acc_19_sdt;
+  wire [4:0] nl_acc_19_sdt;
+  wire [3:0] acc_15_sdt;
+  wire [4:0] nl_acc_15_sdt;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign vout_rsc_mgc_out_stdreg_d = {reg_vout_rsc_mgc_out_stdreg_d_tmp , reg_vout_rsc_mgc_out_stdreg_d_tmp_1
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_2 , reg_vout_rsc_mgc_out_stdreg_d_tmp_3};
+  assign nl_ACC_acc_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_1_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_2_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[29:20]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[59:50]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[89:80])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[29:20])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[59:50])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[89:80])
+      + conv_u2u_10_11(slc_regs_regs_2_itm)));
+  assign ACC_acc_psp_sva = nl_ACC_acc_psp_sva[13:0];
+  assign nl_acc_imod_sva = conv_s2s_5_6({(({1'b1 , (acc_15_sdt[3:1])}) + 4'b1) ,
+      (acc_15_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_psp_sva[2:0]));
+  assign acc_imod_sva = nl_acc_imod_sva[5:0];
+  assign nl_acc_9_psp_sva = conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_20_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_20_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_2_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_2_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_2_sva[5:3])) , (~ (acc_imod_2_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_2_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_20_psp_sva[8:6])))
+      + ({4'b1001 , (acc_imod_2_sva[5])})))) + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_2_10(ACC_acc_20_psp_sva[13:12])
+      * 10'b100000001));
+  assign acc_9_psp_sva = nl_acc_9_psp_sva[11:0];
+  assign nl_acc_14_psp_sva = conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_21_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_21_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_4_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_4_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_4_sva[5:3])) , (~ (acc_imod_4_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_4_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_21_psp_sva[8:6])))
+      + ({4'b1001 , (acc_imod_4_sva[5])})))) + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_2_10(ACC_acc_21_psp_sva[13:12])
+      * 10'b100000001));
+  assign acc_14_psp_sva = nl_acc_14_psp_sva[11:0];
+  assign nl_ACC_acc_21_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_7_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_8_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[19:10]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[49:40]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[79:70])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[19:10])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[49:40])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[79:70])
+      + conv_u2u_10_11(slc_regs_regs_2_6_itm)));
+  assign ACC_acc_21_psp_sva = nl_ACC_acc_21_psp_sva[13:0];
+  assign nl_acc_imod_4_sva = conv_s2s_5_6({(({1'b1 , (acc_29_sdt[3:1])}) + 4'b1)
+      , (acc_29_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_21_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_21_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_21_psp_sva[2:0]));
+  assign acc_imod_4_sva = nl_acc_imod_4_sva[5:0];
+  assign nl_acc_29_sdt = conv_u2u_3_4(~ (ACC_acc_21_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_21_psp_sva[8:6]);
+  assign acc_29_sdt = nl_acc_29_sdt[3:0];
+  assign nl_ACC_acc_20_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_4_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_5_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[9:0]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[39:30]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[69:60])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[9:0])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[39:30])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[69:60])
+      + conv_u2u_10_11(slc_regs_regs_2_3_itm)));
+  assign ACC_acc_20_psp_sva = nl_ACC_acc_20_psp_sva[13:0];
+  assign nl_acc_imod_2_sva = conv_s2s_5_6({(({1'b1 , (acc_19_sdt[3:1])}) + 4'b1)
+      , (acc_19_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_20_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_20_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_20_psp_sva[2:0]));
+  assign acc_imod_2_sva = nl_acc_imod_2_sva[5:0];
+  assign nl_acc_19_sdt = conv_u2u_3_4(~ (ACC_acc_20_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_20_psp_sva[8:6]);
+  assign acc_19_sdt = nl_acc_19_sdt[3:0];
+  assign nl_acc_15_sdt = conv_u2u_3_4(~ (ACC_acc_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_psp_sva[8:6]);
+  assign acc_15_sdt = nl_acc_15_sdt[3:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      slc_regs_regs_2_7_itm <= 10'b0;
+      slc_regs_regs_2_8_itm <= 10'b0;
+      reg_regs_regs_0_sva_cse <= 90'b0;
+      slc_regs_regs_2_6_itm <= 10'b0;
+      slc_regs_regs_2_4_itm <= 10'b0;
+      slc_regs_regs_2_5_itm <= 10'b0;
+      slc_regs_regs_2_3_itm <= 10'b0;
+      slc_regs_regs_2_1_itm <= 10'b0;
+      slc_regs_regs_2_2_itm <= 10'b0;
+      slc_regs_regs_2_itm <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= 10'b0;
+    end
+    else begin
+      if ( en ) begin
+        slc_regs_regs_2_7_itm <= reg_regs_regs_0_sva_cse[49:40];
+        slc_regs_regs_2_8_itm <= reg_regs_regs_0_sva_cse[79:70];
+        reg_regs_regs_0_sva_cse <= vin_rsc_mgc_in_wire_d;
+        slc_regs_regs_2_6_itm <= reg_regs_regs_0_sva_cse[19:10];
+        slc_regs_regs_2_4_itm <= reg_regs_regs_0_sva_cse[39:30];
+        slc_regs_regs_2_5_itm <= reg_regs_regs_0_sva_cse[69:60];
+        slc_regs_regs_2_3_itm <= reg_regs_regs_0_sva_cse[9:0];
+        slc_regs_regs_2_1_itm <= reg_regs_regs_0_sva_cse[59:50];
+        slc_regs_regs_2_2_itm <= reg_regs_regs_0_sva_cse[89:80];
+        slc_regs_regs_2_itm <= reg_regs_regs_0_sva_cse[29:20];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp <= ((conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_psp_sva[11:9])
+            * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+            (acc_imod_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_sva[2:0])
+            , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_sva[5:3])) , (~ (acc_imod_sva[5]))})))))})
+            + conv_u2u_2_4(acc_imod_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_psp_sva[8:6])))
+            + ({4'b1001 , (acc_imod_sva[5])})))) + conv_u2u_20_10(conv_u2u_2_10(ACC_acc_psp_sva[13:12])
+            * 10'b100000001)) | ({5'b0 , (signext_5_2(acc_9_psp_sva[11:10]))});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= acc_9_psp_sva[9:5];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= (acc_9_psp_sva[4:0]) | (signext_5_2(acc_14_psp_sva[11:10]));
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= acc_14_psp_sva[9:0];
+      end
+    end
+  end
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_2;
+    input [1:0] vector;
+  begin
+    signext_5_2= {{3{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_13_14 ;
+    input [12:0]  vector ;
+  begin
+    conv_u2u_13_14 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    mean_vga
+//  Generated from file(s):
+//    5) $PROJECT_HOME/vga_mouse_filter/blur.c
+// ------------------------------------------------------------------
+
+
+module mean_vga (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  mean_vga_core mean_vga_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+