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-rw-r--r--sobel_filter/Sobel/sobel.v1/rtl.v565
1 files changed, 0 insertions, 565 deletions
diff --git a/sobel_filter/Sobel/sobel.v1/rtl.v b/sobel_filter/Sobel/sobel.v1/rtl.v
deleted file mode 100644
index 75c0023..0000000
--- a/sobel_filter/Sobel/sobel.v1/rtl.v
+++ /dev/null
@@ -1,565 +0,0 @@
-// ----------------------------------------------------------------------
-// HLS HDL: Verilog Netlister
-// HLS Version: 2011a.126 Production Release
-// HLS Date: Wed Aug 8 00:52:07 PDT 2012
-//
-// Generated by: mg3115@EEWS104A-013
-// Generated date: Tue Mar 08 13:49:49 2016
-// ----------------------------------------------------------------------
-
-//
-// ------------------------------------------------------------------
-// Design Unit: sobel_core
-// ------------------------------------------------------------------
-
-
-module sobel_core (
- clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
-);
- input clk;
- input en;
- input arst_n;
- input [89:0] vin_rsc_mgc_in_wire_d;
- output [29:0] vout_rsc_mgc_out_stdreg_d;
-
-
- // Interconnect Declarations
- reg [89:0] regs_regs_1_sva;
- reg [9:0] ACC1_slc_regs_regs_2_itm;
- reg [9:0] ACC1_slc_regs_regs_2_9_itm;
- reg [9:0] ACC1_slc_regs_regs_2_10_itm;
- reg [9:0] ACC1_slc_regs_regs_2_11_itm;
- reg [9:0] ACC1_slc_regs_regs_2_12_itm;
- reg [9:0] ACC1_slc_regs_regs_2_13_itm;
- reg [9:0] ACC1_slc_regs_regs_2_14_itm;
- reg [9:0] ACC1_slc_regs_regs_2_15_itm;
- reg [9:0] ACC1_slc_regs_regs_2_16_itm;
- reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp;
- wire [11:0] nl_reg_vout_rsc_mgc_out_stdreg_d_tmp;
- reg [3:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_1;
- reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_2;
- reg reg_vout_rsc_mgc_out_stdreg_d_tmp_3;
- reg [8:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_4;
- reg reg_vout_rsc_mgc_out_stdreg_d_tmp_5;
- wire [12:0] ACC1_acc_psp_sva;
- wire [13:0] nl_ACC1_acc_psp_sva;
- wire [6:0] FRAME_acc_41_sdt;
- wire [7:0] nl_FRAME_acc_41_sdt;
- wire [11:0] FRAME_acc_psp;
- wire [12:0] nl_FRAME_acc_psp;
- wire [11:0] FRAME_acc_24_sdt;
- wire [12:0] nl_FRAME_acc_24_sdt;
- wire [11:0] FRAME_acc_61_psp;
- wire [12:0] nl_FRAME_acc_61_psp;
- wire [11:0] FRAME_acc_37_sdt;
- wire [12:0] nl_FRAME_acc_37_sdt;
- wire [4:0] FRAME_acc_47_psp;
- wire [5:0] nl_FRAME_acc_47_psp;
- wire [5:0] FRAME_acc_13_sdt;
- wire [6:0] nl_FRAME_acc_13_sdt;
- wire [12:0] ACC1_acc_43_psp_sva;
- wire [13:0] nl_ACC1_acc_43_psp_sva;
- wire [4:0] FRAME_acc_55_psp;
- wire [5:0] nl_FRAME_acc_55_psp;
- wire [5:0] FRAME_acc_31_sdt;
- wire [6:0] nl_FRAME_acc_31_sdt;
- wire [12:0] ACC1_acc_42_psp_sva;
- wire [13:0] nl_ACC1_acc_42_psp_sva;
- wire [4:0] FRAME_acc_49_psp;
- wire [5:0] nl_FRAME_acc_49_psp;
- wire [5:0] FRAME_acc_18_sdt;
- wire [6:0] nl_FRAME_acc_18_sdt;
-
-
- // Interconnect Declarations for Component Instantiations
- assign vout_rsc_mgc_out_stdreg_d = {reg_vout_rsc_mgc_out_stdreg_d_tmp , reg_vout_rsc_mgc_out_stdreg_d_tmp_1
- , reg_vout_rsc_mgc_out_stdreg_d_tmp_2 , reg_vout_rsc_mgc_out_stdreg_d_tmp_3
- , reg_vout_rsc_mgc_out_stdreg_d_tmp_4 , reg_vout_rsc_mgc_out_stdreg_d_tmp_5};
- assign nl_ACC1_acc_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_itm
- , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_9_itm , 1'b1})))) , 1'b1})
- + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[29:20]))
- , 1'b1}) + conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[89:80])) , 1'b1})))) ,
- 1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_10_itm) +
- conv_s2u_10_11(~ (vin_rsc_mgc_in_wire_d[59:50]))) , 1'b1});
- assign ACC1_acc_psp_sva = nl_ACC1_acc_psp_sva[12:0];
- assign nl_FRAME_acc_41_sdt = conv_s2s_5_7(readslicef_6_5_1((conv_s2s_5_6({1'b1
- , (~ (ACC1_acc_psp_sva[8:6])) , 1'b1}) + conv_s2s_4_6({(FRAME_acc_47_psp[4:2])
- , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_47_psp[1:0]) , (FRAME_acc_13_sdt[0])
- , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_47_psp[4:2])) , (~ (FRAME_acc_47_psp[4]))})))))}))))
- + conv_u2s_5_7(signext_5_3({(ACC1_acc_psp_sva[12]) , (ACC1_acc_psp_sva[12])
- , (FRAME_acc_47_psp[4])}));
- assign FRAME_acc_41_sdt = nl_FRAME_acc_41_sdt[6:0];
- assign nl_FRAME_acc_psp = ({(conv_u2u_3_4(signext_3_1(ACC1_acc_42_psp_sva[12]))
- + conv_u2u_2_4(signext_2_1(ACC1_acc_42_psp_sva[12]))) , (ACC1_acc_42_psp_sva[12])
- , 1'b0 , (conv_u2u_2_4(signext_2_1(ACC1_acc_42_psp_sva[12])) + conv_u2u_3_4({(ACC1_acc_42_psp_sva[12])
- , (ACC1_acc_42_psp_sva[12]) , (ACC1_acc_42_psp_sva[12])})) , (ACC1_acc_42_psp_sva[12])
- , (ACC1_acc_42_psp_sva[12])}) + conv_s2u_11_12(FRAME_acc_24_sdt[11:1]);
- assign FRAME_acc_psp = nl_FRAME_acc_psp[11:0];
- assign nl_FRAME_acc_24_sdt = conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(signext_2_1(ACC1_acc_42_psp_sva[12]))
- * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_42_psp_sva[11:9])
- * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_42_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
- (FRAME_acc_49_psp[4])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_49_psp[1:0])
- , (FRAME_acc_18_sdt[0]) , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_49_psp[4:2]))
- , (~ (FRAME_acc_49_psp[4]))})))))}) + conv_u2u_2_4(FRAME_acc_49_psp[3:2]))
- + conv_u2u_3_5(~ (ACC1_acc_42_psp_sva[8:6]))) + ({4'b1001 , (FRAME_acc_49_psp[4])}))));
- assign FRAME_acc_24_sdt = nl_FRAME_acc_24_sdt[11:0];
- assign nl_FRAME_acc_61_psp = ({(conv_u2u_3_4(signext_3_1(ACC1_acc_43_psp_sva[12]))
- + conv_u2u_2_4(signext_2_1(ACC1_acc_43_psp_sva[12]))) , (ACC1_acc_43_psp_sva[12])
- , 1'b0 , (conv_u2u_2_4(signext_2_1(ACC1_acc_43_psp_sva[12])) + conv_u2u_3_4({(ACC1_acc_43_psp_sva[12])
- , (ACC1_acc_43_psp_sva[12]) , (ACC1_acc_43_psp_sva[12])})) , (ACC1_acc_43_psp_sva[12])
- , (ACC1_acc_43_psp_sva[12])}) + conv_s2u_11_12(FRAME_acc_37_sdt[11:1]);
- assign FRAME_acc_61_psp = nl_FRAME_acc_61_psp[11:0];
- assign nl_FRAME_acc_37_sdt = conv_u2s_11_13(conv_u2s_22_12(conv_u2u_2_11(signext_2_1(ACC1_acc_43_psp_sva[12]))
- * 11'b111000111)) + conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC1_acc_43_psp_sva[11:9])
- * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC1_acc_43_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
- (FRAME_acc_55_psp[4])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (FRAME_acc_55_psp[1:0])
- , (FRAME_acc_31_sdt[0]) , 1'b1}) + conv_u2s_4_5({(~ (FRAME_acc_55_psp[4:2]))
- , (~ (FRAME_acc_55_psp[4]))})))))}) + conv_u2u_2_4(FRAME_acc_55_psp[3:2]))
- + conv_u2u_3_5(~ (ACC1_acc_43_psp_sva[8:6]))) + ({4'b1001 , (FRAME_acc_55_psp[4])}))));
- assign FRAME_acc_37_sdt = nl_FRAME_acc_37_sdt[11:0];
- assign nl_FRAME_acc_47_psp = (FRAME_acc_13_sdt[5:1]) + 5'b10101;
- assign FRAME_acc_47_psp = nl_FRAME_acc_47_psp[4:0];
- assign nl_FRAME_acc_13_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_psp_sva[8:6])
- + conv_u2u_3_4(~ (ACC1_acc_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_psp_sva[12]))
- , (~ (ACC1_acc_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_psp_sva[12])
- , 1'b0 , (ACC1_acc_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_psp_sva[2:0]));
- assign FRAME_acc_13_sdt = nl_FRAME_acc_13_sdt[5:0];
- assign nl_ACC1_acc_43_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_14_itm
- , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_15_itm , 1'b1})))) , 1'b1})
- + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[9:0]))
- , 1'b1}) + conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[69:60])) , 1'b1})))) ,
- 1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_16_itm) +
- conv_s2u_10_11(~ (vin_rsc_mgc_in_wire_d[39:30]))) , 1'b1});
- assign ACC1_acc_43_psp_sva = nl_ACC1_acc_43_psp_sva[12:0];
- assign nl_FRAME_acc_55_psp = (FRAME_acc_31_sdt[5:1]) + 5'b10101;
- assign FRAME_acc_55_psp = nl_FRAME_acc_55_psp[4:0];
- assign nl_FRAME_acc_31_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_43_psp_sva[8:6])
- + conv_u2u_3_4(~ (ACC1_acc_43_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_43_psp_sva[12]))
- , (~ (ACC1_acc_43_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_43_psp_sva[12])
- , 1'b0 , (ACC1_acc_43_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_43_psp_sva[2:0]));
- assign FRAME_acc_31_sdt = nl_FRAME_acc_31_sdt[5:0];
- assign nl_ACC1_acc_42_psp_sva = conv_s2s_12_13(readslicef_13_12_1((conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({ACC1_slc_regs_regs_2_11_itm
- , 1'b1}) + conv_s2s_11_12({ACC1_slc_regs_regs_2_12_itm , 1'b1})))) , 1'b1})
- + conv_s2s_12_13({(readslicef_12_11_1((conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[19:10]))
- , 1'b1}) + conv_s2s_11_12({(~ (vin_rsc_mgc_in_wire_d[79:70])) , 1'b1})))) ,
- 1'b1})))) + conv_s2s_12_13({(conv_s2u_10_11(ACC1_slc_regs_regs_2_13_itm) +
- conv_s2u_10_11(~ (vin_rsc_mgc_in_wire_d[49:40]))) , 1'b1});
- assign ACC1_acc_42_psp_sva = nl_ACC1_acc_42_psp_sva[12:0];
- assign nl_FRAME_acc_49_psp = (FRAME_acc_18_sdt[5:1]) + 5'b10101;
- assign FRAME_acc_49_psp = nl_FRAME_acc_49_psp[4:0];
- assign nl_FRAME_acc_18_sdt = conv_u2u_5_6(conv_u2u_4_5(conv_u2u_3_4(ACC1_acc_42_psp_sva[8:6])
- + conv_u2u_3_4(~ (ACC1_acc_42_psp_sva[11:9]))) + conv_u2u_4_5({(~ (ACC1_acc_42_psp_sva[12]))
- , (~ (ACC1_acc_42_psp_sva[5:3]))})) + conv_u2u_4_6(conv_u2u_3_4({(ACC1_acc_42_psp_sva[12])
- , 1'b0 , (ACC1_acc_42_psp_sva[12])}) + conv_u2u_3_4(ACC1_acc_42_psp_sva[2:0]));
- assign FRAME_acc_18_sdt = nl_FRAME_acc_18_sdt[5:0];
- always @(posedge clk or negedge arst_n) begin
- if ( ~ arst_n ) begin
- ACC1_slc_regs_regs_2_14_itm <= 10'b0;
- ACC1_slc_regs_regs_2_15_itm <= 10'b0;
- ACC1_slc_regs_regs_2_16_itm <= 10'b0;
- ACC1_slc_regs_regs_2_11_itm <= 10'b0;
- ACC1_slc_regs_regs_2_12_itm <= 10'b0;
- ACC1_slc_regs_regs_2_13_itm <= 10'b0;
- ACC1_slc_regs_regs_2_itm <= 10'b0;
- ACC1_slc_regs_regs_2_9_itm <= 10'b0;
- ACC1_slc_regs_regs_2_10_itm <= 10'b0;
- regs_regs_1_sva <= 90'b0;
- reg_vout_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
- reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= 4'b0;
- reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= 5'b0;
- reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= 1'b0;
- reg_vout_rsc_mgc_out_stdreg_d_tmp_4 <= 9'b0;
- reg_vout_rsc_mgc_out_stdreg_d_tmp_5 <= 1'b0;
- end
- else begin
- if ( en ) begin
- ACC1_slc_regs_regs_2_14_itm <= regs_regs_1_sva[9:0];
- ACC1_slc_regs_regs_2_15_itm <= regs_regs_1_sva[69:60];
- ACC1_slc_regs_regs_2_16_itm <= regs_regs_1_sva[39:30];
- ACC1_slc_regs_regs_2_11_itm <= regs_regs_1_sva[19:10];
- ACC1_slc_regs_regs_2_12_itm <= regs_regs_1_sva[79:70];
- ACC1_slc_regs_regs_2_13_itm <= regs_regs_1_sva[49:40];
- ACC1_slc_regs_regs_2_itm <= regs_regs_1_sva[29:20];
- ACC1_slc_regs_regs_2_9_itm <= regs_regs_1_sva[89:80];
- ACC1_slc_regs_regs_2_10_itm <= regs_regs_1_sva[59:50];
- regs_regs_1_sva <= vin_rsc_mgc_in_wire_d;
- reg_vout_rsc_mgc_out_stdreg_d_tmp <= ((conv_u2u_20_10(conv_u2u_2_10(signext_2_1(ACC1_acc_psp_sva[12]))
- * 10'b111000111) + conv_u2u_9_10(conv_u2u_18_9(conv_u2u_3_9(ACC1_acc_psp_sva[11:9])
- * 9'b111001))) + (conv_u2s_9_10({(ACC1_acc_psp_sva[12]) , 2'b0 , (signext_6_4({(ACC1_acc_psp_sva[12])
- , (ACC1_acc_psp_sva[5:3])}))}) + conv_s2s_8_10({(conv_s2u_4_5(FRAME_acc_41_sdt[6:3])
- + conv_u2u_3_5(ACC1_acc_psp_sva[8:6])) , (FRAME_acc_41_sdt[2:0])})))
- | ({7'b0 , (FRAME_acc_psp[11:9])});
- reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= FRAME_acc_psp[8:5];
- reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= (FRAME_acc_psp[4:0]) | ({3'b0 , (FRAME_acc_61_psp[11:10])});
- reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= (FRAME_acc_24_sdt[0]) | (FRAME_acc_61_psp[9]);
- reg_vout_rsc_mgc_out_stdreg_d_tmp_4 <= FRAME_acc_61_psp[8:0];
- reg_vout_rsc_mgc_out_stdreg_d_tmp_5 <= FRAME_acc_37_sdt[0];
- end
- end
- end
-
- function [11:0] readslicef_13_12_1;
- input [12:0] vector;
- reg [12:0] tmp;
- begin
- tmp = vector >> 1;
- readslicef_13_12_1 = tmp[11:0];
- end
- endfunction
-
-
- function [10:0] readslicef_12_11_1;
- input [11:0] vector;
- reg [11:0] tmp;
- begin
- tmp = vector >> 1;
- readslicef_12_11_1 = tmp[10:0];
- end
- endfunction
-
-
- function [4:0] readslicef_6_5_1;
- input [5:0] vector;
- reg [5:0] tmp;
- begin
- tmp = vector >> 1;
- readslicef_6_5_1 = tmp[4:0];
- end
- endfunction
-
-
- function [0:0] readslicef_5_1_4;
- input [4:0] vector;
- reg [4:0] tmp;
- begin
- tmp = vector >> 4;
- readslicef_5_1_4 = tmp[0:0];
- end
- endfunction
-
-
- function [4:0] signext_5_3;
- input [2:0] vector;
- begin
- signext_5_3= {{2{vector[2]}}, vector};
- end
- endfunction
-
-
- function [2:0] signext_3_1;
- input [0:0] vector;
- begin
- signext_3_1= {{2{vector[0]}}, vector};
- end
- endfunction
-
-
- function [1:0] signext_2_1;
- input [0:0] vector;
- begin
- signext_2_1= {{1{vector[0]}}, vector};
- end
- endfunction
-
-
- function [5:0] signext_6_4;
- input [3:0] vector;
- begin
- signext_6_4= {{2{vector[3]}}, vector};
- end
- endfunction
-
-
- function signed [12:0] conv_s2s_12_13 ;
- input signed [11:0] vector ;
- begin
- conv_s2s_12_13 = {vector[11], vector};
- end
- endfunction
-
-
- function signed [11:0] conv_s2s_11_12 ;
- input signed [10:0] vector ;
- begin
- conv_s2s_11_12 = {vector[10], vector};
- end
- endfunction
-
-
- function [10:0] conv_s2u_10_11 ;
- input signed [9:0] vector ;
- begin
- conv_s2u_10_11 = {vector[9], vector};
- end
- endfunction
-
-
- function signed [6:0] conv_s2s_5_7 ;
- input signed [4:0] vector ;
- begin
- conv_s2s_5_7 = {{2{vector[4]}}, vector};
- end
- endfunction
-
-
- function signed [5:0] conv_s2s_5_6 ;
- input signed [4:0] vector ;
- begin
- conv_s2s_5_6 = {vector[4], vector};
- end
- endfunction
-
-
- function signed [5:0] conv_s2s_4_6 ;
- input signed [3:0] vector ;
- begin
- conv_s2s_4_6 = {{2{vector[3]}}, vector};
- end
- endfunction
-
-
- function signed [4:0] conv_u2s_4_5 ;
- input [3:0] vector ;
- begin
- conv_u2s_4_5 = {1'b0, vector};
- end
- endfunction
-
-
- function signed [6:0] conv_u2s_5_7 ;
- input [4:0] vector ;
- begin
- conv_u2s_5_7 = {{2{1'b0}}, vector};
- end
- endfunction
-
-
- function [3:0] conv_u2u_3_4 ;
- input [2:0] vector ;
- begin
- conv_u2u_3_4 = {1'b0, vector};
- end
- endfunction
-
-
- function [3:0] conv_u2u_2_4 ;
- input [1:0] vector ;
- begin
- conv_u2u_2_4 = {{2{1'b0}}, vector};
- end
- endfunction
-
-
- function [11:0] conv_s2u_11_12 ;
- input signed [10:0] vector ;
- begin
- conv_s2u_11_12 = {vector[10], vector};
- end
- endfunction
-
-
- function signed [12:0] conv_u2s_11_13 ;
- input [10:0] vector ;
- begin
- conv_u2s_11_13 = {{2{1'b0}}, vector};
- end
- endfunction
-
-
- function signed [11:0] conv_u2s_22_12 ;
- input [21:0] vector ;
- begin
- conv_u2s_22_12 = vector[11:0];
- end
- endfunction
-
-
- function [10:0] conv_u2u_2_11 ;
- input [1:0] vector ;
- begin
- conv_u2u_2_11 = {{9{1'b0}}, vector};
- end
- endfunction
-
-
- function signed [11:0] conv_s2s_10_12 ;
- input signed [9:0] vector ;
- begin
- conv_s2s_10_12 = {{2{vector[9]}}, vector};
- end
- endfunction
-
-
- function signed [10:0] conv_u2s_9_11 ;
- input [8:0] vector ;
- begin
- conv_u2s_9_11 = {{2{1'b0}}, vector};
- end
- endfunction
-
-
- function signed [9:0] conv_u2s_18_10 ;
- input [17:0] vector ;
- begin
- conv_u2s_18_10 = vector[9:0];
- end
- endfunction
-
-
- function [8:0] conv_u2u_3_9 ;
- input [2:0] vector ;
- begin
- conv_u2u_3_9 = {{6{1'b0}}, vector};
- end
- endfunction
-
-
- function signed [9:0] conv_s2s_8_10 ;
- input signed [7:0] vector ;
- begin
- conv_s2s_8_10 = {{2{vector[7]}}, vector};
- end
- endfunction
-
-
- function signed [7:0] conv_u2s_6_8 ;
- input [5:0] vector ;
- begin
- conv_u2s_6_8 = {{2{1'b0}}, vector};
- end
- endfunction
-
-
- function signed [7:0] conv_s2s_5_8 ;
- input signed [4:0] vector ;
- begin
- conv_s2s_5_8 = {{3{vector[4]}}, vector};
- end
- endfunction
-
-
- function [4:0] conv_u2u_4_5 ;
- input [3:0] vector ;
- begin
- conv_u2u_4_5 = {1'b0, vector};
- end
- endfunction
-
-
- function [4:0] conv_u2u_3_5 ;
- input [2:0] vector ;
- begin
- conv_u2u_3_5 = {{2{1'b0}}, vector};
- end
- endfunction
-
-
- function [5:0] conv_u2u_5_6 ;
- input [4:0] vector ;
- begin
- conv_u2u_5_6 = {1'b0, vector};
- end
- endfunction
-
-
- function [5:0] conv_u2u_4_6 ;
- input [3:0] vector ;
- begin
- conv_u2u_4_6 = {{2{1'b0}}, vector};
- end
- endfunction
-
-
- function [9:0] conv_u2u_20_10 ;
- input [19:0] vector ;
- begin
- conv_u2u_20_10 = vector[9:0];
- end
- endfunction
-
-
- function [9:0] conv_u2u_2_10 ;
- input [1:0] vector ;
- begin
- conv_u2u_2_10 = {{8{1'b0}}, vector};
- end
- endfunction
-
-
- function [9:0] conv_u2u_9_10 ;
- input [8:0] vector ;
- begin
- conv_u2u_9_10 = {1'b0, vector};
- end
- endfunction
-
-
- function [8:0] conv_u2u_18_9 ;
- input [17:0] vector ;
- begin
- conv_u2u_18_9 = vector[8:0];
- end
- endfunction
-
-
- function signed [9:0] conv_u2s_9_10 ;
- input [8:0] vector ;
- begin
- conv_u2s_9_10 = {1'b0, vector};
- end
- endfunction
-
-
- function [4:0] conv_s2u_4_5 ;
- input signed [3:0] vector ;
- begin
- conv_s2u_4_5 = {vector[3], vector};
- end
- endfunction
-
-endmodule
-
-// ------------------------------------------------------------------
-// Design Unit: sobel
-// Generated from file(s):
-// 7) $PROJECT_HOME/sobel.cpp
-// ------------------------------------------------------------------
-
-
-module sobel (
- vin_rsc_z, vout_rsc_z, clk, en, arst_n
-);
- input [89:0] vin_rsc_z;
- output [29:0] vout_rsc_z;
- input clk;
- input en;
- input arst_n;
-
-
- // Interconnect Declarations
- wire [89:0] vin_rsc_mgc_in_wire_d;
- wire [29:0] vout_rsc_mgc_out_stdreg_d;
-
-
- // Interconnect Declarations for Component Instantiations
- mgc_in_wire #(.rscid(1),
- .width(90)) vin_rsc_mgc_in_wire (
- .d(vin_rsc_mgc_in_wire_d),
- .z(vin_rsc_z)
- );
- mgc_out_stdreg #(.rscid(2),
- .width(30)) vout_rsc_mgc_out_stdreg (
- .d(vout_rsc_mgc_out_stdreg_d),
- .z(vout_rsc_z)
- );
- sobel_core sobel_core_inst (
- .clk(clk),
- .en(en),
- .arst_n(arst_n),
- .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
- .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
- );
-endmodule
-
-
-
generated by cgit (git 2.34.1) at 2024-06-01 02:32:31 +0000