diff options
Diffstat (limited to 'sobel_filter/Sobel/sobel.v9/rtl.rpt')
| -rw-r--r-- | sobel_filter/Sobel/sobel.v9/rtl.rpt | 825 |
1 files changed, 0 insertions, 825 deletions
diff --git a/sobel_filter/Sobel/sobel.v9/rtl.rpt b/sobel_filter/Sobel/sobel.v9/rtl.rpt deleted file mode 100644 index 49c0be8..0000000 --- a/sobel_filter/Sobel/sobel.v9/rtl.rpt +++ /dev/null @@ -1,825 +0,0 @@ --- Catapult University Version: Report --- ---------------------------- --------------------------------------------------- --- Version: 2011a.126 Production Release --- Build Date: Wed Aug 8 00:52:07 PDT 2012 - --- Generated by: mg3115@EEWS104A-013 --- Generated date: Tue Mar 08 15:38:54 +0000 2016 - -Solution Settings: sobel.v9 - Current state: extract - Project: Sobel - - Design Input Files Specified - $PROJECT_HOME/sobel.h - $MGC_HOME/shared/include/ac_int.h - $PROJECT_HOME/bmp_io.cpp - $PROJECT_HOME/bmp_io.h - $PROJECT_HOME/tb_blur.cpp - $MGC_HOME/shared/include/mc_testbench.h - $MGC_HOME/shared/include/mc_scverify.h - $MGC_HOME/shared/include/ac_int.h - $PROJECT_HOME/sobel.h - $PROJECT_HOME/bmp_io.h - $PROJECT_HOME/bmp_io.h - $PROJECT_HOME/shift_class.h - $PROJECT_HOME/sobel.cpp - $MGC_HOME/shared/include/ac_fixed.h - $MGC_HOME/shared/include/ac_int.h - $PROJECT_HOME/sobel.h - $PROJECT_HOME/shift_class.h - - Processes/Blocks in Design - Process Real Operation(s) count Latency Throughput Reset Length II Comments - ------------- ----------------------- ------- ---------- ------------ -- -------- - /sobel/core 220 1843201 1843200 0 1 - Design Total: 220 1843201 1843200 0 0 - - Bill Of Materials (Datapath) - Component Name Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign - --------------------------------------- ---------- --------------------------- ---------- ----- ---------- ----------- - [Lib: mgc_Altera-Cyclone-III-6_beh_psr] - mgc_add(10,0,10,0,10) 11.241 0.000 11.241 1.301 1 1 - mgc_add(10,0,9,1,10) 11.000 0.000 11.000 1.303 1 0 - mgc_add(11,0,10,1,12) 12.000 0.000 12.000 1.208 2 2 - mgc_add(12,0,11,0,12) 13.228 0.000 13.228 1.436 2 2 - mgc_add(15,0,11,1,15) 16.000 0.000 16.000 1.633 3 3 - mgc_add(15,0,15,0,15) 16.198 0.000 16.198 1.627 0 3 - mgc_add(16,0,12,1,16) 17.000 0.000 17.000 1.696 12 12 - mgc_add(16,0,16,0,16) 17.189 0.000 17.189 1.690 6 3 - mgc_add(19,0,2,1,19) 20.000 0.000 20.000 1.908 1 1 - mgc_add(2,0,1,0,2) 3.315 0.000 3.315 0.658 0 2 - mgc_add(2,0,1,1,2) 3.000 0.000 3.000 0.658 1 2 - mgc_add(2,0,2,0,2) 3.311 0.000 3.311 0.653 2 2 - mgc_add(3,0,3,0,3) 4.302 0.000 4.302 0.761 2 0 - mgc_add(3,0,3,0,4) 4.302 0.000 4.302 0.761 12 12 - mgc_add(4,0,4,0,5) 5.293 0.000 5.293 0.854 6 6 - mgc_add(5,0,4,0,6) 6.288 0.000 6.288 0.940 3 3 - mgc_add(5,0,5,0,5) 6.285 0.000 6.285 0.938 6 6 - mgc_add(5,0,5,0,6) 6.285 0.000 6.285 0.938 0 1 - mgc_add(6,0,5,1,8) 7.000 0.000 7.000 0.693 3 3 - mgc_add(6,0,6,0,6) 7.276 0.000 7.276 1.016 3 3 - mgc_add(8,0,7,0,8) 9.262 0.000 9.262 1.165 1 1 - mgc_add(9,0,8,1,10) 10.000 0.000 10.000 1.072 3 3 - mgc_and(1,2) 0.730 0.000 0.730 0.263 0 6 - mgc_and(1,3) 1.054 0.000 1.054 0.416 0 1 - mgc_and(15,2) 10.947 0.000 10.947 0.263 3 3 - mgc_and(16,2) 11.677 0.000 11.677 0.263 6 6 - mgc_and(19,2) 13.867 0.000 13.867 0.263 1 1 - mgc_and(2,2) 1.460 0.000 1.460 0.263 6 2 - mgc_mul(2,0,9,0,11) 330.250 2.000 10.250 3.044 3 3 - mgc_mul(2,1,10,1,12) 330.000 2.000 10.000 3.087 9 15 - mgc_mul(3,0,6,0,9) 330.250 2.000 10.250 2.846 3 3 - mgc_mux(1,1,2) 0.919 0.000 0.919 0.369 4 3 - mgc_mux(10,2,4) 22.259 0.000 22.259 0.936 15 15 - mgc_mux(15,1,2) 13.791 0.000 13.791 0.369 3 3 - mgc_mux(16,1,2) 14.711 0.000 14.711 0.369 6 6 - mgc_mux(19,1,2) 17.469 0.000 17.469 0.369 1 1 - mgc_mux(2,1,2) 1.839 0.000 1.839 0.369 2 2 - mgc_mux(30,1,2) 27.583 0.000 27.583 0.369 0 1 - mgc_mux(90,1,2) 82.748 0.000 82.748 0.369 3 3 - mgc_nand(1,2) 0.730 0.000 0.730 0.268 0 4 - mgc_nand(1,3) 1.054 0.000 1.054 0.425 0 1 - mgc_nor(1,2) 0.730 0.000 0.730 0.263 0 4 - mgc_not(1) 0.000 0.000 0.000 0.000 0 28 - mgc_not(3) 0.000 0.000 0.000 0.000 0 12 - mgc_or(1,2) 0.730 0.000 0.730 0.268 0 6 - mgc_or(1,3) 1.054 0.000 1.054 0.425 0 3 - mgc_or(10,2) 7.298 0.000 7.298 0.268 1 1 - mgc_or(2,2) 1.460 0.000 1.460 0.268 4 0 - mgc_or(6,2) 4.379 0.000 4.379 0.268 1 1 - mgc_reg_pos(1,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 12 - mgc_reg_pos(11,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 2 - mgc_reg_pos(15,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 3 - mgc_reg_pos(16,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 6 - mgc_reg_pos(19,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 - mgc_reg_pos(2,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 4 - mgc_reg_pos(30,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 1 - mgc_reg_pos(5,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 3 - mgc_reg_pos(6,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 4 - mgc_reg_pos(9,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 3 - mgc_reg_pos(90,1,0,0,0,1,1) 0.000 0.000 0.000 0.000 0 3 - [Lib: mgc_ioport] - mgc_in_wire(1,90) 0.000 0.000 0.000 0.000 1 1 - mgc_out_stdreg(2,30) 0.000 0.000 0.000 0.000 1 1 - - TOTAL AREA (After Assignment): 8527.433 42.000 1807.000 - - Area Scores - Post-Scheduling Post-DP & FSM Post-Assignment - ----------------- --------------- --------------- --------------- - Total Area Score: 6519.2 8702.1 8527.4 - Total Reg: 0.0 0.0 0.0 - - DataPath: 6519.2 (100%) 8702.1 (100%) 8527.4 (100%) - MUX: 736.6 (11%) 935.3 (11%) 763.3 (9%) - FUNC: 5639.6 (87%) 7614.9 (88%) 7612.9 (89%) - LOGIC: 143.0 (2%) 152.0 (2%) 151.2 (2%) - BUFFER: 0.0 0.0 0.0 - MEM: 0.0 0.0 0.0 - ROM: 0.0 0.0 0.0 - REG: 0.0 0.0 0.0 - - - FSM: 0.0 0.0 0.0 - FSM-REG: 0.0 0.0 0.0 - FSM-COMB: 0.0 0.0 0.0 - - - Register-to-Variable Mappings - Register Size(bits) Gated Register CG Opt Done Variables - ------------------------------- ---------- -------------- ----------- ----------------------------------------------------- - regs.regs(0).sva 90 Y regs.regs(0).sva - regs.regs(1).sva 90 Y regs.regs(1).sva - regs.regs(2).lpi#1.dfm 90 Y regs.regs(2).lpi#1.dfm - vout:rsc:mgc_out_stdreg.d 30 Y vout:rsc:mgc_out_stdreg.d - FRAME:p#1.lpi#1 19 Y FRAME:p#1.lpi#1 - b(0).lpi#1 16 Y b(0).lpi#1 - b(2).lpi#1 16 Y b(2).lpi#1 - g(0).lpi#1 16 Y g(0).lpi#1 - g(2).lpi#1 16 Y g(2).lpi#1 - r(0).lpi#1 16 Y r(0).lpi#1 - r(2).lpi#1 16 Y r(2).lpi#1 - b(1).sg1.lpi#1 15 Y b(1).sg1.lpi#1 - g(1).sg1.lpi#1 15 Y g(1).sg1.lpi#1 - r(1).sg1.lpi#1 15 Y r(1).sg1.lpi#1 - FRAME:mul#2.itm#1 11 Y FRAME:mul#2.itm#1 - FRAME:mul#4.itm#1 11 Y FRAME:mul#4.itm#1 - FRAME:mul#1.itm#1 9 Y FRAME:mul#1.itm#1 - FRAME:mul#3.itm#1 9 Y FRAME:mul#3.itm#1 - FRAME:mul#5.itm#1 9 Y FRAME:mul#5.itm#1 - FRAME:acc#41.itm#3 6 Y FRAME:acc#41.itm#3 - blue:slc(blue#2.sg1).itm#1 6 Y blue:slc(blue#2.sg1).itm#1 - green:slc(green#2.sg1).itm#1 6 Y green:slc(green#2.sg1).itm#1 - red:slc(red#2.sg1).itm#1 6 Y red:slc(red#2.sg1).itm#1 - FRAME:acc#18.itm#1 5 Y FRAME:acc#18.itm#1 - FRAME:acc#30.itm#1 5 Y FRAME:acc#30.itm#1 - FRAME:acc#37.itm#1 5 Y FRAME:acc#37.itm#1 - FRAME:acc#41.itm#1.sg1 2 Y FRAME:acc#41.itm#1.sg1 - FRAME:acc#41.itm#1.sg2 2 Y FRAME:acc#41.itm#1.sg2 - i#6.lpi#1 2 Y i#6.lpi#1 - i#7.lpi#1 2 Y i#7.lpi#1 - FRAME:slc(acc.imod#3)#4.itm#1 1 Y FRAME:slc(acc.imod#3)#4.itm#1 - FRAME:slc(acc.imod#5)#4.itm#1 1 Y FRAME:slc(acc.imod#5)#4.itm#1 - FRAME:slc(acc.imod#7)#4.itm#1 1 Y FRAME:slc(acc.imod#7)#4.itm#1 - blue:slc(blue#2.sg1)#12.itm#1 1 Y blue:slc(blue#2.sg1)#12.itm#1 - exit:FRAME#1.sva 1 Y exit:FRAME#1.sva - exit:FRAME.lpi#1.dfm#2 1 Y exit:FRAME.lpi#1.dfm#2 - exit:FRAME:for#1.lpi#1.dfm#4 1 Y exit:FRAME:for#1.lpi#1.dfm#4 - exit:FRAME:for#1.sva#2.st#1 1 Y exit:FRAME:for#1.sva#2.st#1 - exit:FRAME:for.lpi#1 1 Y exit:FRAME:for.lpi#1 - exit:FRAME:for.lpi#1.dfm.st#1 1 Y exit:FRAME:for.lpi#1.dfm.st#1 - green:slc(green#2.sg1)#12.itm#1 1 Y green:slc(green#2.sg1)#12.itm#1 - main.stage_0#2 1 Y main.stage_0#2 - - Total: 568 568 0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) - - Timing Report - Critical Path - Max Delay: 15.158629 - Slack: 4.8413710000000005 - - Path Startpoint Endpoint Delay Slack - ---------------------------------------------- -------------------------------------- ---------------------------------- ------- ------- - 1 sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#37.itm#1) 15.1586 4.8414 - - Instance Component Delta Delay - -------- --------- ----- ----- - sobel:core/reg(regs.regs(2).lpi#1.dfm) mgc_reg_pos_90_1_0_0_0_1_1 0.0000 0.0000 - sobel:core/regs.regs(2).lpi#1.dfm 0.0000 0.0000 - sobel:core/slc(regs.regs(2).lpi#1.dfm)#2 0.0000 0.0000 - sobel:core/slc(regs.regs(2).lpi#1.dfm)#2.itm 0.0000 0.0000 - sobel:core/regs.operator[]#21:mux mgc_mux_10_2_4 0.9364 0.9364 - sobel:core/regs.operator[]#21:mux.itm 0.0000 0.9364 - sobel:core/FRAME:for#1:mul#6 mgc_mul_2_1_10_1_12 3.0868 4.0232 - sobel:core/FRAME:for#1:mul#6.itm 0.0000 4.0232 - sobel:core/FRAME:for#1:acc#10 mgc_add_16_0_12_1_16 1.6960 5.7193 - sobel:core/r(2).sva#1 0.0000 5.7193 - sobel:core/slc(r(2).sva#1) 0.0000 5.7193 - sobel:core/slc(r(2).sva#1).itm 0.0000 5.7193 - sobel:core/ACC2:acc mgc_add_15_0_15_0_15 1.6269 7.3461 - sobel:core/ACC2:acc.itm 0.0000 7.3461 - sobel:core/ACC2:conc 0.0000 7.3461 - sobel:core/ACC2:conc.itm 0.0000 7.3461 - sobel:core/ACC2-3:acc#1 mgc_add_16_0_16_0_16 1.6898 9.0359 - sobel:core/ACC2-3:acc#1.itm 0.0000 9.0359 - sobel:core/ACC2:slc 0.0000 9.0359 - sobel:core/red#2.sg1.sva 0.0000 9.0359 - sobel:core/slc(red#2.sg1.sva) 0.0000 9.0359 - sobel:core/slc(red#2.sg1.sva).itm 0.0000 9.0359 - sobel:core/FRAME:acc#8 mgc_add_3_0_3_0_4 0.7609 9.7968 - sobel:core/FRAME:acc#8.itm 0.0000 9.7968 - sobel:core/FRAME:acc#10 mgc_add_4_0_4_0_5 0.8536 10.6503 - sobel:core/FRAME:acc#10.itm 0.0000 10.6503 - sobel:core/FRAME:acc#11 mgc_add_5_0_4_0_6 0.9400 11.5904 - sobel:core/FRAME:acc#11.itm 0.0000 11.5904 - sobel:core/acc#3 mgc_add_6_0_6_0_6 1.0162 12.6066 - sobel:core/acc.imod#3.sva 0.0000 12.6066 - sobel:core/slc(acc.imod#3.sva)#1 0.0000 12.6066 - sobel:core/slc(acc.imod#3.sva)#1.itm 0.0000 12.6066 - sobel:core/conc#142 0.0000 12.6066 - sobel:core/conc#142.itm 0.0000 12.6066 - sobel:core/FRAME:acc#42 mgc_add_5_0_5_0_5 0.9376 13.5442 - sobel:core/FRAME:acc#42.itm 0.0000 13.5442 - sobel:core/FRAME:slc#7 0.0000 13.5442 - sobel:core/FRAME:slc#7.itm 0.0000 13.5442 - sobel:core/FRAME:not#39 mgc_not_1 0.0000 13.5442 - sobel:core/FRAME:not#39.itm 0.0000 13.5442 - sobel:core/conc#141 0.0000 13.5442 - sobel:core/conc#141.itm 0.0000 13.5442 - sobel:core/FRAME:acc#36 mgc_add_3_0_3_0_4 0.7609 14.3051 - sobel:core/FRAME:acc#36.itm 0.0000 14.3051 - sobel:core/FRAME:acc#37 mgc_add_4_0_4_0_5 0.8536 15.1586 - sobel:core/FRAME:acc#37.itm 0.0000 15.1586 - sobel:core/reg(FRAME:acc#37.itm#1) mgc_reg_pos_5_1_0_0_0_1_1 0.0000 15.1586 - - 2 sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414 - - Instance Component Delta Delay - -------- --------- ----- ----- - sobel:core/reg(regs.regs(2).lpi#1.dfm) mgc_reg_pos_90_1_0_0_0_1_1 0.0000 0.0000 - sobel:core/regs.regs(2).lpi#1.dfm 0.0000 0.0000 - sobel:core/slc(regs.regs(2).lpi#1.dfm)#1 0.0000 0.0000 - sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm 0.0000 0.0000 - sobel:core/regs.operator[]#22:mux mgc_mux_10_2_4 0.9364 0.9364 - sobel:core/regs.operator[]#22:mux.itm 0.0000 0.9364 - sobel:core/FRAME:for#1:mul#7 mgc_mul_2_1_10_1_12 3.0868 4.0232 - sobel:core/FRAME:for#1:mul#7.itm 0.0000 4.0232 - sobel:core/FRAME:for#1:acc#12 mgc_add_16_0_12_1_16 1.6960 5.7193 - sobel:core/g(2).sva#1 0.0000 5.7193 - sobel:core/slc(g(2).sva#1) 0.0000 5.7193 - sobel:core/slc(g(2).sva#1).itm 0.0000 5.7193 - sobel:core/ACC2:acc#7 mgc_add_15_0_15_0_15 1.6269 7.3461 - sobel:core/ACC2:acc#7.itm 0.0000 7.3461 - sobel:core/ACC2:conc#1 0.0000 7.3461 - sobel:core/ACC2:conc#1.itm 0.0000 7.3461 - sobel:core/ACC2-3:acc#2 mgc_add_16_0_16_0_16 1.6898 9.0359 - sobel:core/ACC2-3:acc#2.itm 0.0000 9.0359 - sobel:core/ACC2:slc#1 0.0000 9.0359 - sobel:core/green#2.sg1.sva 0.0000 9.0359 - sobel:core/slc(green#2.sg1.sva)#1 0.0000 9.0359 - sobel:core/slc(green#2.sg1.sva)#1.itm 0.0000 9.0359 - sobel:core/FRAME:acc#13 mgc_add_3_0_3_0_4 0.7609 9.7968 - sobel:core/FRAME:acc#13.itm 0.0000 9.7968 - sobel:core/FRAME:acc#15 mgc_add_4_0_4_0_5 0.8536 10.6503 - sobel:core/FRAME:acc#15.itm 0.0000 10.6503 - sobel:core/FRAME:acc#16 mgc_add_5_0_4_0_6 0.9400 11.5904 - sobel:core/FRAME:acc#16.itm 0.0000 11.5904 - sobel:core/acc#5 mgc_add_6_0_6_0_6 1.0162 12.6066 - sobel:core/acc.imod#5.sva 0.0000 12.6066 - sobel:core/slc(acc.imod#5.sva)#1 0.0000 12.6066 - sobel:core/slc(acc.imod#5.sva)#1.itm 0.0000 12.6066 - sobel:core/conc#146 0.0000 12.6066 - sobel:core/conc#146.itm 0.0000 12.6066 - sobel:core/FRAME:acc#23 mgc_add_5_0_5_0_5 0.9376 13.5442 - sobel:core/FRAME:acc#23.itm 0.0000 13.5442 - sobel:core/FRAME:slc#5 0.0000 13.5442 - sobel:core/FRAME:slc#5.itm 0.0000 13.5442 - sobel:core/FRAME:not#43 mgc_not_1 0.0000 13.5442 - sobel:core/FRAME:not#43.itm 0.0000 13.5442 - sobel:core/conc#145 0.0000 13.5442 - sobel:core/conc#145.itm 0.0000 13.5442 - sobel:core/FRAME:acc#17 mgc_add_3_0_3_0_4 0.7609 14.3051 - sobel:core/FRAME:acc#17.itm 0.0000 14.3051 - sobel:core/FRAME:acc#18 mgc_add_4_0_4_0_5 0.8536 15.1586 - sobel:core/FRAME:acc#18.itm 0.0000 15.1586 - sobel:core/reg(FRAME:acc#18.itm#1) mgc_reg_pos_5_1_0_0_0_1_1 0.0000 15.1586 - - 3 sobel:core/reg(regs.regs(1).sva) sobel:core/reg(FRAME:acc#37.itm#1) 15.1586 4.8414 - - Instance Component Delta Delay - -------- --------- ----- ----- - sobel:core/reg(regs.regs(1).sva) mgc_reg_pos_90_1_0_0_0_1_1 0.0000 0.0000 - sobel:core/regs.regs(1).sva 0.0000 0.0000 - sobel:core/slc(regs.regs(1).sva)#2 0.0000 0.0000 - sobel:core/slc(regs.regs(1).sva)#2.itm 0.0000 0.0000 - sobel:core/regs.operator[]#21:mux mgc_mux_10_2_4 0.9364 0.9364 - sobel:core/regs.operator[]#21:mux.itm 0.0000 0.9364 - sobel:core/FRAME:for#1:mul#6 mgc_mul_2_1_10_1_12 3.0868 4.0232 - sobel:core/FRAME:for#1:mul#6.itm 0.0000 4.0232 - sobel:core/FRAME:for#1:acc#10 mgc_add_16_0_12_1_16 1.6960 5.7193 - sobel:core/r(2).sva#1 0.0000 5.7193 - sobel:core/slc(r(2).sva#1) 0.0000 5.7193 - sobel:core/slc(r(2).sva#1).itm 0.0000 5.7193 - sobel:core/ACC2:acc mgc_add_15_0_15_0_15 1.6269 7.3461 - sobel:core/ACC2:acc.itm 0.0000 7.3461 - sobel:core/ACC2:conc 0.0000 7.3461 - sobel:core/ACC2:conc.itm 0.0000 7.3461 - sobel:core/ACC2-3:acc#1 mgc_add_16_0_16_0_16 1.6898 9.0359 - sobel:core/ACC2-3:acc#1.itm 0.0000 9.0359 - sobel:core/ACC2:slc 0.0000 9.0359 - sobel:core/red#2.sg1.sva 0.0000 9.0359 - sobel:core/slc(red#2.sg1.sva) 0.0000 9.0359 - sobel:core/slc(red#2.sg1.sva).itm 0.0000 9.0359 - sobel:core/FRAME:acc#8 mgc_add_3_0_3_0_4 0.7609 9.7968 - sobel:core/FRAME:acc#8.itm 0.0000 9.7968 - sobel:core/FRAME:acc#10 mgc_add_4_0_4_0_5 0.8536 10.6503 - sobel:core/FRAME:acc#10.itm 0.0000 10.6503 - sobel:core/FRAME:acc#11 mgc_add_5_0_4_0_6 0.9400 11.5904 - sobel:core/FRAME:acc#11.itm 0.0000 11.5904 - sobel:core/acc#3 mgc_add_6_0_6_0_6 1.0162 12.6066 - sobel:core/acc.imod#3.sva 0.0000 12.6066 - sobel:core/slc(acc.imod#3.sva)#1 0.0000 12.6066 - sobel:core/slc(acc.imod#3.sva)#1.itm 0.0000 12.6066 - sobel:core/conc#142 0.0000 12.6066 - sobel:core/conc#142.itm 0.0000 12.6066 - sobel:core/FRAME:acc#42 mgc_add_5_0_5_0_5 0.9376 13.5442 - sobel:core/FRAME:acc#42.itm 0.0000 13.5442 - sobel:core/FRAME:slc#7 0.0000 13.5442 - sobel:core/FRAME:slc#7.itm 0.0000 13.5442 - sobel:core/FRAME:not#39 mgc_not_1 0.0000 13.5442 - sobel:core/FRAME:not#39.itm 0.0000 13.5442 - sobel:core/conc#141 0.0000 13.5442 - sobel:core/conc#141.itm 0.0000 13.5442 - sobel:core/FRAME:acc#36 mgc_add_3_0_3_0_4 0.7609 14.3051 - sobel:core/FRAME:acc#36.itm 0.0000 14.3051 - sobel:core/FRAME:acc#37 mgc_add_4_0_4_0_5 0.8536 15.1586 - sobel:core/FRAME:acc#37.itm 0.0000 15.1586 - sobel:core/reg(FRAME:acc#37.itm#1) mgc_reg_pos_5_1_0_0_0_1_1 0.0000 15.1586 - - 4 sobel:core/reg(regs.regs(0).sva) sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414 - - Instance Component Delta Delay - -------- --------- ----- ----- - sobel:core/reg(regs.regs(0).sva) mgc_reg_pos_90_1_0_0_0_1_1 0.0000 0.0000 - sobel:core/regs.regs(0).sva 0.0000 0.0000 - sobel:core/slc(regs.regs(0).sva)#1 0.0000 0.0000 - sobel:core/slc(regs.regs(0).sva)#1.itm 0.0000 0.0000 - sobel:core/regs.operator[]#22:mux mgc_mux_10_2_4 0.9364 0.9364 - sobel:core/regs.operator[]#22:mux.itm 0.0000 0.9364 - sobel:core/FRAME:for#1:mul#7 mgc_mul_2_1_10_1_12 3.0868 4.0232 - sobel:core/FRAME:for#1:mul#7.itm 0.0000 4.0232 - sobel:core/FRAME:for#1:acc#12 mgc_add_16_0_12_1_16 1.6960 5.7193 - sobel:core/g(2).sva#1 0.0000 5.7193 - sobel:core/slc(g(2).sva#1) 0.0000 5.7193 - sobel:core/slc(g(2).sva#1).itm 0.0000 5.7193 - sobel:core/ACC2:acc#7 mgc_add_15_0_15_0_15 1.6269 7.3461 - sobel:core/ACC2:acc#7.itm 0.0000 7.3461 - sobel:core/ACC2:conc#1 0.0000 7.3461 - sobel:core/ACC2:conc#1.itm 0.0000 7.3461 - sobel:core/ACC2-3:acc#2 mgc_add_16_0_16_0_16 1.6898 9.0359 - sobel:core/ACC2-3:acc#2.itm 0.0000 9.0359 - sobel:core/ACC2:slc#1 0.0000 9.0359 - sobel:core/green#2.sg1.sva 0.0000 9.0359 - sobel:core/slc(green#2.sg1.sva)#1 0.0000 9.0359 - sobel:core/slc(green#2.sg1.sva)#1.itm 0.0000 9.0359 - sobel:core/FRAME:acc#13 mgc_add_3_0_3_0_4 0.7609 9.7968 - sobel:core/FRAME:acc#13.itm 0.0000 9.7968 - sobel:core/FRAME:acc#15 mgc_add_4_0_4_0_5 0.8536 10.6503 - sobel:core/FRAME:acc#15.itm 0.0000 10.6503 - sobel:core/FRAME:acc#16 mgc_add_5_0_4_0_6 0.9400 11.5904 - sobel:core/FRAME:acc#16.itm 0.0000 11.5904 - sobel:core/acc#5 mgc_add_6_0_6_0_6 1.0162 12.6066 - sobel:core/acc.imod#5.sva 0.0000 12.6066 - sobel:core/slc(acc.imod#5.sva)#1 0.0000 12.6066 - sobel:core/slc(acc.imod#5.sva)#1.itm 0.0000 12.6066 - sobel:core/conc#146 0.0000 12.6066 - sobel:core/conc#146.itm 0.0000 12.6066 - sobel:core/FRAME:acc#23 mgc_add_5_0_5_0_5 0.9376 13.5442 - sobel:core/FRAME:acc#23.itm 0.0000 13.5442 - sobel:core/FRAME:slc#5 0.0000 13.5442 - sobel:core/FRAME:slc#5.itm 0.0000 13.5442 - sobel:core/FRAME:not#43 mgc_not_1 0.0000 13.5442 - sobel:core/FRAME:not#43.itm 0.0000 13.5442 - sobel:core/conc#145 0.0000 13.5442 - sobel:core/conc#145.itm 0.0000 13.5442 - sobel:core/FRAME:acc#17 mgc_add_3_0_3_0_4 0.7609 14.3051 - sobel:core/FRAME:acc#17.itm 0.0000 14.3051 - sobel:core/FRAME:acc#18 mgc_add_4_0_4_0_5 0.8536 15.1586 - sobel:core/FRAME:acc#18.itm 0.0000 15.1586 - sobel:core/reg(FRAME:acc#18.itm#1) mgc_reg_pos_5_1_0_0_0_1_1 0.0000 15.1586 - - 5 sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414 - - Instance Component Delta Delay - -------- --------- ----- ----- - sobel:core/reg(regs.regs(2).lpi#1.dfm) mgc_reg_pos_90_1_0_0_0_1_1 0.0000 0.0000 - sobel:core/regs.regs(2).lpi#1.dfm 0.0000 0.0000 - sobel:core/slc(regs.regs(2).lpi#1.dfm)#1 0.0000 0.0000 - sobel:core/slc(regs.regs(2).lpi#1.dfm)#1.itm 0.0000 0.0000 - sobel:core/regs.operator[]#22:mux mgc_mux_10_2_4 0.9364 0.9364 - sobel:core/regs.operator[]#22:mux.itm 0.0000 0.9364 - sobel:core/FRAME:for#1:mul#7 mgc_mul_2_1_10_1_12 3.0868 4.0232 - sobel:core/FRAME:for#1:mul#7.itm 0.0000 4.0232 - sobel:core/FRAME:for#1:acc#12 mgc_add_16_0_12_1_16 1.6960 5.7193 - sobel:core/g(2).sva#1 0.0000 5.7193 - sobel:core/slc(g(2).sva#1) 0.0000 5.7193 - sobel:core/slc(g(2).sva#1).itm 0.0000 5.7193 - sobel:core/ACC2:acc#7 mgc_add_15_0_15_0_15 1.6269 7.3461 - sobel:core/ACC2:acc#7.itm 0.0000 7.3461 - sobel:core/ACC2:conc#1 0.0000 7.3461 - sobel:core/ACC2:conc#1.itm 0.0000 7.3461 - sobel:core/ACC2-3:acc#2 mgc_add_16_0_16_0_16 1.6898 9.0359 - sobel:core/ACC2-3:acc#2.itm 0.0000 9.0359 - sobel:core/ACC2:slc#1 0.0000 9.0359 - sobel:core/green#2.sg1.sva 0.0000 9.0359 - sobel:core/slc(green#2.sg1.sva)#12 0.0000 9.0359 - sobel:core/slc(green#2.sg1.sva)#12.itm 0.0000 9.0359 - sobel:core/FRAME:not#37 mgc_not_1 0.0000 9.0359 - sobel:core/FRAME:not#37.itm 0.0000 9.0359 - sobel:core/conc#155 0.0000 9.0359 - sobel:core/conc#155.itm 0.0000 9.0359 - sobel:core/FRAME:acc#12 mgc_add_3_0_3_0_4 0.7609 9.7968 - sobel:core/FRAME:acc#12.itm 0.0000 9.7968 - sobel:core/FRAME:acc#15 mgc_add_4_0_4_0_5 0.8536 10.6503 - sobel:core/FRAME:acc#15.itm 0.0000 10.6503 - sobel:core/FRAME:acc#16 mgc_add_5_0_4_0_6 0.9400 11.5904 - sobel:core/FRAME:acc#16.itm 0.0000 11.5904 - sobel:core/acc#5 mgc_add_6_0_6_0_6 1.0162 12.6066 - sobel:core/acc.imod#5.sva 0.0000 12.6066 - sobel:core/slc(acc.imod#5.sva)#1 0.0000 12.6066 - sobel:core/slc(acc.imod#5.sva)#1.itm 0.0000 12.6066 - sobel:core/conc#146 0.0000 12.6066 - sobel:core/conc#146.itm 0.0000 12.6066 - sobel:core/FRAME:acc#23 mgc_add_5_0_5_0_5 0.9376 13.5442 - sobel:core/FRAME:acc#23.itm 0.0000 13.5442 - sobel:core/FRAME:slc#5 0.0000 13.5442 - sobel:core/FRAME:slc#5.itm 0.0000 13.5442 - sobel:core/FRAME:not#43 mgc_not_1 0.0000 13.5442 - sobel:core/FRAME:not#43.itm 0.0000 13.5442 - sobel:core/conc#145 0.0000 13.5442 - sobel:core/conc#145.itm 0.0000 13.5442 - sobel:core/FRAME:acc#17 mgc_add_3_0_3_0_4 0.7609 14.3051 - sobel:core/FRAME:acc#17.itm 0.0000 14.3051 - sobel:core/FRAME:acc#18 mgc_add_4_0_4_0_5 0.8536 15.1586 - sobel:core/FRAME:acc#18.itm 0.0000 15.1586 - sobel:core/reg(FRAME:acc#18.itm#1) mgc_reg_pos_5_1_0_0_0_1_1 0.0000 15.1586 - - 6 sobel:core/reg(regs.regs(0).sva) sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414 - - Instance Component Delta Delay - -------- --------- ----- ----- - sobel:core/reg(regs.regs(0).sva) mgc_reg_pos_90_1_0_0_0_1_1 0.0000 0.0000 - sobel:core/regs.regs(0).sva 0.0000 0.0000 - sobel:core/slc(regs.regs(0).sva)#1 0.0000 0.0000 - sobel:core/slc(regs.regs(0).sva)#1.itm 0.0000 0.0000 - sobel:core/regs.operator[]#22:mux mgc_mux_10_2_4 0.9364 0.9364 - sobel:core/regs.operator[]#22:mux.itm 0.0000 0.9364 - sobel:core/FRAME:for#1:mul#7 mgc_mul_2_1_10_1_12 3.0868 4.0232 - sobel:core/FRAME:for#1:mul#7.itm 0.0000 4.0232 - sobel:core/FRAME:for#1:acc#12 mgc_add_16_0_12_1_16 1.6960 5.7193 - sobel:core/g(2).sva#1 0.0000 5.7193 - sobel:core/slc(g(2).sva#1) 0.0000 5.7193 - sobel:core/slc(g(2).sva#1).itm 0.0000 5.7193 - sobel:core/ACC2:acc#7 mgc_add_15_0_15_0_15 1.6269 7.3461 - sobel:core/ACC2:acc#7.itm 0.0000 7.3461 - sobel:core/ACC2:conc#1 0.0000 7.3461 - sobel:core/ACC2:conc#1.itm 0.0000 7.3461 - sobel:core/ACC2-3:acc#2 mgc_add_16_0_16_0_16 1.6898 9.0359 - sobel:core/ACC2-3:acc#2.itm 0.0000 9.0359 - sobel:core/ACC2:slc#1 0.0000 9.0359 - sobel:core/green#2.sg1.sva 0.0000 9.0359 - sobel:core/slc(green#2.sg1.sva)#12 0.0000 9.0359 - sobel:core/slc(green#2.sg1.sva)#12.itm 0.0000 9.0359 - sobel:core/FRAME:not#37 mgc_not_1 0.0000 9.0359 - sobel:core/FRAME:not#37.itm 0.0000 9.0359 - sobel:core/conc#155 0.0000 9.0359 - sobel:core/conc#155.itm 0.0000 9.0359 - sobel:core/FRAME:acc#12 mgc_add_3_0_3_0_4 0.7609 9.7968 - sobel:core/FRAME:acc#12.itm 0.0000 9.7968 - sobel:core/FRAME:acc#15 mgc_add_4_0_4_0_5 0.8536 10.6503 - sobel:core/FRAME:acc#15.itm 0.0000 10.6503 - sobel:core/FRAME:acc#16 mgc_add_5_0_4_0_6 0.9400 11.5904 - sobel:core/FRAME:acc#16.itm 0.0000 11.5904 - sobel:core/acc#5 mgc_add_6_0_6_0_6 1.0162 12.6066 - sobel:core/acc.imod#5.sva 0.0000 12.6066 - sobel:core/slc(acc.imod#5.sva)#1 0.0000 12.6066 - sobel:core/slc(acc.imod#5.sva)#1.itm 0.0000 12.6066 - sobel:core/conc#146 0.0000 12.6066 - sobel:core/conc#146.itm 0.0000 12.6066 - sobel:core/FRAME:acc#23 mgc_add_5_0_5_0_5 0.9376 13.5442 - sobel:core/FRAME:acc#23.itm 0.0000 13.5442 - sobel:core/FRAME:slc#5 0.0000 13.5442 - sobel:core/FRAME:slc#5.itm 0.0000 13.5442 - sobel:core/FRAME:not#43 mgc_not_1 0.0000 13.5442 - sobel:core/FRAME:not#43.itm 0.0000 13.5442 - sobel:core/conc#145 0.0000 13.5442 - sobel:core/conc#145.itm 0.0000 13.5442 - sobel:core/FRAME:acc#17 mgc_add_3_0_3_0_4 0.7609 14.3051 - sobel:core/FRAME:acc#17.itm 0.0000 14.3051 - sobel:core/FRAME:acc#18 mgc_add_4_0_4_0_5 0.8536 15.1586 - sobel:core/FRAME:acc#18.itm 0.0000 15.1586 - sobel:core/reg(FRAME:acc#18.itm#1) mgc_reg_pos_5_1_0_0_0_1_1 0.0000 15.1586 - - 7 sobel:core/reg(regs.regs(1).sva) sobel:core/reg(FRAME:acc#18.itm#1) 15.1586 4.8414 - - Instance Component Delta Delay - -------- --------- ----- ----- - sobel:core/reg(regs.regs(1).sva) mgc_reg_pos_90_1_0_0_0_1_1 0.0000 0.0000 - sobel:core/regs.regs(1).sva 0.0000 0.0000 - sobel:core/slc(regs.regs(1).sva)#1 0.0000 0.0000 - sobel:core/slc(regs.regs(1).sva)#1.itm 0.0000 0.0000 - sobel:core/regs.operator[]#22:mux mgc_mux_10_2_4 0.9364 0.9364 - sobel:core/regs.operator[]#22:mux.itm 0.0000 0.9364 - sobel:core/FRAME:for#1:mul#7 mgc_mul_2_1_10_1_12 3.0868 4.0232 - sobel:core/FRAME:for#1:mul#7.itm 0.0000 4.0232 - sobel:core/FRAME:for#1:acc#12 mgc_add_16_0_12_1_16 1.6960 5.7193 - sobel:core/g(2).sva#1 0.0000 5.7193 - sobel:core/slc(g(2).sva#1) 0.0000 5.7193 - sobel:core/slc(g(2).sva#1).itm 0.0000 5.7193 - sobel:core/ACC2:acc#7 mgc_add_15_0_15_0_15 1.6269 7.3461 - sobel:core/ACC2:acc#7.itm 0.0000 7.3461 - sobel:core/ACC2:conc#1 0.0000 7.3461 - sobel:core/ACC2:conc#1.itm 0.0000 7.3461 - sobel:core/ACC2-3:acc#2 mgc_add_16_0_16_0_16 1.6898 9.0359 - sobel:core/ACC2-3:acc#2.itm 0.0000 9.0359 - sobel:core/ACC2:slc#1 0.0000 9.0359 - sobel:core/green#2.sg1.sva 0.0000 9.0359 - sobel:core/slc(green#2.sg1.sva)#12 0.0000 9.0359 - sobel:core/slc(green#2.sg1.sva)#12.itm 0.0000 9.0359 - sobel:core/FRAME:not#37 mgc_not_1 0.0000 9.0359 - sobel:core/FRAME:not#37.itm 0.0000 9.0359 - sobel:core/conc#155 0.0000 9.0359 - sobel:core/conc#155.itm 0.0000 9.0359 - sobel:core/FRAME:acc#12 mgc_add_3_0_3_0_4 0.7609 9.7968 - sobel:core/FRAME:acc#12.itm 0.0000 9.7968 - sobel:core/FRAME:acc#15 mgc_add_4_0_4_0_5 0.8536 10.6503 - sobel:core/FRAME:acc#15.itm 0.0000 10.6503 - sobel:core/FRAME:acc#16 mgc_add_5_0_4_0_6 0.9400 11.5904 - sobel:core/FRAME:acc#16.itm 0.0000 11.5904 - sobel:core/acc#5 mgc_add_6_0_6_0_6 1.0162 12.6066 - sobel:core/acc.imod#5.sva 0.0000 12.6066 - sobel:core/slc(acc.imod#5.sva)#1 0.0000 12.6066 - sobel:core/slc(acc.imod#5.sva)#1.itm 0.0000 12.6066 - sobel:core/conc#146 0.0000 12.6066 - sobel:core/conc#146.itm 0.0000 12.6066 - sobel:core/FRAME:acc#23 mgc_add_5_0_5_0_5 0.9376 13.5442 - sobel:core/FRAME:acc#23.itm 0.0000 13.5442 - sobel:core/FRAME:slc#5 0.0000 13.5442 - sobel:core/FRAME:slc#5.itm 0.0000 13.5442 - sobel:core/FRAME:not#43 mgc_not_1 0.0000 13.5442 - sobel:core/FRAME:not#43.itm 0.0000 13.5442 - sobel:core/conc#145 0.0000 13.5442 - sobel:core/conc#145.itm 0.0000 13.5442 - sobel:core/FRAME:acc#17 mgc_add_3_0_3_0_4 0.7609 14.3051 - sobel:core/FRAME:acc#17.itm 0.0000 14.3051 - sobel:core/FRAME:acc#18 mgc_add_4_0_4_0_5 0.8536 15.1586 - sobel:core/FRAME:acc#18.itm 0.0000 15.1586 - sobel:core/reg(FRAME:acc#18.itm#1) mgc_reg_pos_5_1_0_0_0_1_1 0.0000 15.1586 - - 8 sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#30.itm#1) 15.1586 4.8414 - - Instance Component Delta Delay - -------- --------- ----- ----- - sobel:core/reg(regs.regs(2).lpi#1.dfm) mgc_reg_pos_90_1_0_0_0_1_1 0.0000 0.0000 - sobel:core/regs.regs(2).lpi#1.dfm 0.0000 0.0000 - sobel:core/slc(regs.regs(2).lpi#1.dfm) 0.0000 0.0000 - sobel:core/slc(regs.regs(2).lpi#1.dfm).itm 0.0000 0.0000 - sobel:core/regs.operator[]#23:mux mgc_mux_10_2_4 0.9364 0.9364 - sobel:core/regs.operator[]#23:mux.itm 0.0000 0.9364 - sobel:core/FRAME:for#1:mul#8 mgc_mul_2_1_10_1_12 3.0868 4.0232 - sobel:core/FRAME:for#1:mul#8.itm 0.0000 4.0232 - sobel:core/FRAME:for#1:acc#14 mgc_add_16_0_12_1_16 1.6960 5.7193 - sobel:core/b(2).sva#1 0.0000 5.7193 - sobel:core/slc(b(2).sva#1) 0.0000 5.7193 - sobel:core/slc(b(2).sva#1).itm 0.0000 5.7193 - sobel:core/ACC2:acc#8 mgc_add_15_0_15_0_15 1.6269 7.3461 - sobel:core/ACC2:acc#8.itm 0.0000 7.3461 - sobel:core/ACC2:conc#2 0.0000 7.3461 - sobel:core/ACC2:conc#2.itm 0.0000 7.3461 - sobel:core/ACC2-3:acc#3 mgc_add_16_0_16_0_16 1.6898 9.0359 - sobel:core/ACC2-3:acc#3.itm 0.0000 9.0359 - sobel:core/ACC2:slc#2 0.0000 9.0359 - sobel:core/blue#2.sg1.sva 0.0000 9.0359 - sobel:core/slc(blue#2.sg1.sva)#1 0.0000 9.0359 - sobel:core/slc(blue#2.sg1.sva)#1.itm 0.0000 9.0359 - sobel:core/FRAME:acc#25 mgc_add_3_0_3_0_4 0.7609 9.7968 - sobel:core/FRAME:acc#25.itm 0.0000 9.7968 - sobel:core/FRAME:acc#27 mgc_add_4_0_4_0_5 0.8536 10.6503 - sobel:core/FRAME:acc#27.itm 0.0000 10.6503 - sobel:core/FRAME:acc#28 mgc_add_5_0_4_0_6 0.9400 11.5904 - sobel:core/FRAME:acc#28.itm 0.0000 11.5904 - sobel:core/acc#7 mgc_add_6_0_6_0_6 1.0162 12.6066 - sobel:core/acc.imod#7.sva 0.0000 12.6066 - sobel:core/slc(acc.imod#7.sva)#1 0.0000 12.6066 - sobel:core/slc(acc.imod#7.sva)#1.itm 0.0000 12.6066 - sobel:core/conc#144 0.0000 12.6066 - sobel:core/conc#144.itm 0.0000 12.6066 - sobel:core/FRAME:acc#35 mgc_add_5_0_5_0_5 0.9376 13.5442 - sobel:core/FRAME:acc#35.itm 0.0000 13.5442 - sobel:core/FRAME:slc#6 0.0000 13.5442 - sobel:core/FRAME:slc#6.itm 0.0000 13.5442 - sobel:core/FRAME:not#41 mgc_not_1 0.0000 13.5442 - sobel:core/FRAME:not#41.itm 0.0000 13.5442 - sobel:core/conc#143 0.0000 13.5442 - sobel:core/conc#143.itm 0.0000 13.5442 - sobel:core/FRAME:acc#29 mgc_add_3_0_3_0_4 0.7609 14.3051 - sobel:core/FRAME:acc#29.itm 0.0000 14.3051 - sobel:core/FRAME:acc#30 mgc_add_4_0_4_0_5 0.8536 15.1586 - sobel:core/FRAME:acc#30.itm 0.0000 15.1586 - sobel:core/reg(FRAME:acc#30.itm#1) mgc_reg_pos_5_1_0_0_0_1_1 0.0000 15.1586 - - 9 sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#30.itm#1) 15.1586 4.8414 - - Instance Component Delta Delay - -------- --------- ----- ----- - sobel:core/reg(regs.regs(2).lpi#1.dfm) mgc_reg_pos_90_1_0_0_0_1_1 0.0000 0.0000 - sobel:core/regs.regs(2).lpi#1.dfm 0.0000 0.0000 - sobel:core/slc(regs.regs(2).lpi#1.dfm) 0.0000 0.0000 - sobel:core/slc(regs.regs(2).lpi#1.dfm).itm 0.0000 0.0000 - sobel:core/regs.operator[]#23:mux mgc_mux_10_2_4 0.9364 0.9364 - sobel:core/regs.operator[]#23:mux.itm 0.0000 0.9364 - sobel:core/FRAME:for#1:mul#8 mgc_mul_2_1_10_1_12 3.0868 4.0232 - sobel:core/FRAME:for#1:mul#8.itm 0.0000 4.0232 - sobel:core/FRAME:for#1:acc#14 mgc_add_16_0_12_1_16 1.6960 5.7193 - sobel:core/b(2).sva#1 0.0000 5.7193 - sobel:core/slc(b(2).sva#1) 0.0000 5.7193 - sobel:core/slc(b(2).sva#1).itm 0.0000 5.7193 - sobel:core/ACC2:acc#8 mgc_add_15_0_15_0_15 1.6269 7.3461 - sobel:core/ACC2:acc#8.itm 0.0000 7.3461 - sobel:core/ACC2:conc#2 0.0000 7.3461 - sobel:core/ACC2:conc#2.itm 0.0000 7.3461 - sobel:core/ACC2-3:acc#3 mgc_add_16_0_16_0_16 1.6898 9.0359 - sobel:core/ACC2-3:acc#3.itm 0.0000 9.0359 - sobel:core/ACC2:slc#2 0.0000 9.0359 - sobel:core/blue#2.sg1.sva 0.0000 9.0359 - sobel:core/slc(blue#2.sg1.sva)#1 0.0000 9.0359 - sobel:core/slc(blue#2.sg1.sva)#1.itm 0.0000 9.0359 - sobel:core/FRAME:acc#25 mgc_add_3_0_3_0_4 0.7609 9.7968 - sobel:core/FRAME:acc#25.itm 0.0000 9.7968 - sobel:core/FRAME:acc#27 mgc_add_4_0_4_0_5 0.8536 10.6503 - sobel:core/FRAME:acc#27.itm 0.0000 10.6503 - sobel:core/FRAME:acc#28 mgc_add_5_0_4_0_6 0.9400 11.5904 - sobel:core/FRAME:acc#28.itm 0.0000 11.5904 - sobel:core/acc#7 mgc_add_6_0_6_0_6 1.0162 12.6066 - sobel:core/acc.imod#7.sva 0.0000 12.6066 - sobel:core/slc(acc.imod#7.sva)#2 0.0000 12.6066 - sobel:core/slc(acc.imod#7.sva)#2.itm 0.0000 12.6066 - sobel:core/FRAME:not#21 mgc_not_3 0.0000 12.6066 - sobel:core/FRAME:not#21.itm 0.0000 12.6066 - sobel:core/FRAME:conc#29 0.0000 12.6066 - sobel:core/FRAME:conc#29.itm 0.0000 12.6066 - sobel:core/FRAME:acc#35 mgc_add_5_0_5_0_5 0.9376 13.5442 - sobel:core/FRAME:acc#35.itm 0.0000 13.5442 - sobel:core/FRAME:slc#6 0.0000 13.5442 - sobel:core/FRAME:slc#6.itm 0.0000 13.5442 - sobel:core/FRAME:not#41 mgc_not_1 0.0000 13.5442 - sobel:core/FRAME:not#41.itm 0.0000 13.5442 - sobel:core/conc#143 0.0000 13.5442 - sobel:core/conc#143.itm 0.0000 13.5442 - sobel:core/FRAME:acc#29 mgc_add_3_0_3_0_4 0.7609 14.3051 - sobel:core/FRAME:acc#29.itm 0.0000 14.3051 - sobel:core/FRAME:acc#30 mgc_add_4_0_4_0_5 0.8536 15.1586 - sobel:core/FRAME:acc#30.itm 0.0000 15.1586 - sobel:core/reg(FRAME:acc#30.itm#1) mgc_reg_pos_5_1_0_0_0_1_1 0.0000 15.1586 - - 10 sobel:core/reg(regs.regs(2).lpi#1.dfm) sobel:core/reg(FRAME:acc#30.itm#1) 15.1586 4.8414 - - Instance Component Delta Delay - -------- --------- ----- ----- - sobel:core/reg(regs.regs(2).lpi#1.dfm) mgc_reg_pos_90_1_0_0_0_1_1 0.0000 0.0000 - sobel:core/regs.regs(2).lpi#1.dfm 0.0000 0.0000 - sobel:core/slc(regs.regs(2).lpi#1.dfm) 0.0000 0.0000 - sobel:core/slc(regs.regs(2).lpi#1.dfm).itm 0.0000 0.0000 - sobel:core/regs.operator[]#23:mux mgc_mux_10_2_4 0.9364 0.9364 - sobel:core/regs.operator[]#23:mux.itm 0.0000 0.9364 - sobel:core/FRAME:for#1:mul#8 mgc_mul_2_1_10_1_12 3.0868 4.0232 - sobel:core/FRAME:for#1:mul#8.itm 0.0000 4.0232 - sobel:core/FRAME:for#1:acc#14 mgc_add_16_0_12_1_16 1.6960 5.7193 - sobel:core/b(2).sva#1 0.0000 5.7193 - sobel:core/slc(b(2).sva#1) 0.0000 5.7193 - sobel:core/slc(b(2).sva#1).itm 0.0000 5.7193 - sobel:core/ACC2:acc#8 mgc_add_15_0_15_0_15 1.6269 7.3461 - sobel:core/ACC2:acc#8.itm 0.0000 7.3461 - sobel:core/ACC2:conc#2 0.0000 7.3461 - sobel:core/ACC2:conc#2.itm 0.0000 7.3461 - sobel:core/ACC2-3:acc#3 mgc_add_16_0_16_0_16 1.6898 9.0359 - sobel:core/ACC2-3:acc#3.itm 0.0000 9.0359 - sobel:core/ACC2:slc#2 0.0000 9.0359 - sobel:core/blue#2.sg1.sva 0.0000 9.0359 - sobel:core/slc(blue#2.sg1.sva)#3 0.0000 9.0359 - sobel:core/slc(blue#2.sg1.sva)#3.itm 0.0000 9.0359 - sobel:core/FRAME:not#18 mgc_not_3 0.0000 9.0359 - sobel:core/FRAME:not#18.itm 0.0000 9.0359 - sobel:core/FRAME:acc#25 mgc_add_3_0_3_0_4 0.7609 9.7968 - sobel:core/FRAME:acc#25.itm 0.0000 9.7968 - sobel:core/FRAME:acc#27 mgc_add_4_0_4_0_5 0.8536 10.6503 - sobel:core/FRAME:acc#27.itm 0.0000 10.6503 - sobel:core/FRAME:acc#28 mgc_add_5_0_4_0_6 0.9400 11.5904 - sobel:core/FRAME:acc#28.itm 0.0000 11.5904 - sobel:core/acc#7 mgc_add_6_0_6_0_6 1.0162 12.6066 - sobel:core/acc.imod#7.sva 0.0000 12.6066 - sobel:core/slc(acc.imod#7.sva)#2 0.0000 12.6066 - sobel:core/slc(acc.imod#7.sva)#2.itm 0.0000 12.6066 - sobel:core/FRAME:not#21 mgc_not_3 0.0000 12.6066 - sobel:core/FRAME:not#21.itm 0.0000 12.6066 - sobel:core/FRAME:conc#29 0.0000 12.6066 - sobel:core/FRAME:conc#29.itm 0.0000 12.6066 - sobel:core/FRAME:acc#35 mgc_add_5_0_5_0_5 0.9376 13.5442 - sobel:core/FRAME:acc#35.itm 0.0000 13.5442 - sobel:core/FRAME:slc#6 0.0000 13.5442 - sobel:core/FRAME:slc#6.itm 0.0000 13.5442 - sobel:core/FRAME:not#41 mgc_not_1 0.0000 13.5442 - sobel:core/FRAME:not#41.itm 0.0000 13.5442 - sobel:core/conc#143 0.0000 13.5442 - sobel:core/conc#143.itm 0.0000 13.5442 - sobel:core/FRAME:acc#29 mgc_add_3_0_3_0_4 0.7609 14.3051 - sobel:core/FRAME:acc#29.itm 0.0000 14.3051 - sobel:core/FRAME:acc#30 mgc_add_4_0_4_0_5 0.8536 15.1586 - sobel:core/FRAME:acc#30.itm 0.0000 15.1586 - sobel:core/reg(FRAME:acc#30.itm#1) mgc_reg_pos_5_1_0_0_0_1_1 0.0000 15.1586 - - - Register Input and Register-to-Output Slack - Clock period or pin-to-reg delay constraint (clk): 20.0 - Clock uncertainty constraint (clk) : 0.0 - - Instance Port Slack (Delay) Messages - ----------------------------------------------- -------------------------------- ------- ------- -------- - sobel:core/reg(vout:rsc:mgc_out_stdreg.d) mux.itm 14.0161 5.9839 - sobel:core/reg(FRAME:acc#41.itm#1.sg2) FRAME:acc#43.itm 7.2622 12.7378 - sobel:core/reg(FRAME:acc#41.itm#1.sg1) slc(FRAME:mul.sdt)#2.itm 7.9199 12.0801 - sobel:core/reg(FRAME:acc#41.itm#3) FRAME:acc#44.itm 6.9824 13.0176 - sobel:core/reg(FRAME:mul#1.itm#1) FRAME:mul#1.itm 8.1180 11.8820 - sobel:core/reg(red:slc(red#2.sg1).itm#1) slc(red#2.sg1.sva)#1.itm 10.9641 9.0359 - sobel:core/reg(FRAME:acc#37.itm#1) FRAME:acc#37.itm 4.8414 15.1586 - sobel:core/reg(FRAME:slc(acc.imod#3)#4.itm#1) slc(acc.imod#3.sva).itm 7.3934 12.6066 - sobel:core/reg(FRAME:mul#4.itm#1) FRAME:mul#4.itm 7.9199 12.0801 - sobel:core/reg(FRAME:mul#5.itm#1) FRAME:mul#5.itm 8.1180 11.8820 - sobel:core/reg(blue:slc(blue#2.sg1).itm#1) slc(blue#2.sg1.sva)#2.itm 10.9641 9.0359 - sobel:core/reg(FRAME:acc#30.itm#1) FRAME:acc#30.itm 4.8414 15.1586 - sobel:core/reg(FRAME:slc(acc.imod#7)#4.itm#1) slc(acc.imod#7.sva).itm 7.3934 12.6066 - sobel:core/reg(blue:slc(blue#2.sg1)#12.itm#1) slc(blue#2.sg1.sva).itm 10.9641 9.0359 - sobel:core/reg(FRAME:mul#2.itm#1) FRAME:mul#2.itm 7.9199 12.0801 - sobel:core/reg(FRAME:mul#3.itm#1) FRAME:mul#3.itm 8.1180 11.8820 - sobel:core/reg(green:slc(green#2.sg1).itm#1) slc(green#2.sg1.sva)#2.itm 10.9641 9.0359 - sobel:core/reg(FRAME:acc#18.itm#1) FRAME:acc#18.itm 4.8414 15.1586 - sobel:core/reg(FRAME:slc(acc.imod#5)#4.itm#1) slc(acc.imod#5.sva).itm 7.3934 12.6066 - sobel:core/reg(green:slc(green#2.sg1)#12.itm#1) slc(green#2.sg1.sva).itm 10.9641 9.0359 - sobel:core/reg(exit:FRAME:for#1.sva#2.st#1) FRAME:for#1:not#7.itm 18.6898 1.3102 - sobel:core/reg(exit:FRAME:for.lpi#1.dfm.st#1) exit:FRAME:for.lpi#1.dfm 18.3131 1.6869 - sobel:core/reg(i#7.lpi#1) mux#1.itm 17.5333 2.4667 - sobel:core/reg(exit:FRAME:for.lpi#1) mux#2.itm 17.7958 2.2042 - sobel:core/reg(exit:FRAME:for#1.lpi#1.dfm#4) exit:FRAME:for#1.lpi#1.dfm#4:mx0 15.7649 4.2351 - sobel:core/reg(exit:FRAME#1.sva) FRAME:and.itm 15.7649 4.2351 - sobel:core/reg(main.stage_0#2) Cn1_1#4 20.0000 0.0000 - sobel:core/reg(regs.regs(2).lpi#1.dfm) regs.regs(2).lpi#1.dfm:mx0 13.2803 6.7197 - sobel:core/reg(regs.regs(1).sva) regs.regs(1).sva.dfm:mx0 13.2803 6.7197 - sobel:core/reg(regs.regs(0).sva) regs.regs(0).sva.dfm:mx0 13.2803 6.7197 - sobel:core/reg(exit:FRAME.lpi#1.dfm#2) exit:FRAME.lpi#1.dfm#2:mx0 16.0328 3.9672 - sobel:core/reg(b(1).sg1.lpi#1) mux#8.itm 13.0411 6.9589 - sobel:core/reg(g(1).sg1.lpi#1) mux#9.itm 13.0411 6.9589 - sobel:core/reg(r(1).sg1.lpi#1) mux#10.itm 13.0411 6.9589 - sobel:core/reg(i#6.lpi#1) mux#11.itm 18.4535 1.5465 - sobel:core/reg(b(2).lpi#1) mux#12.itm 13.2803 6.7197 - sobel:core/reg(b(0).lpi#1) mux#13.itm 13.2803 6.7197 - sobel:core/reg(g(2).lpi#1) mux#14.itm 13.2803 6.7197 - sobel:core/reg(g(0).lpi#1) mux#15.itm 13.2803 6.7197 - sobel:core/reg(r(2).lpi#1) mux#16.itm 13.2803 6.7197 - sobel:core/reg(r(0).lpi#1) mux#17.itm 13.2803 6.7197 - sobel:core/reg(FRAME:p#1.lpi#1) mux#18.itm 17.4604 2.5396 - sobel vout:rsc.z 20.0000 0.0000 - - Operator Bitwidth Summary - Operation Size (bits) Count - ---------- ----------- ----- - add - - 19 1 - - 16 15 - - 15 6 - - 12 4 - - 10 4 - - 8 4 - - 6 7 - - 5 12 - - 4 12 - - 2 6 - and - - 3 1 - - 2 18 - mul - - 12 15 - - 11 3 - - 9 3 - mux - - 2 15 - - 1 19 - nand - - 3 1 - - 2 4 - nor - - 2 4 - not - - 3 12 - - 1 28 - or - - 3 3 - - 2 8 - read_port - - 90 1 - reg - - 90 3 - - 30 1 - - 19 1 - - 16 6 - - 15 3 - - 11 2 - - 9 3 - - 6 4 - - 5 3 - - 2 4 - - 1 12 - write_port - - 30 1 - - End of Report |