diff options
Diffstat (limited to 'sobel_filter/Sobel/sobel.v9/rtl.v.psr')
-rw-r--r-- | sobel_filter/Sobel/sobel.v9/rtl.v.psr | 289 |
1 files changed, 289 insertions, 0 deletions
diff --git a/sobel_filter/Sobel/sobel.v9/rtl.v.psr b/sobel_filter/Sobel/sobel.v9/rtl.v.psr new file mode 100644 index 0000000..1e55f8c --- /dev/null +++ b/sobel_filter/Sobel/sobel.v9/rtl.v.psr @@ -0,0 +1,289 @@ +puts {-- Note: Precision Synthesis Started} + +proc get_state { args } { + set state {} + catch { + set impl [get_impl_property -name] + set psi [open $impl/${impl}.psi r] + while {[gets $psi line] >= 0} { + if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} { + break + } + } + close $psi + } + set state +} +proc run_setup { args } { + ## Setup Project + new_project -name psr_v -folder . -createimpl_name psr_v_impl -force + set_project_property -usetempdir false + set_input_dir . + setup_design -var "analyze_extra_options=-override -keeplast" + + ## Add source HDL files + add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v9/rtl_mgc_ioport.v}} -format verilog + add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v9/rtl_mgc_ioport_v2001.v}} -format verilog + add_input_file {{//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Sobel Filter Catapult/Sobel/sobel.v9/rtl.v}} -format verilog + setup_design -design=sobel + + ## Setup global frequence + setup_design -frequency 50.0 + + ## Setup technology settings + setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6 + setup_design -variable bumpup_device=true + setup_design -addio=true + setup_design -edif=true + setup_design -retiming=false + +if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} { +setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog +} + + ## Add timing constraint file + add_input_file ./rtl.v.psr_timing -format SDC + + save_project +} + +proc run_mapped { args } { + ## Synthesize design + puts "-- Starting synthesis for design 'sobel': [clock format [clock seconds]]" + compile + + # When a clock is not detected (e.g. combinational designs) Precision RTL + # creates the fake clock "Design_Clock" with the period corresponding to the frequency + # setting in the setup_design. + + ## IO TIMING CONSTRAINTS + set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0] + # These constraints prevent the 'No initialized timing analysis; + # cannot define a Clock.' error message in combinational designs + set_input_delay 0.0 -clock $hls_design_clk [all_inputs] + set_output_delay 0.0 -clock $hls_design_clk [all_outputs] + + synthesize + puts "-- Synthesis finished for design 'sobel': [clock format [clock seconds]]" + + puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0" + puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0" + + puts "-- Characterization mode: p2p " + + # Gather area and timing information + puts "-- Synthesis area report for design 'sobel'" + report_area -cell_usage + puts "-- END Synthesis area report for design 'sobel'" + + puts "-- Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'" + set_max_delay 20.000000 -design rtl -from en -to vout_rsc_z(29:0) + report_timing -from en -to vout_rsc_z(29:0) -num_paths 1 -detail + puts "-- END Synthesis input_to_output:timing report for design 'sobel' '0' 'INOUT' port 'en' '2' 'OUT' port 'vout_rsc_z'" + + puts "-- Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'" + set_max_delay 20.000000 -design rtl -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) + report_timing -from vin_rsc_z(89:0) -to vout_rsc_z(29:0) -num_paths 1 -detail + puts "-- END Synthesis input_to_output:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '2' 'OUT' port 'vout_rsc_z'" + + + set regs_clk [all_registers -clock {clk}] + if { [llength ${regs_clk} ] > 0 } { + puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'" + set_input_delay -design rtl -clock clk 0.0 en + report_timing -from en -to $regs_clk -num_paths 1 -detail + puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'" + + puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'" + set_input_delay -design rtl -clock clk 0.0 vin_rsc_z(89:0) + report_timing -from vin_rsc_z(89:0) -to $regs_clk -num_paths 1 -detail + puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'clk'" + + # this workaround ensures that there is a input delay for the cases + # where Precision does not have a complete timing model for a particular device + # the reported value is used if no other input delay value is reported + #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'" + #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail + #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'" + } + + set regs_en [all_registers -clock {en}] + if { [llength ${regs_en} ] > 0 } { + puts "-- Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'" + set_input_delay -design rtl -clock en 0.0 vin_rsc_z(89:0) + report_timing -from vin_rsc_z(89:0) -to $regs_en -num_paths 1 -detail + puts "-- END Synthesis input_to_register:timing report for design 'sobel' '1' 'IN' port 'vin_rsc_z' '0' 'INOUT' CLOCK 'en'" + + # this workaround ensures that there is a input delay for the cases + # where Precision does not have a complete timing model for a particular device + # the reported value is used if no other input delay value is reported + #puts "-- Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'" + #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail + #puts "-- END Synthesis input_to_register:timing report for design 'sobel' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'" + } + + set regsi_clk [all_registers -clock {clk}] + set regso_clk [all_registers -clock {clk}] + if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } { + puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'" + report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail + puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'" + } + + set regsi_clk [all_registers -clock {clk}] + set regso_en [all_registers -clock {en}] + if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } { + puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'" + report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail + puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'" + } + + set regsi_en [all_registers -clock {en}] + set regso_clk [all_registers -clock {clk}] + if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } { + puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'" + report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail + puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'" + } + + set regsi_en [all_registers -clock {en}] + set regso_en [all_registers -clock {en}] + if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } { + puts "-- Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'" + report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail + puts "-- END Synthesis register_to_register:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'" + } + + set regs_clk [all_registers -clock {clk}] + if { [llength ${regs_clk} ] > 0 } { + puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'" + set_output_delay -design rtl -clock clk 0.0 vout_rsc_z(29:0) + report_timing -from [all_registers -clock clk] -to vout_rsc_z(29:0) -num_paths 1 -detail + puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'clk' '2' 'OUT' port 'vout_rsc_z'" + } + + set regs_en [all_registers -clock {en}] + if { [llength ${regs_en} ] > 0 } { + puts "-- Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'" + set_output_delay -design rtl -clock en 0.0 vout_rsc_z(29:0) + report_timing -from [all_registers -clock en] -to vout_rsc_z(29:0) -num_paths 1 -detail + puts "-- END Synthesis register_to_output:timing report for design 'sobel' '0' 'INOUT' CLOCK 'en' '2' 'OUT' port 'vout_rsc_z'" + } + + save_project +} + +proc remove_sdf_annotate { infile outfile } { + if { ![file exists $infile] } { + puts "Error - input file $infile not found" + return + } + set s [open $infile "r"] + set d [open $outfile "w"] + while { ! [eof $s] } { + gets $s line + if { [string match "*\$sdf_annotate*" $line] == 0 } { + puts $d $line + } + } + close $s + close $d +} + +proc vendor_vars { vendor tech lang stage } { + # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts } + set SDFINST "" + switch -glob -- "${vendor}-${tech}" { + "Xilinx*" { + if { $stage == "gate" } { + set SDFINST scverify_top/rtl + } + if { $lang == "vhdl" } { + return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST] + } else { + return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST] + } + } + "Altera*" { + if { $stage == "gate" } { + set SDFINST scverify_top/rtl + } + if { $lang == "vhdl" } { + return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST] + } else { + return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST] + } + } + } + } +proc run_gate { args } { + puts "PROC run_gate $args - enable_run_pnr=1" + place_and_route cl + save_project + puts "-- Synthesis design report for design 'sobel'" + puts "-- Implementation directory: [MGS_Core::get_design_impls -active]" + puts "-- END Synthesis design report for design 'sobel'" +} + +proc run_flow { argv } { + global gui_mode + array set db $argv + if {[info exists db(-run_state)]} { + set db(run_state) $db(-run_state) + } + if {![info exists db(run_state)]} { + set db(run_state) {mapped} + } + + if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} { + run_setup + } + # verify that addio option is correct in the project + if { [string is true [report_project -addio]] != [string is true true] } { + puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation" + setup_design -addio=true + compile + run_mapped + } + if {$db(run_state) == {setup}} return + + if {![info exists db(gui_mode)] || !$db(gui_mode) } { + set cstate [get_state] + if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped + if {$db(run_state) == {mapped}} { + set mapped_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v9 mapped.v] + puts "-- Writing mapped netlist for 'sobel' to file '$mapped_netlist'" + auto_write $mapped_netlist + return + } + + if {[get_state] != {pnr}} run_gate + if {$db(run_state) == {gate}} { + set gate_netlist [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v9 gate.v] + set gate_sdf [file join //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/SOBELF~1/Sobel/sobel.v9 gate.v.sdf] + set IMPL_DIR [MGS_Core::get_design_impls -active] + set DESIGNNAME [report_project -basename] + set vendor [report_project -manufacturer] + set tech [report_project -libname] + set lang v + set vendor_var_list [vendor_vars $vendor $tech $lang "gate"] + foreach { vname vval } $vendor_var_list { + set $vname $vval + } + set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF} + if { $lang == "v" } { + puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'" + remove_sdf_annotate $NETLIST_FILE $gate_netlist + } else { + puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'" + file copy -force $NETLIST_FILE $gate_netlist + } + set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF} + puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'" + file copy -force $NETLIST_SDF $gate_sdf + return + } + + } +} +run_flow [expr {[info exists argv]?$argv:{}}] |