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Diffstat (limited to 'sobel_filter/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v')
| -rw-r--r-- | sobel_filter/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v | 70 |
1 files changed, 0 insertions, 70 deletions
diff --git a/sobel_filter/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v b/sobel_filter/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v deleted file mode 100644 index 2756db0..0000000 --- a/sobel_filter/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v +++ /dev/null @@ -1,70 +0,0 @@ -// -------------------------------------------------------------------- -// Copyright (c) 2007 by Terasic Technologies Inc. -// -------------------------------------------------------------------- -// -// Permission: -// -// Terasic grants permission to use and modify this code for use -// in synthesis for all Terasic Development Boards and Altera Development -// Kits made by Terasic. Other use of this code, including the selling -// ,duplication, or modification of any portion is strictly prohibited. -// -// Disclaimer: -// -// This VHDL/Verilog or C/C++ source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Terasic provides no warranty regarding the use -// or functionality of this code. -// -// -------------------------------------------------------------------- -// -// Terasic Technologies Inc -// 356 Fu-Shin E. Rd Sec. 1. JhuBei City, -// HsinChu County, Taiwan -// 302 -// -// web: http://www.terasic.com/ -// email: support@terasic.com -// -// -------------------------------------------------------------------- -// -// Major Functions: SEG7_LUT -// -// -------------------------------------------------------------------- -// -// Revision History : -// -------------------------------------------------------------------- -// Ver :| Author :| Mod. Date :| Changes Made: -// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision -// -------------------------------------------------------------------- - -module SEG7_LUT ( oSEG,iDIG ); -input [3:0] iDIG; -output [6:0] oSEG; -reg [6:0] oSEG; - -always @(iDIG) -begin - case(iDIG) - 4'h1: oSEG = 7'b1111001; // ---t---- - 4'h2: oSEG = 7'b0100100; // | | - 4'h3: oSEG = 7'b0110000; // lt rt - 4'h4: oSEG = 7'b0011001; // | | - 4'h5: oSEG = 7'b0010010; // ---m---- - 4'h6: oSEG = 7'b0000010; // | | - 4'h7: oSEG = 7'b1111000; // lb rb - 4'h8: oSEG = 7'b0000000; // | | - 4'h9: oSEG = 7'b0011000; // ---b---- - 4'ha: oSEG = 7'b0001000; - 4'hb: oSEG = 7'b0000011; - 4'hc: oSEG = 7'b1000110; - 4'hd: oSEG = 7'b0100001; - 4'he: oSEG = 7'b0000110; - 4'hf: oSEG = 7'b0001110; - 4'h0: oSEG = 7'b1000000; - endcase -end - -endmodule |