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-- Catapult University Version: Report
-- ---------------------------- ---------------------------------------------------
-- Version: 2011a.126 Production Release
-- Build Date: Wed Aug 8 00:52:07 PDT 2012
-- Generated by: mg3115@EEWS104A-015
-- Generated date: Tue Mar 01 15:39:34 +0000 2016
Solution Settings: dot_product.v10
Current state: schedule
Project: dot_product
Design Input Files Specified
$PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
$PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
$MGC_HOME/shared/include/ac_int.h
$PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
$MGC_HOME/shared/include/ac_int.h
$PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
$PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
$MGC_HOME/shared/include/ac_int.h
$MGC_HOME/shared/include/mc_scverify.h
Processes/Blocks in Design
Process Real Operation(s) count Latency Throughput Reset Length II Comments
----------------- ----------------------- ------- ---------- ------------ -- --------
/dot_product/core 12 5 5 0 1
Design Total: 12 5 5 0 1
Clock Information
Clock Signal Edge Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks
------------ ------ ------ ----------------- ----------- ------------------------
clk rising 20.000 20.00 0.000000 /dot_product/core
I/O Data Ranges
Port Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange
------------- ---- -------- --------- --------- ------- -------- --------
input_a:rsc.z IN Unsigned 8
input_b:rsc.z IN Unsigned 8
clk IN Unsigned 1
en IN Unsigned 1
arst_n IN Unsigned 1
output:rsc.z OUT Unsigned 8
Memory Resources
Resource Name: /dot_product/input_a:rsc
Memory Component: mgc_in_wire Size: 1 x 8
External: true Packing Mode: sidebyside
Memory Map:
Variable Indices Phys Memory Address
-------------------- ------- -----------------------
/dot_product/input_a 0:7 00000000-00000000 (0-0)
Resource Name: /dot_product/input_b:rsc
Memory Component: mgc_in_wire Size: 1 x 8
External: true Packing Mode: sidebyside
Memory Map:
Variable Indices Phys Memory Address
-------------------- ------- -----------------------
/dot_product/input_b 0:7 00000000-00000000 (0-0)
Resource Name: /dot_product/output:rsc
Memory Component: mgc_out_stdreg Size: 1 x 8
External: true Packing Mode: sidebyside
Memory Map:
Variable Indices Phys Memory Address
------------------- ------- -----------------------
/dot_product/output 0:7 00000000-00000000 (0-0)
Multi-Cycle (Combinational) Component Usage
Instance Component Name Delay
-------- -------------- -----
Loops
Process Loop Iterations C-Steps Total Cycles Duration Unroll Init Comments
----------------- ---------------- ---------- ------- ------------- ---------- ------ ---- --------
/dot_product/core main Infinite 2 5 100.00 ns 1
Loop Execution Profile
Process Loop Total Cycles % of Overall Design Cycles Throughput Cycles Comments
----------------- ---------------- ------------ -------------------------- ----------------- --------
/dot_product/core main 5 100.00 5
End of Report
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