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set a(0-312) {NAME MAC:asn TYPE ASSIGN PAR 0-311 XREFS 1207 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-335 {}}} SUCCS {{259 0 0-313 {}} {256 0 0-335 {}}} CYCLES {}}
set a(0-313) {NAME MAC:select TYPE SELECT PAR 0-311 XREFS 1208 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{259 0 0-312 {}}} SUCCS {} CYCLES {}}
set a(0-314) {NAME MAC:asn#4 TYPE ASSIGN PAR 0-311 XREFS 1209 LOC {0 1.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{262 0 0-335 {}}} SUCCS {{259 0 0-315 {}} {256 0 0-335 {}}} CYCLES {}}
set a(0-315) {NAME MAC:not#1 TYPE NOT PAR 0-311 XREFS 1210 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{259 0 0-314 {}}} SUCCS {{259 0 0-316 {}}} CYCLES {}}
set a(0-316) {NAME MAC:exs TYPE SIGNEXTEND PAR 0-311 XREFS 1211 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{259 0 0-315 {}}} SUCCS {{259 0 0-317 {}}} CYCLES {}}
set a(0-317) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(8,2) AREA_SCORE 5.84 QUANTITY 1 NAME MAC:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-311 XREFS 1212 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.9273052062638539 1 0.9273052062638539} PREDS {{262 0 0-333 {}} {259 0 0-316 {}}} SUCCS {{258 0 0-321 {}} {256 0 0-333 {}}} CYCLES {}}
set a(0-318) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-311 XREFS 1213 LOC {1 0.0 1 0.761104025 1 0.761104025 1 0.761104025 1 0.761104025} PREDS {{80 0 0-319 {}}} SUCCS {{80 0 0-319 {}} {258 0 0-320 {}}} CYCLES {}}
set a(0-319) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-311 XREFS 1214 LOC {1 0.0 1 0.761104025 1 0.761104025 1 0.761104025 1 0.761104025} PREDS {{80 0 0-318 {}}} SUCCS {{80 0 0-318 {}} {259 0 0-320 {}}} CYCLES {}}
set a(0-320) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-311 XREFS 1215 LOC {1 0.0 1 0.761104025 1 0.761104025 1 0.9273051907433434 1 0.9273051907433434} PREDS {{258 0 0-318 {}} {259 0 0-319 {}}} SUCCS {{259 0 0-321 {}}} CYCLES {}}
set a(0-321) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME MAC:acc#3 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-311 XREFS 1216 LOC {1 0.16620122499999998 1 0.92730525 1 0.92730525 1 0.9999999527684257 1 0.9999999527684257} PREDS {{258 0 0-317 {}} {259 0 0-320 {}}} SUCCS {{258 0 0-332 {}} {258 0 0-333 {}}} CYCLES {}}
set a(0-322) {NAME MAC:asn#5 TYPE ASSIGN PAR 0-311 XREFS 1217 LOC {0 1.0 1 0.88229375 1 0.88229375 1 0.88229375} PREDS {{262 0 0-335 {}}} SUCCS {{259 0 0-323 {}} {256 0 0-335 {}}} CYCLES {}}
set a(0-323) {NAME MAC:not#2 TYPE NOT PAR 0-311 XREFS 1218 LOC {1 0.0 1 0.88229375 1 0.88229375 1 0.88229375} PREDS {{259 0 0-322 {}}} SUCCS {{259 0 0-324 {}}} CYCLES {}}
set a(0-324) {NAME MAC:exs#1 TYPE SIGNEXTEND PAR 0-311 XREFS 1219 LOC {1 0.0 1 0.88229375 1 0.88229375 1 0.88229375} PREDS {{259 0 0-323 {}}} SUCCS {{259 0 0-325 {}}} CYCLES {}}
set a(0-325) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(3,2) AREA_SCORE 2.19 QUANTITY 1 NAME MAC:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-311 XREFS 1220 LOC {1 0.0 1 0.88229375 1 0.88229375 1 0.8987004812638539 1 0.8987004812638539} PREDS {{262 0 0-334 {}} {259 0 0-324 {}}} SUCCS {{259 0 0-326 {}} {256 0 0-334 {}}} CYCLES {}}
set a(0-326) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,2,1,3) AREA_SCORE 4.00 QUANTITY 1 NAME MAC:acc#4 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-311 XREFS 1221 LOC {1 0.016406775 1 0.898700525 1 0.898700525 1 0.9464762270241717 1 0.9464762270241717} PREDS {{259 0 0-325 {}}} SUCCS {{259 0 0-327 {}} {258 0 0-334 {}}} CYCLES {}}
set a(0-327) {NAME MAC:asn#3 TYPE ASSIGN PAR 0-311 XREFS 1222 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 1 0.946476275} PREDS {{259 0 0-326 {}}} SUCCS {{259 0 0-328 {}}} CYCLES {}}
set a(0-328) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,4) AREA_SCORE 5.30 QUANTITY 1 NAME MAC:acc TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-311 XREFS 1223 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 1 0.9999999399089293 1 0.9999999399089293} PREDS {{259 0 0-327 {}}} SUCCS {{259 0 0-329 {}}} CYCLES {}}
set a(0-329) {NAME MAC:slc TYPE READSLICE PAR 0-311 XREFS 1224 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-328 {}}} SUCCS {{259 0 0-330 {}}} CYCLES {}}
set a(0-330) {NAME MAC:not TYPE NOT PAR 0-311 XREFS 1225 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-329 {}}} SUCCS {{259 0 0-331 {}} {258 0 0-335 {}}} CYCLES {}}
set a(0-331) {NAME MAC:select#1 TYPE SELECT PAR 0-311 XREFS 1226 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-330 {}}} SUCCS {{131 0 0-332 {}}} CYCLES {}}
set a(0-332) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(3,8) AREA_SCORE 0.00 QUANTITY 1 NAME io_write(output:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-311 XREFS 1227 LOC {1 1.0 1 1.0 1 1.0 2 0.0 1 0.9999} PREDS {{260 0 0-332 {}} {258 0 0-321 {}} {131 0 0-331 {}}} SUCCS {{260 0 0-332 {}}} CYCLES {}}
set a(0-333) {NAME MAC:asn(acc.lpi) TYPE ASSIGN PAR 0-311 XREFS 1228 LOC {1 0.23889597499999998 1 1.0 1 1.0 2 0.910898475} PREDS {{260 0 0-333 {}} {256 0 0-317 {}} {258 0 0-321 {}}} SUCCS {{262 0 0-317 {}} {260 0 0-333 {}}} CYCLES {}}
set a(0-334) {NAME MAC:asn(i#1.lpi) TYPE ASSIGN PAR 0-311 XREFS 1229 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 2 0.88229375} PREDS {{260 0 0-334 {}} {256 0 0-325 {}} {258 0 0-326 {}}} SUCCS {{262 0 0-325 {}} {260 0 0-334 {}}} CYCLES {}}
set a(0-335) {NAME MAC:asn(exit:MAC.lpi) TYPE ASSIGN PAR 0-311 XREFS 1230 LOC {1 0.11770625 1 1.0 1 1.0 2 0.88229375} PREDS {{260 0 0-335 {}} {256 0 0-312 {}} {256 0 0-314 {}} {256 0 0-322 {}} {258 0 0-330 {}}} SUCCS {{262 0 0-312 {}} {262 0 0-314 {}} {262 0 0-322 {}} {260 0 0-335 {}}} CYCLES {}}
set a(0-311) {CHI {0-312 0-313 0-314 0-315 0-316 0-317 0-318 0-319 0-320 0-321 0-322 0-323 0-324 0-325 0-326 0-327 0-328 0-329 0-330 0-331 0-332 0-333 0-334 0-335} ITERATIONS Infinite LATENCY 5 RESET_LATENCY 0 CSTEPS 2 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 5 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 2.0 CYCLES_IN 5 TOTAL_CYCLES_IN 5 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 5 NAME main TYPE LOOP DELAY {120.00 ns} PAR {} XREFS 1231 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
set a(0-311-TOTALCYCLES) {5}
set a(0-311-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(8,2) 0-317 mgc_ioport.mgc_in_wire(1,8) 0-318 mgc_ioport.mgc_in_wire(2,8) 0-319 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8) 0-320 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) 0-321 mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(3,2) 0-325 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,1,3) 0-326 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,4) 0-328 mgc_ioport.mgc_out_stdreg(3,8) 0-332}
set a(0-311-PROC_NAME) {core}
set a(0-311-HIER_NAME) {/dot_product/core}
set a(TOP) {0-311}
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