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# Program: Catapult University Version
# Version: 2011a.126
# File: Nlview netlist
module new "dot_product:core" "orig"
load port {clk} input -attr xrf 1376 -attr oid 1 -attr vt d -attr @path {/dot_product/dot_product:core/clk}
load port {en} input -attr xrf 1377 -attr oid 2 -attr vt d -attr @path {/dot_product/dot_product:core/en}
load port {arst_n} input -attr xrf 1378 -attr oid 3 -attr vt d -attr @path {/dot_product/dot_product:core/arst_n}
load portBus {input_a:rsc:mgc_in_wire.d(7:0)} input 8 {input_a:rsc:mgc_in_wire.d(7)} {input_a:rsc:mgc_in_wire.d(6)} {input_a:rsc:mgc_in_wire.d(5)} {input_a:rsc:mgc_in_wire.d(4)} {input_a:rsc:mgc_in_wire.d(3)} {input_a:rsc:mgc_in_wire.d(2)} {input_a:rsc:mgc_in_wire.d(1)} {input_a:rsc:mgc_in_wire.d(0)} -attr xrf 1379 -attr oid 4 -attr vt d -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
load portBus {input_b:rsc:mgc_in_wire.d(7:0)} input 8 {input_b:rsc:mgc_in_wire.d(7)} {input_b:rsc:mgc_in_wire.d(6)} {input_b:rsc:mgc_in_wire.d(5)} {input_b:rsc:mgc_in_wire.d(4)} {input_b:rsc:mgc_in_wire.d(3)} {input_b:rsc:mgc_in_wire.d(2)} {input_b:rsc:mgc_in_wire.d(1)} {input_b:rsc:mgc_in_wire.d(0)} -attr xrf 1380 -attr oid 5 -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
load portBus {output:rsc:mgc_out_stdreg.d(7:0)} output 8 {output:rsc:mgc_out_stdreg.d(7)} {output:rsc:mgc_out_stdreg.d(6)} {output:rsc:mgc_out_stdreg.d(5)} {output:rsc:mgc_out_stdreg.d(4)} {output:rsc:mgc_out_stdreg.d(3)} {output:rsc:mgc_out_stdreg.d(2)} {output:rsc:mgc_out_stdreg.d(1)} {output:rsc:mgc_out_stdreg.d(0)} -attr xrf 1381 -attr oid 6 -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load symbol "mux(2,8)" "INTERFACE" MUX boxcolor 0 \
portBus {A0(7:0)} input 8 {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
portBus {A1(7:0)} input 8 {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
portBus {S(0:0)} input.top 1 {S(0)} \
portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
load symbol "reg(8,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
portBus {D(7:0)} input 8 {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
portBus {DRa(7:0)} input 8 {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
port {clk} input.clk \
portBus {en(0:0)} input 1 {en(0)} \
portBus {Ra(0:0)} input 1 {Ra(0)} \
portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
load symbol "reg(3,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
portBus {D(2:0)} input 3 {D(2)} {D(1)} {D(0)} \
portBus {DRa(2:0)} input 3 {DRa(2)} {DRa(1)} {DRa(0)} \
port {clk} input.clk \
portBus {en(0:0)} input 1 {en(0)} \
portBus {Ra(0:0)} input 1 {Ra(0)} \
portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
portBus {A(0:0)} input 1 {A(0)} \
portBus {Z(0:0)} output 1 {Z(0)} \
load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
portBus {D(0:0)} input 1 {D(0)} \
portBus {DRa(0:0)} input 1 {DRa(0)} \
port {clk} input.clk \
portBus {en(0:0)} input 1 {en(0)} \
portBus {Ra(0:0)} input 1 {Ra(0)} \
portBus {Z(0:0)} output 1 {Z(0)} \
load symbol "and(2,8)" "INTERFACE" AND boxcolor 0 \
portBus {A0(7:0)} input 8 {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
portBus {A1(7:0)} input 8 {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
load symbol "mul(8,-1,8,-1,8)" "INTERFACE" RTL(*) boxcolor 0 \
portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
load symbol "add(8,-1,8,-1,8)" "INTERFACE" RTL(+) boxcolor 0 \
portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
load symbol "and(2,3)" "INTERFACE" AND boxcolor 0 \
portBus {A0(2:0)} input 3 {A0(2)} {A0(1)} {A0(0)} \
portBus {A1(2:0)} input 3 {A1(2)} {A1(1)} {A1(0)} \
portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
load symbol "add(3,-1,1,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
portBus {B(0:0)} input 1 {B(0)} \
portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
load symbol "add(3,-1,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
portBus {B(1:0)} input 2 {B(1)} {B(0)} \
portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
load net {acc.sva#1(0)} -attr vt d
load net {acc.sva#1(1)} -attr vt d
load net {acc.sva#1(2)} -attr vt d
load net {acc.sva#1(3)} -attr vt d
load net {acc.sva#1(4)} -attr vt d
load net {acc.sva#1(5)} -attr vt d
load net {acc.sva#1(6)} -attr vt d
load net {acc.sva#1(7)} -attr vt d
load netBundle {acc.sva#1} 8 {acc.sva#1(0)} {acc.sva#1(1)} {acc.sva#1(2)} {acc.sva#1(3)} {acc.sva#1(4)} {acc.sva#1(5)} {acc.sva#1(6)} {acc.sva#1(7)} -attr xrf 1382 -attr oid 7 -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {i#1.sva#1(0)} -attr vt d
load net {i#1.sva#1(1)} -attr vt d
load net {i#1.sva#1(2)} -attr vt d
load netBundle {i#1.sva#1} 3 {i#1.sva#1(0)} {i#1.sva#1(1)} {i#1.sva#1(2)} -attr xrf 1383 -attr oid 8 -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
load net {acc.sva#2(0)} -attr vt d
load net {acc.sva#2(1)} -attr vt d
load net {acc.sva#2(2)} -attr vt d
load net {acc.sva#2(3)} -attr vt d
load net {acc.sva#2(4)} -attr vt d
load net {acc.sva#2(5)} -attr vt d
load net {acc.sva#2(6)} -attr vt d
load net {acc.sva#2(7)} -attr vt d
load netBundle {acc.sva#2} 8 {acc.sva#2(0)} {acc.sva#2(1)} {acc.sva#2(2)} {acc.sva#2(3)} {acc.sva#2(4)} {acc.sva#2(5)} {acc.sva#2(6)} {acc.sva#2(7)} -attr xrf 1384 -attr oid 9 -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {i#1.sva#2(0)} -attr vt d
load net {i#1.sva#2(1)} -attr vt d
load net {i#1.sva#2(2)} -attr vt d
load netBundle {i#1.sva#2} 3 {i#1.sva#2(0)} {i#1.sva#2(1)} {i#1.sva#2(2)} -attr xrf 1385 -attr oid 10 -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
load net {mux.itm(0)} -attr vt d
load net {mux.itm(1)} -attr vt d
load net {mux.itm(2)} -attr vt d
load net {mux.itm(3)} -attr vt d
load net {mux.itm(4)} -attr vt d
load net {mux.itm(5)} -attr vt d
load net {mux.itm(6)} -attr vt d
load net {mux.itm(7)} -attr vt d
load netBundle {mux.itm} 8 {mux.itm(0)} {mux.itm(1)} {mux.itm(2)} {mux.itm(3)} {mux.itm(4)} {mux.itm(5)} {mux.itm(6)} {mux.itm(7)} -attr xrf 1386 -attr oid 11 -attr vt d -attr @path {/dot_product/dot_product:core/mux.itm}
load net {MAC:and.itm(0)} -attr vt d
load net {MAC:and.itm(1)} -attr vt d
load net {MAC:and.itm(2)} -attr vt d
load net {MAC:and.itm(3)} -attr vt d
load net {MAC:and.itm(4)} -attr vt d
load net {MAC:and.itm(5)} -attr vt d
load net {MAC:and.itm(6)} -attr vt d
load net {MAC:and.itm(7)} -attr vt d
load netBundle {MAC:and.itm} 8 {MAC:and.itm(0)} {MAC:and.itm(1)} {MAC:and.itm(2)} {MAC:and.itm(3)} {MAC:and.itm(4)} {MAC:and.itm(5)} {MAC:and.itm(6)} {MAC:and.itm(7)} -attr xrf 1387 -attr oid 12 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:exs.itm(0)} -attr vt d
load net {MAC:exs.itm(1)} -attr vt d
load net {MAC:exs.itm(2)} -attr vt d
load net {MAC:exs.itm(3)} -attr vt d
load net {MAC:exs.itm(4)} -attr vt d
load net {MAC:exs.itm(5)} -attr vt d
load net {MAC:exs.itm(6)} -attr vt d
load net {MAC:exs.itm(7)} -attr vt d
load netBundle {MAC:exs.itm} 8 {MAC:exs.itm(0)} {MAC:exs.itm(1)} {MAC:exs.itm(2)} {MAC:exs.itm(3)} {MAC:exs.itm(4)} {MAC:exs.itm(5)} {MAC:exs.itm(6)} {MAC:exs.itm(7)} -attr xrf 1388 -attr oid 13 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
load net {MAC:mul.itm(0)} -attr vt d
load net {MAC:mul.itm(1)} -attr vt d
load net {MAC:mul.itm(2)} -attr vt d
load net {MAC:mul.itm(3)} -attr vt d
load net {MAC:mul.itm(4)} -attr vt d
load net {MAC:mul.itm(5)} -attr vt d
load net {MAC:mul.itm(6)} -attr vt d
load net {MAC:mul.itm(7)} -attr vt d
load netBundle {MAC:mul.itm} 8 {MAC:mul.itm(0)} {MAC:mul.itm(1)} {MAC:mul.itm(2)} {MAC:mul.itm(3)} {MAC:mul.itm(4)} {MAC:mul.itm(5)} {MAC:mul.itm(6)} {MAC:mul.itm(7)} -attr xrf 1389 -attr oid 14 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:and#1.itm(0)} -attr vt d
load net {MAC:and#1.itm(1)} -attr vt d
load net {MAC:and#1.itm(2)} -attr vt d
load netBundle {MAC:and#1.itm} 3 {MAC:and#1.itm(0)} {MAC:and#1.itm(1)} {MAC:and#1.itm(2)} -attr xrf 1390 -attr oid 15 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
load net {MAC:exs#1.itm(0)} -attr vt d
load net {MAC:exs#1.itm(1)} -attr vt d
load net {MAC:exs#1.itm(2)} -attr vt d
load netBundle {MAC:exs#1.itm} 3 {MAC:exs#1.itm(0)} {MAC:exs#1.itm(1)} {MAC:exs#1.itm(2)} -attr xrf 1391 -attr oid 16 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs#1.itm}
load net {clk} -attr xrf 1392 -attr oid 17
load net {clk} -port {clk} -attr xrf 1393 -attr oid 18
load net {en} -attr xrf 1394 -attr oid 19
load net {en} -port {en} -attr xrf 1395 -attr oid 20
load net {arst_n} -attr xrf 1396 -attr oid 21
load net {arst_n} -port {arst_n} -attr xrf 1397 -attr oid 22
load net {input_a:rsc:mgc_in_wire.d(0)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(1)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(2)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(3)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(4)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(5)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(6)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(7)} -attr vt d
load netBundle {input_a:rsc:mgc_in_wire.d} 8 {input_a:rsc:mgc_in_wire.d(0)} {input_a:rsc:mgc_in_wire.d(1)} {input_a:rsc:mgc_in_wire.d(2)} {input_a:rsc:mgc_in_wire.d(3)} {input_a:rsc:mgc_in_wire.d(4)} {input_a:rsc:mgc_in_wire.d(5)} {input_a:rsc:mgc_in_wire.d(6)} {input_a:rsc:mgc_in_wire.d(7)} -attr xrf 1398 -attr oid 23 -attr vt d -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d(0)} -port {input_a:rsc:mgc_in_wire.d(0)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(1)} -port {input_a:rsc:mgc_in_wire.d(1)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(2)} -port {input_a:rsc:mgc_in_wire.d(2)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(3)} -port {input_a:rsc:mgc_in_wire.d(3)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(4)} -port {input_a:rsc:mgc_in_wire.d(4)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(5)} -port {input_a:rsc:mgc_in_wire.d(5)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(6)} -port {input_a:rsc:mgc_in_wire.d(6)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d(7)} -port {input_a:rsc:mgc_in_wire.d(7)} -attr vt d
load netBundle {input_a:rsc:mgc_in_wire.d} 8 {input_a:rsc:mgc_in_wire.d(0)} {input_a:rsc:mgc_in_wire.d(1)} {input_a:rsc:mgc_in_wire.d(2)} {input_a:rsc:mgc_in_wire.d(3)} {input_a:rsc:mgc_in_wire.d(4)} {input_a:rsc:mgc_in_wire.d(5)} {input_a:rsc:mgc_in_wire.d(6)} {input_a:rsc:mgc_in_wire.d(7)} -attr xrf 1399 -attr oid 24 -attr vt d -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d(0)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(1)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(2)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(3)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(4)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(5)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(6)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(7)} -attr vt d
load netBundle {input_b:rsc:mgc_in_wire.d} 8 {input_b:rsc:mgc_in_wire.d(0)} {input_b:rsc:mgc_in_wire.d(1)} {input_b:rsc:mgc_in_wire.d(2)} {input_b:rsc:mgc_in_wire.d(3)} {input_b:rsc:mgc_in_wire.d(4)} {input_b:rsc:mgc_in_wire.d(5)} {input_b:rsc:mgc_in_wire.d(6)} {input_b:rsc:mgc_in_wire.d(7)} -attr xrf 1400 -attr oid 25 -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d(0)} -port {input_b:rsc:mgc_in_wire.d(0)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(1)} -port {input_b:rsc:mgc_in_wire.d(1)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(2)} -port {input_b:rsc:mgc_in_wire.d(2)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(3)} -port {input_b:rsc:mgc_in_wire.d(3)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(4)} -port {input_b:rsc:mgc_in_wire.d(4)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(5)} -port {input_b:rsc:mgc_in_wire.d(5)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(6)} -port {input_b:rsc:mgc_in_wire.d(6)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d(7)} -port {input_b:rsc:mgc_in_wire.d(7)} -attr vt d
load netBundle {input_b:rsc:mgc_in_wire.d} 8 {input_b:rsc:mgc_in_wire.d(0)} {input_b:rsc:mgc_in_wire.d(1)} {input_b:rsc:mgc_in_wire.d(2)} {input_b:rsc:mgc_in_wire.d(3)} {input_b:rsc:mgc_in_wire.d(4)} {input_b:rsc:mgc_in_wire.d(5)} {input_b:rsc:mgc_in_wire.d(6)} {input_b:rsc:mgc_in_wire.d(7)} -attr xrf 1401 -attr oid 26 -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
load net {output:rsc:mgc_out_stdreg.d(0)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d(1)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d(2)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d(3)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d(4)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d(5)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d(6)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d(7)} -attr vt d
load netBundle {output:rsc:mgc_out_stdreg.d} 8 {output:rsc:mgc_out_stdreg.d(0)} {output:rsc:mgc_out_stdreg.d(1)} {output:rsc:mgc_out_stdreg.d(2)} {output:rsc:mgc_out_stdreg.d(3)} {output:rsc:mgc_out_stdreg.d(4)} {output:rsc:mgc_out_stdreg.d(5)} {output:rsc:mgc_out_stdreg.d(6)} {output:rsc:mgc_out_stdreg.d(7)} -attr xrf 1402 -attr oid 27 -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(0)} -port {output:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(1)} -port {output:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(2)} -port {output:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(3)} -port {output:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(4)} -port {output:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(5)} -port {output:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(6)} -port {output:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(7)} -port {output:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load inst "mux" "mux(2,8)" "INTERFACE" -attr xrf 1403 -attr oid 28 -attr vt dc -attr @path {/dot_product/dot_product:core/mux} -attr area 7.356384 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(8,1,2)"
load net {output:rsc:mgc_out_stdreg.d(0)} -pin "mux" {A0(0)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(1)} -pin "mux" {A0(1)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(2)} -pin "mux" {A0(2)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(3)} -pin "mux" {A0(3)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(4)} -pin "mux" {A0(4)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(5)} -pin "mux" {A0(5)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(6)} -pin "mux" {A0(6)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(7)} -pin "mux" {A0(7)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {acc.sva#2(0)} -pin "mux" {A1(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(1)} -pin "mux" {A1(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(2)} -pin "mux" {A1(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(3)} -pin "mux" {A1(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(4)} -pin "mux" {A1(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(5)} -pin "mux" {A1(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(6)} -pin "mux" {A1(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(7)} -pin "mux" {A1(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {MAC:acc.itm(2)} -pin "mux" {S(0)} -attr @path {/dot_product/dot_product:core/MAC:slc.itm}
load net {mux.itm(0)} -pin "mux" {Z(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(1)} -pin "mux" {Z(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(2)} -pin "mux" {Z(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(3)} -pin "mux" {Z(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(4)} -pin "mux" {Z(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(5)} -pin "mux" {Z(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(6)} -pin "mux" {Z(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(7)} -pin "mux" {Z(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load inst "reg(output:rsc:mgc_out_stdreg.d)" "reg(8,1,1,-1,0)" "INTERFACE" -attr xrf 1404 -attr oid 29 -attr vt dc -attr @path {/dot_product/dot_product:core/reg(output:rsc:mgc_out_stdreg.d)}
load net {mux.itm(0)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(1)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(2)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(3)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(4)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(5)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(6)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {mux.itm(7)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
load net {GND} -pin "reg(output:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(output:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(output:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(output:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(output:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(output:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(output:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(output:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {clk} -pin "reg(output:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 1405 -attr oid 30 -attr @path {/dot_product/dot_product:core/clk}
load net {en} -pin "reg(output:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/dot_product/dot_product:core/en}
load net {arst_n} -pin "reg(output:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/dot_product/dot_product:core/arst_n}
load net {output:rsc:mgc_out_stdreg.d(0)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(1)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(2)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(3)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(4)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(5)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(6)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d(7)} -pin "reg(output:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
load inst "reg(acc.sva#1)" "reg(8,1,1,-1,0)" "INTERFACE" -attr xrf 1406 -attr oid 31 -attr vt d -attr @path {/dot_product/dot_product:core/reg(acc.sva#1)}
load net {acc.sva#2(0)} -pin "reg(acc.sva#1)" {D(0)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(1)} -pin "reg(acc.sva#1)" {D(1)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(2)} -pin "reg(acc.sva#1)" {D(2)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(3)} -pin "reg(acc.sva#1)" {D(3)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(4)} -pin "reg(acc.sva#1)" {D(4)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(5)} -pin "reg(acc.sva#1)" {D(5)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(6)} -pin "reg(acc.sva#1)" {D(6)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(7)} -pin "reg(acc.sva#1)" {D(7)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {GND} -pin "reg(acc.sva#1)" {DRa(0)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(acc.sva#1)" {DRa(1)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(acc.sva#1)" {DRa(2)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(acc.sva#1)" {DRa(3)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(acc.sva#1)" {DRa(4)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(acc.sva#1)" {DRa(5)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(acc.sva#1)" {DRa(6)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {GND} -pin "reg(acc.sva#1)" {DRa(7)} -attr @path {/dot_product/dot_product:core/C0_8}
load net {clk} -pin "reg(acc.sva#1)" {clk} -attr xrf 1407 -attr oid 32 -attr @path {/dot_product/dot_product:core/clk}
load net {en} -pin "reg(acc.sva#1)" {en(0)} -attr @path {/dot_product/dot_product:core/en}
load net {arst_n} -pin "reg(acc.sva#1)" {Ra(0)} -attr @path {/dot_product/dot_product:core/arst_n}
load net {acc.sva#1(0)} -pin "reg(acc.sva#1)" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(1)} -pin "reg(acc.sva#1)" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(2)} -pin "reg(acc.sva#1)" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(3)} -pin "reg(acc.sva#1)" {Z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(4)} -pin "reg(acc.sva#1)" {Z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(5)} -pin "reg(acc.sva#1)" {Z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(6)} -pin "reg(acc.sva#1)" {Z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(7)} -pin "reg(acc.sva#1)" {Z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load inst "reg(i#1.sva#1)" "reg(3,1,1,-1,0)" "INTERFACE" -attr xrf 1408 -attr oid 33 -attr vt d -attr @path {/dot_product/dot_product:core/reg(i#1.sva#1)}
load net {i#1.sva#2(0)} -pin "reg(i#1.sva#1)" {D(0)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
load net {i#1.sva#2(1)} -pin "reg(i#1.sva#1)" {D(1)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
load net {i#1.sva#2(2)} -pin "reg(i#1.sva#1)" {D(2)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
load net {GND} -pin "reg(i#1.sva#1)" {DRa(0)} -attr @path {/dot_product/dot_product:core/C0_3}
load net {GND} -pin "reg(i#1.sva#1)" {DRa(1)} -attr @path {/dot_product/dot_product:core/C0_3}
load net {GND} -pin "reg(i#1.sva#1)" {DRa(2)} -attr @path {/dot_product/dot_product:core/C0_3}
load net {clk} -pin "reg(i#1.sva#1)" {clk} -attr xrf 1409 -attr oid 34 -attr @path {/dot_product/dot_product:core/clk}
load net {en} -pin "reg(i#1.sva#1)" {en(0)} -attr @path {/dot_product/dot_product:core/en}
load net {arst_n} -pin "reg(i#1.sva#1)" {Ra(0)} -attr @path {/dot_product/dot_product:core/arst_n}
load net {i#1.sva#1(0)} -pin "reg(i#1.sva#1)" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
load net {i#1.sva#1(1)} -pin "reg(i#1.sva#1)" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
load net {i#1.sva#1(2)} -pin "reg(i#1.sva#1)" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
load inst "MAC:not" "not(1)" "INTERFACE" -attr xrf 1410 -attr oid 35 -attr @path {/dot_product/dot_product:core/MAC:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
load net {MAC:acc.itm(2)} -pin "MAC:not" {A(0)} -attr @path {/dot_product/dot_product:core/MAC:slc#1.itm}
load net {MAC:not.itm} -pin "MAC:not" {Z(0)} -attr @path {/dot_product/dot_product:core/MAC:not.itm}
load inst "reg(exit:MAC.lpi)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 1411 -attr oid 36 -attr @path {/dot_product/dot_product:core/reg(exit:MAC.lpi)}
load net {MAC:not.itm} -pin "reg(exit:MAC.lpi)" {D(0)} -attr @path {/dot_product/dot_product:core/MAC:not.itm}
load net {PWR} -pin "reg(exit:MAC.lpi)" {DRa(0)} -attr @path {/dot_product/dot_product:core/C1_1}
load net {clk} -pin "reg(exit:MAC.lpi)" {clk} -attr xrf 1412 -attr oid 37 -attr @path {/dot_product/dot_product:core/clk}
load net {en} -pin "reg(exit:MAC.lpi)" {en(0)} -attr @path {/dot_product/dot_product:core/en}
load net {arst_n} -pin "reg(exit:MAC.lpi)" {Ra(0)} -attr @path {/dot_product/dot_product:core/arst_n}
load net {exit:MAC.lpi} -pin "reg(exit:MAC.lpi)" {Z(0)} -attr @path {/dot_product/dot_product:core/exit:MAC.lpi}
load inst "MAC:not#3" "not(1)" "INTERFACE" -attr xrf 1413 -attr oid 38 -attr @path {/dot_product/dot_product:core/MAC:not#3} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
load net {exit:MAC.lpi} -pin "MAC:not#3" {A(0)} -attr @path {/dot_product/dot_product:core/exit:MAC.lpi}
load net {MAC:not#3.itm} -pin "MAC:not#3" {Z(0)} -attr @path {/dot_product/dot_product:core/MAC:not#3.itm}
load inst "MAC:and" "and(2,8)" "INTERFACE" -attr xrf 1414 -attr oid 39 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and} -attr area 5.838659 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(8,2)"
load net {acc.sva#1(0)} -pin "MAC:and" {A0(0)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(1)} -pin "MAC:and" {A0(1)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(2)} -pin "MAC:and" {A0(2)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(3)} -pin "MAC:and" {A0(3)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(4)} -pin "MAC:and" {A0(4)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(5)} -pin "MAC:and" {A0(5)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(6)} -pin "MAC:and" {A0(6)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {acc.sva#1(7)} -pin "MAC:and" {A0(7)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
load net {MAC:not#3.itm} -pin "MAC:and" {A1(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
load net {MAC:not#3.itm} -pin "MAC:and" {A1(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
load net {MAC:not#3.itm} -pin "MAC:and" {A1(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
load net {MAC:not#3.itm} -pin "MAC:and" {A1(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
load net {MAC:not#3.itm} -pin "MAC:and" {A1(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
load net {MAC:not#3.itm} -pin "MAC:and" {A1(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
load net {MAC:not#3.itm} -pin "MAC:and" {A1(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
load net {MAC:not#3.itm} -pin "MAC:and" {A1(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
load net {MAC:and.itm(0)} -pin "MAC:and" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(1)} -pin "MAC:and" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(2)} -pin "MAC:and" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(3)} -pin "MAC:and" {Z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(4)} -pin "MAC:and" {Z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(5)} -pin "MAC:and" {Z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(6)} -pin "MAC:and" {Z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(7)} -pin "MAC:and" {Z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load inst "MAC:mul" "mul(8,-1,8,-1,8)" "INTERFACE" -attr xrf 1415 -attr oid 40 -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8)"
load net {input_a:rsc:mgc_in_wire.d(0)} -pin "MAC:mul" {A(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d(1)} -pin "MAC:mul" {A(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d(2)} -pin "MAC:mul" {A(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d(3)} -pin "MAC:mul" {A(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d(4)} -pin "MAC:mul" {A(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d(5)} -pin "MAC:mul" {A(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d(6)} -pin "MAC:mul" {A(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d(7)} -pin "MAC:mul" {A(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d(0)} -pin "MAC:mul" {B(0)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d(1)} -pin "MAC:mul" {B(1)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d(2)} -pin "MAC:mul" {B(2)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d(3)} -pin "MAC:mul" {B(3)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d(4)} -pin "MAC:mul" {B(4)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d(5)} -pin "MAC:mul" {B(5)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d(6)} -pin "MAC:mul" {B(6)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d(7)} -pin "MAC:mul" {B(7)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
load net {MAC:mul.itm(0)} -pin "MAC:mul" {Z(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(1)} -pin "MAC:mul" {Z(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(2)} -pin "MAC:mul" {Z(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(3)} -pin "MAC:mul" {Z(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(4)} -pin "MAC:mul" {Z(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(5)} -pin "MAC:mul" {Z(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(6)} -pin "MAC:mul" {Z(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(7)} -pin "MAC:mul" {Z(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load inst "MAC:acc#3" "add(8,-1,8,-1,8)" "INTERFACE" -attr xrf 1416 -attr oid 41 -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:acc#3} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8)"
load net {MAC:and.itm(0)} -pin "MAC:acc#3" {A(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(1)} -pin "MAC:acc#3" {A(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(2)} -pin "MAC:acc#3" {A(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(3)} -pin "MAC:acc#3" {A(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(4)} -pin "MAC:acc#3" {A(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(5)} -pin "MAC:acc#3" {A(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(6)} -pin "MAC:acc#3" {A(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:and.itm(7)} -pin "MAC:acc#3" {A(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
load net {MAC:mul.itm(0)} -pin "MAC:acc#3" {B(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(1)} -pin "MAC:acc#3" {B(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(2)} -pin "MAC:acc#3" {B(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(3)} -pin "MAC:acc#3" {B(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(4)} -pin "MAC:acc#3" {B(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(5)} -pin "MAC:acc#3" {B(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(6)} -pin "MAC:acc#3" {B(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {MAC:mul.itm(7)} -pin "MAC:acc#3" {B(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
load net {acc.sva#2(0)} -pin "MAC:acc#3" {Z(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(1)} -pin "MAC:acc#3" {Z(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(2)} -pin "MAC:acc#3" {Z(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(3)} -pin "MAC:acc#3" {Z(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(4)} -pin "MAC:acc#3" {Z(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(5)} -pin "MAC:acc#3" {Z(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(6)} -pin "MAC:acc#3" {Z(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load net {acc.sva#2(7)} -pin "MAC:acc#3" {Z(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
load inst "MAC:not#5" "not(1)" "INTERFACE" -attr xrf 1417 -attr oid 42 -attr @path {/dot_product/dot_product:core/MAC:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
load net {exit:MAC.lpi} -pin "MAC:not#5" {A(0)} -attr @path {/dot_product/dot_product:core/exit:MAC.lpi}
load net {MAC:not#5.itm} -pin "MAC:not#5" {Z(0)} -attr @path {/dot_product/dot_product:core/MAC:not#5.itm}
load inst "MAC:and#1" "and(2,3)" "INTERFACE" -attr xrf 1418 -attr oid 43 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1} -attr area 2.189497 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(3,2)"
load net {i#1.sva#1(0)} -pin "MAC:and#1" {A0(0)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
load net {i#1.sva#1(1)} -pin "MAC:and#1" {A0(1)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
load net {i#1.sva#1(2)} -pin "MAC:and#1" {A0(2)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
load net {MAC:not#5.itm} -pin "MAC:and#1" {A1(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs#1.itm}
load net {MAC:not#5.itm} -pin "MAC:and#1" {A1(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs#1.itm}
load net {MAC:not#5.itm} -pin "MAC:and#1" {A1(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs#1.itm}
load net {MAC:and#1.itm(0)} -pin "MAC:and#1" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
load net {MAC:and#1.itm(1)} -pin "MAC:and#1" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
load net {MAC:and#1.itm(2)} -pin "MAC:and#1" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
load inst "MAC:acc#4" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 1419 -attr oid 44 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#4} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,1,3)"
load net {MAC:and#1.itm(0)} -pin "MAC:acc#4" {A(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
load net {MAC:and#1.itm(1)} -pin "MAC:acc#4" {A(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
load net {MAC:and#1.itm(2)} -pin "MAC:acc#4" {A(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
load net {PWR} -pin "MAC:acc#4" {B(0)} -attr @path {/dot_product/dot_product:core/C1_1#1}
load net {i#1.sva#2(0)} -pin "MAC:acc#4" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
load net {i#1.sva#2(1)} -pin "MAC:acc#4" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
load net {i#1.sva#2(2)} -pin "MAC:acc#4" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
load inst "MAC:acc" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 1420 -attr oid 45 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc} -attr area 4.306828 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,0,3)"
load net {i#1.sva#2(0)} -pin "MAC:acc" {A(0)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
load net {i#1.sva#2(1)} -pin "MAC:acc" {A(1)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
load net {i#1.sva#2(2)} -pin "MAC:acc" {A(2)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
load net {PWR} -pin "MAC:acc" {B(0)} -attr @path {/dot_product/dot_product:core/C3_2}
load net {PWR} -pin "MAC:acc" {B(1)} -attr @path {/dot_product/dot_product:core/C3_2}
load net {MAC:acc.itm(0)} -pin "MAC:acc" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
load net {MAC:acc.itm(1)} -pin "MAC:acc" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
load net {MAC:acc.itm(2)} -pin "MAC:acc" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
### END MODULE
module new "dot_product" "orig"
load portBus {input_a:rsc.z(7:0)} input 8 {input_a:rsc.z(7)} {input_a:rsc.z(6)} {input_a:rsc.z(5)} {input_a:rsc.z(4)} {input_a:rsc.z(3)} {input_a:rsc.z(2)} {input_a:rsc.z(1)} {input_a:rsc.z(0)} -attr xrf 1421 -attr oid 46 -attr vt d -attr @path {/dot_product/input_a:rsc.z}
load portBus {input_b:rsc.z(7:0)} input 8 {input_b:rsc.z(7)} {input_b:rsc.z(6)} {input_b:rsc.z(5)} {input_b:rsc.z(4)} {input_b:rsc.z(3)} {input_b:rsc.z(2)} {input_b:rsc.z(1)} {input_b:rsc.z(0)} -attr xrf 1422 -attr oid 47 -attr vt d -attr @path {/dot_product/input_b:rsc.z}
load portBus {output:rsc.z(7:0)} output 8 {output:rsc.z(7)} {output:rsc.z(6)} {output:rsc.z(5)} {output:rsc.z(4)} {output:rsc.z(3)} {output:rsc.z(2)} {output:rsc.z(1)} {output:rsc.z(0)} -attr xrf 1423 -attr oid 48 -attr vt d -attr @path {/dot_product/output:rsc.z}
load port {clk} input -attr xrf 1424 -attr oid 49 -attr vt d -attr @path {/dot_product/clk}
load port {en} input -attr xrf 1425 -attr oid 50 -attr vt d -attr @path {/dot_product/en}
load port {arst_n} input -attr xrf 1426 -attr oid 51 -attr vt d -attr @path {/dot_product/arst_n}
load symbol "mgc_ioport.mgc_in_wire(1,8)" "INTERFACE" GEN boxcolor 0 \
portBus {d(7:0)} output 8 {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
portBus {z(7:0)} input 8 {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
load symbol "mgc_ioport.mgc_in_wire(2,8)" "INTERFACE" GEN boxcolor 0 \
portBus {d(7:0)} output 8 {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
portBus {z(7:0)} input 8 {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
load symbol "mgc_ioport.mgc_out_stdreg(3,8)" "INTERFACE" GEN boxcolor 0 \
portBus {d(7:0)} input 8 {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
portBus {z(7:0)} output 8 {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
load symbol "dot_product:core" "orig" GEN \
port {clk#1} input \
port {en#1} input \
port {arst_n#1} input \
portBus {input_a:rsc:mgc_in_wire.d(7:0)} input 8 {input_a:rsc:mgc_in_wire.d(7)} {input_a:rsc:mgc_in_wire.d(6)} {input_a:rsc:mgc_in_wire.d(5)} {input_a:rsc:mgc_in_wire.d(4)} {input_a:rsc:mgc_in_wire.d(3)} {input_a:rsc:mgc_in_wire.d(2)} {input_a:rsc:mgc_in_wire.d(1)} {input_a:rsc:mgc_in_wire.d(0)} \
portBus {input_b:rsc:mgc_in_wire.d(7:0)} input 8 {input_b:rsc:mgc_in_wire.d(7)} {input_b:rsc:mgc_in_wire.d(6)} {input_b:rsc:mgc_in_wire.d(5)} {input_b:rsc:mgc_in_wire.d(4)} {input_b:rsc:mgc_in_wire.d(3)} {input_b:rsc:mgc_in_wire.d(2)} {input_b:rsc:mgc_in_wire.d(1)} {input_b:rsc:mgc_in_wire.d(0)} \
portBus {output:rsc:mgc_out_stdreg.d(7:0)} output 8 {output:rsc:mgc_out_stdreg.d(7)} {output:rsc:mgc_out_stdreg.d(6)} {output:rsc:mgc_out_stdreg.d(5)} {output:rsc:mgc_out_stdreg.d(4)} {output:rsc:mgc_out_stdreg.d(3)} {output:rsc:mgc_out_stdreg.d(2)} {output:rsc:mgc_out_stdreg.d(1)} {output:rsc:mgc_out_stdreg.d(0)} \
load net {input_a:rsc:mgc_in_wire.d#1(0)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d#1(1)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d#1(2)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d#1(3)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d#1(4)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d#1(5)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d#1(6)} -attr vt d
load net {input_a:rsc:mgc_in_wire.d#1(7)} -attr vt d
load netBundle {input_a:rsc:mgc_in_wire.d#1} 8 {input_a:rsc:mgc_in_wire.d#1(0)} {input_a:rsc:mgc_in_wire.d#1(1)} {input_a:rsc:mgc_in_wire.d#1(2)} {input_a:rsc:mgc_in_wire.d#1(3)} {input_a:rsc:mgc_in_wire.d#1(4)} {input_a:rsc:mgc_in_wire.d#1(5)} {input_a:rsc:mgc_in_wire.d#1(6)} {input_a:rsc:mgc_in_wire.d#1(7)} -attr xrf 1427 -attr oid 52 -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(0)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d#1(1)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d#1(2)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d#1(3)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d#1(4)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d#1(5)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d#1(6)} -attr vt d
load net {input_b:rsc:mgc_in_wire.d#1(7)} -attr vt d
load netBundle {input_b:rsc:mgc_in_wire.d#1} 8 {input_b:rsc:mgc_in_wire.d#1(0)} {input_b:rsc:mgc_in_wire.d#1(1)} {input_b:rsc:mgc_in_wire.d#1(2)} {input_b:rsc:mgc_in_wire.d#1(3)} {input_b:rsc:mgc_in_wire.d#1(4)} {input_b:rsc:mgc_in_wire.d#1(5)} {input_b:rsc:mgc_in_wire.d#1(6)} {input_b:rsc:mgc_in_wire.d#1(7)} -attr xrf 1428 -attr oid 53 -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {output:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
load net {output:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
load netBundle {output:rsc:mgc_out_stdreg.d#1} 8 {output:rsc:mgc_out_stdreg.d#1(0)} {output:rsc:mgc_out_stdreg.d#1(1)} {output:rsc:mgc_out_stdreg.d#1(2)} {output:rsc:mgc_out_stdreg.d#1(3)} {output:rsc:mgc_out_stdreg.d#1(4)} {output:rsc:mgc_out_stdreg.d#1(5)} {output:rsc:mgc_out_stdreg.d#1(6)} {output:rsc:mgc_out_stdreg.d#1(7)} -attr xrf 1429 -attr oid 54 -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {input_a:rsc.z(0)} -attr vt d
load net {input_a:rsc.z(1)} -attr vt d
load net {input_a:rsc.z(2)} -attr vt d
load net {input_a:rsc.z(3)} -attr vt d
load net {input_a:rsc.z(4)} -attr vt d
load net {input_a:rsc.z(5)} -attr vt d
load net {input_a:rsc.z(6)} -attr vt d
load net {input_a:rsc.z(7)} -attr vt d
load netBundle {input_a:rsc.z} 8 {input_a:rsc.z(0)} {input_a:rsc.z(1)} {input_a:rsc.z(2)} {input_a:rsc.z(3)} {input_a:rsc.z(4)} {input_a:rsc.z(5)} {input_a:rsc.z(6)} {input_a:rsc.z(7)} -attr xrf 1430 -attr oid 55 -attr vt d -attr @path {/dot_product/input_a:rsc.z}
load net {input_a:rsc.z(0)} -port {input_a:rsc.z(0)} -attr vt d
load net {input_a:rsc.z(1)} -port {input_a:rsc.z(1)} -attr vt d
load net {input_a:rsc.z(2)} -port {input_a:rsc.z(2)} -attr vt d
load net {input_a:rsc.z(3)} -port {input_a:rsc.z(3)} -attr vt d
load net {input_a:rsc.z(4)} -port {input_a:rsc.z(4)} -attr vt d
load net {input_a:rsc.z(5)} -port {input_a:rsc.z(5)} -attr vt d
load net {input_a:rsc.z(6)} -port {input_a:rsc.z(6)} -attr vt d
load net {input_a:rsc.z(7)} -port {input_a:rsc.z(7)} -attr vt d
load netBundle {input_a:rsc.z} 8 {input_a:rsc.z(0)} {input_a:rsc.z(1)} {input_a:rsc.z(2)} {input_a:rsc.z(3)} {input_a:rsc.z(4)} {input_a:rsc.z(5)} {input_a:rsc.z(6)} {input_a:rsc.z(7)} -attr xrf 1431 -attr oid 56 -attr vt d -attr @path {/dot_product/input_a:rsc.z}
load net {input_b:rsc.z(0)} -attr vt d
load net {input_b:rsc.z(1)} -attr vt d
load net {input_b:rsc.z(2)} -attr vt d
load net {input_b:rsc.z(3)} -attr vt d
load net {input_b:rsc.z(4)} -attr vt d
load net {input_b:rsc.z(5)} -attr vt d
load net {input_b:rsc.z(6)} -attr vt d
load net {input_b:rsc.z(7)} -attr vt d
load netBundle {input_b:rsc.z} 8 {input_b:rsc.z(0)} {input_b:rsc.z(1)} {input_b:rsc.z(2)} {input_b:rsc.z(3)} {input_b:rsc.z(4)} {input_b:rsc.z(5)} {input_b:rsc.z(6)} {input_b:rsc.z(7)} -attr xrf 1432 -attr oid 57 -attr vt d -attr @path {/dot_product/input_b:rsc.z}
load net {input_b:rsc.z(0)} -port {input_b:rsc.z(0)} -attr vt d
load net {input_b:rsc.z(1)} -port {input_b:rsc.z(1)} -attr vt d
load net {input_b:rsc.z(2)} -port {input_b:rsc.z(2)} -attr vt d
load net {input_b:rsc.z(3)} -port {input_b:rsc.z(3)} -attr vt d
load net {input_b:rsc.z(4)} -port {input_b:rsc.z(4)} -attr vt d
load net {input_b:rsc.z(5)} -port {input_b:rsc.z(5)} -attr vt d
load net {input_b:rsc.z(6)} -port {input_b:rsc.z(6)} -attr vt d
load net {input_b:rsc.z(7)} -port {input_b:rsc.z(7)} -attr vt d
load netBundle {input_b:rsc.z} 8 {input_b:rsc.z(0)} {input_b:rsc.z(1)} {input_b:rsc.z(2)} {input_b:rsc.z(3)} {input_b:rsc.z(4)} {input_b:rsc.z(5)} {input_b:rsc.z(6)} {input_b:rsc.z(7)} -attr xrf 1433 -attr oid 58 -attr vt d -attr @path {/dot_product/input_b:rsc.z}
load net {output:rsc.z(0)} -attr vt d
load net {output:rsc.z(1)} -attr vt d
load net {output:rsc.z(2)} -attr vt d
load net {output:rsc.z(3)} -attr vt d
load net {output:rsc.z(4)} -attr vt d
load net {output:rsc.z(5)} -attr vt d
load net {output:rsc.z(6)} -attr vt d
load net {output:rsc.z(7)} -attr vt d
load netBundle {output:rsc.z} 8 {output:rsc.z(0)} {output:rsc.z(1)} {output:rsc.z(2)} {output:rsc.z(3)} {output:rsc.z(4)} {output:rsc.z(5)} {output:rsc.z(6)} {output:rsc.z(7)} -attr xrf 1434 -attr oid 59 -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(0)} -port {output:rsc.z(0)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(1)} -port {output:rsc.z(1)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(2)} -port {output:rsc.z(2)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(3)} -port {output:rsc.z(3)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(4)} -port {output:rsc.z(4)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(5)} -port {output:rsc.z(5)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(6)} -port {output:rsc.z(6)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(7)} -port {output:rsc.z(7)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {clk} -attr xrf 1435 -attr oid 60
load net {clk} -port {clk} -attr xrf 1436 -attr oid 61
load net {en} -attr xrf 1437 -attr oid 62
load net {en} -port {en} -attr xrf 1438 -attr oid 63
load net {arst_n} -attr xrf 1439 -attr oid 64
load net {arst_n} -port {arst_n} -attr xrf 1440 -attr oid 65
load inst "dot_product:core:inst" "dot_product:core" "orig" -attr xrf 1441 -attr oid 66 -attr vt dc -attr @path {/dot_product/dot_product:core:inst} -attr area 363.202905 -attr delay 2.160303 -attr hier "/dot_product/dot_product:core" -pg 1 -lvl 3
load net {clk} -pin "dot_product:core:inst" {clk#1} -attr xrf 1442 -attr oid 67 -attr @path {/dot_product/clk}
load net {en} -pin "dot_product:core:inst" {en#1} -attr xrf 1443 -attr oid 68 -attr @path {/dot_product/en}
load net {arst_n} -pin "dot_product:core:inst" {arst_n#1} -attr xrf 1444 -attr oid 69 -attr @path {/dot_product/arst_n}
load net {input_a:rsc:mgc_in_wire.d#1(0)} -pin "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(1)} -pin "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(2)} -pin "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(3)} -pin "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(4)} -pin "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(5)} -pin "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(6)} -pin "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(7)} -pin "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(0)} -pin "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(1)} -pin "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(2)} -pin "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(3)} -pin "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(4)} -pin "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(5)} -pin "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(6)} -pin "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(7)} -pin "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {output:rsc:mgc_out_stdreg.d#1(0)} -pin "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(1)} -pin "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(2)} -pin "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(3)} -pin "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(4)} -pin "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(5)} -pin "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(6)} -pin "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(7)} -pin "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load inst "input_a:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,8)" "INTERFACE" -attr xrf 1445 -attr oid 70 -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,8)" -pg 1 -lvl 1
load net {input_a:rsc:mgc_in_wire.d#1(0)} -pin "input_a:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(1)} -pin "input_a:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(2)} -pin "input_a:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(3)} -pin "input_a:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(4)} -pin "input_a:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(5)} -pin "input_a:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(6)} -pin "input_a:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc:mgc_in_wire.d#1(7)} -pin "input_a:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
load net {input_a:rsc.z(0)} -pin "input_a:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
load net {input_a:rsc.z(1)} -pin "input_a:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
load net {input_a:rsc.z(2)} -pin "input_a:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
load net {input_a:rsc.z(3)} -pin "input_a:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
load net {input_a:rsc.z(4)} -pin "input_a:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
load net {input_a:rsc.z(5)} -pin "input_a:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
load net {input_a:rsc.z(6)} -pin "input_a:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
load net {input_a:rsc.z(7)} -pin "input_a:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
load inst "input_b:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(2,8)" "INTERFACE" -attr xrf 1446 -attr oid 71 -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(2,8)" -pg 1 -lvl 1
load net {input_b:rsc:mgc_in_wire.d#1(0)} -pin "input_b:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(1)} -pin "input_b:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(2)} -pin "input_b:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(3)} -pin "input_b:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(4)} -pin "input_b:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(5)} -pin "input_b:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(6)} -pin "input_b:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc:mgc_in_wire.d#1(7)} -pin "input_b:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
load net {input_b:rsc.z(0)} -pin "input_b:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
load net {input_b:rsc.z(1)} -pin "input_b:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
load net {input_b:rsc.z(2)} -pin "input_b:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
load net {input_b:rsc.z(3)} -pin "input_b:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
load net {input_b:rsc.z(4)} -pin "input_b:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
load net {input_b:rsc.z(5)} -pin "input_b:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
load net {input_b:rsc.z(6)} -pin "input_b:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
load net {input_b:rsc.z(7)} -pin "input_b:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
load inst "output:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(3,8)" "INTERFACE" -attr xrf 1447 -attr oid 72 -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(3,8)" -pg 1 -lvl 1002
load net {output:rsc:mgc_out_stdreg.d#1(0)} -pin "output:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(1)} -pin "output:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(2)} -pin "output:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(3)} -pin "output:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(4)} -pin "output:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(5)} -pin "output:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(6)} -pin "output:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc:mgc_out_stdreg.d#1(7)} -pin "output:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
load net {output:rsc.z(0)} -pin "output:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(1)} -pin "output:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(2)} -pin "output:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(3)} -pin "output:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(4)} -pin "output:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(5)} -pin "output:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(6)} -pin "output:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/dot_product/output:rsc.z}
load net {output:rsc.z(7)} -pin "output:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/dot_product/output:rsc.z}
### END MODULE
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