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set a(0-99) {NAME MAC:asn TYPE ASSIGN PAR 0-98 XREFS 441 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-134 {}}} SUCCS {{259 0 0-100 {}} {256 0 0-134 {}}} CYCLES {}}
set a(0-100) {NAME MAC:select TYPE SELECT PAR 0-98 XREFS 442 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{259 0 0-99 {}}} SUCCS {} CYCLES {}}
set a(0-101) {NAME MAC:asn#4 TYPE ASSIGN PAR 0-98 XREFS 443 LOC {0 1.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6507022499999999} PREDS {{262 0 0-134 {}}} SUCCS {{259 0 0-102 {}} {256 0 0-134 {}}} CYCLES {}}
set a(0-102) {NAME MAC:not#2 TYPE NOT PAR 0-98 XREFS 444 LOC {1 0.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6507022499999999} PREDS {{259 0 0-101 {}}} SUCCS {{259 0 0-103 {}}} CYCLES {}}
set a(0-103) {NAME MAC:exs#1 TYPE SIGNEXTEND PAR 0-98 XREFS 445 LOC {1 0.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6507022499999999} PREDS {{259 0 0-102 {}}} SUCCS {{259 0 0-104 {}}} CYCLES {}}
set a(0-104) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(3,2) AREA_SCORE 2.19 QUANTITY 1 NAME MAC:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-98 XREFS 446 LOC {1 0.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6671089812638539 1 0.6671089812638539} PREDS {{262 0 0-133 {}} {259 0 0-103 {}}} SUCCS {{258 0 0-116 {}} {258 0 0-122 {}} {258 0 0-125 {}} {256 0 0-133 {}}} CYCLES {}}
set a(0-105) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-98 XREFS 447 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{80 0 0-106 {}}} SUCCS {{80 0 0-106 {}} {258 0 0-111 {}} {258 0 0-112 {}} {258 0 0-113 {}} {258 0 0-114 {}} {258 0 0-115 {}}} CYCLES {}}
set a(0-106) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-98 XREFS 448 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{80 0 0-105 {}}} SUCCS {{80 0 0-105 {}} {258 0 0-117 {}} {258 0 0-118 {}} {258 0 0-119 {}} {258 0 0-120 {}} {258 0 0-121 {}}} CYCLES {}}
set a(0-107) {NAME MAC:asn#5 TYPE ASSIGN PAR 0-98 XREFS 449 LOC {0 1.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{262 0 0-134 {}}} SUCCS {{259 0 0-108 {}} {256 0 0-134 {}}} CYCLES {}}
set a(0-108) {NAME MAC:not#1 TYPE NOT PAR 0-98 XREFS 450 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{259 0 0-107 {}}} SUCCS {{259 0 0-109 {}}} CYCLES {}}
set a(0-109) {NAME MAC:exs TYPE SIGNEXTEND PAR 0-98 XREFS 451 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{259 0 0-108 {}}} SUCCS {{259 0 0-110 {}}} CYCLES {}}
set a(0-110) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(8,2) AREA_SCORE 5.84 QUANTITY 1 NAME MAC:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-98 XREFS 452 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.9273052062638539 1 0.9273052062638539} PREDS {{262 0 0-132 {}} {259 0 0-109 {}}} SUCCS {{258 0 0-124 {}} {256 0 0-132 {}}} CYCLES {}}
set a(0-111) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt) TYPE READSLICE PAR 0-98 XREFS 453 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-105 {}}} SUCCS {{258 0 0-116 {}}} CYCLES {}}
set a(0-112) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#1 TYPE READSLICE PAR 0-98 XREFS 454 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-105 {}}} SUCCS {{258 0 0-116 {}}} CYCLES {}}
set a(0-113) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#2 TYPE READSLICE PAR 0-98 XREFS 455 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-105 {}}} SUCCS {{258 0 0-116 {}}} CYCLES {}}
set a(0-114) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#3 TYPE READSLICE PAR 0-98 XREFS 456 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-105 {}}} SUCCS {{258 0 0-116 {}}} CYCLES {}}
set a(0-115) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#4 TYPE READSLICE PAR 0-98 XREFS 457 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-105 {}}} SUCCS {{259 0 0-116 {}}} CYCLES {}}
set a(0-116) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(8,3,8) AREA_SCORE 38.71 QUANTITY 2 NAME MAC:mux TYPE MUX DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-98 XREFS 458 LOC {1 0.016406775 1 0.667109025 1 0.667109025 1 0.7611039625 1 0.7611039625} PREDS {{258 0 0-104 {}} {258 0 0-114 {}} {258 0 0-113 {}} {258 0 0-112 {}} {258 0 0-111 {}} {259 0 0-115 {}}} SUCCS {{258 0 0-123 {}}} CYCLES {}}
set a(0-117) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt) TYPE READSLICE PAR 0-98 XREFS 459 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-106 {}}} SUCCS {{258 0 0-122 {}}} CYCLES {}}
set a(0-118) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#1 TYPE READSLICE PAR 0-98 XREFS 460 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-106 {}}} SUCCS {{258 0 0-122 {}}} CYCLES {}}
set a(0-119) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#2 TYPE READSLICE PAR 0-98 XREFS 461 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-106 {}}} SUCCS {{258 0 0-122 {}}} CYCLES {}}
set a(0-120) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#3 TYPE READSLICE PAR 0-98 XREFS 462 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-106 {}}} SUCCS {{258 0 0-122 {}}} CYCLES {}}
set a(0-121) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#4 TYPE READSLICE PAR 0-98 XREFS 463 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-106 {}}} SUCCS {{259 0 0-122 {}}} CYCLES {}}
set a(0-122) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(8,3,8) AREA_SCORE 38.71 QUANTITY 2 NAME MAC:mux#3 TYPE MUX DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-98 XREFS 464 LOC {1 0.016406775 1 0.667109025 1 0.667109025 1 0.7611039625 1 0.7611039625} PREDS {{258 0 0-104 {}} {258 0 0-120 {}} {258 0 0-119 {}} {258 0 0-118 {}} {258 0 0-117 {}} {259 0 0-121 {}}} SUCCS {{259 0 0-123 {}}} CYCLES {}}
set a(0-123) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-98 XREFS 465 LOC {1 0.110401775 1 0.761104025 1 0.761104025 1 0.9273051907433434 1 0.9273051907433434} PREDS {{258 0 0-116 {}} {259 0 0-122 {}}} SUCCS {{259 0 0-124 {}}} CYCLES {}}
set a(0-124) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME MAC:acc#3 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-98 XREFS 466 LOC {1 0.276603 1 0.92730525 1 0.92730525 1 0.9999999527684257 1 0.9999999527684257} PREDS {{258 0 0-110 {}} {259 0 0-123 {}}} SUCCS {{258 0 0-131 {}} {258 0 0-132 {}}} CYCLES {}}
set a(0-125) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,2,1,3) AREA_SCORE 4.00 QUANTITY 1 NAME MAC:acc#4 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-98 XREFS 467 LOC {1 0.016406775 1 0.898700525 1 0.898700525 1 0.9464762270241717 1 0.9464762270241717} PREDS {{258 0 0-104 {}}} SUCCS {{259 0 0-126 {}} {258 0 0-133 {}}} CYCLES {}}
set a(0-126) {NAME MAC:asn#3 TYPE ASSIGN PAR 0-98 XREFS 468 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 1 0.946476275} PREDS {{259 0 0-125 {}}} SUCCS {{259 0 0-127 {}}} CYCLES {}}
set a(0-127) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,4) AREA_SCORE 5.30 QUANTITY 1 NAME MAC:acc TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-98 XREFS 469 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 1 0.9999999399089293 1 0.9999999399089293} PREDS {{259 0 0-126 {}}} SUCCS {{259 0 0-128 {}}} CYCLES {}}
set a(0-128) {NAME MAC:slc TYPE READSLICE PAR 0-98 XREFS 470 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-127 {}}} SUCCS {{259 0 0-129 {}}} CYCLES {}}
set a(0-129) {NAME MAC:not TYPE NOT PAR 0-98 XREFS 471 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-128 {}}} SUCCS {{259 0 0-130 {}} {258 0 0-134 {}}} CYCLES {}}
set a(0-130) {NAME MAC:select#1 TYPE SELECT PAR 0-98 XREFS 472 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-129 {}}} SUCCS {{131 0 0-131 {}}} CYCLES {}}
set a(0-131) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(3,8) AREA_SCORE 0.00 QUANTITY 1 NAME io_write(output:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-98 XREFS 473 LOC {1 1.0 1 1.0 1 1.0 2 0.0 1 0.9999} PREDS {{260 0 0-131 {}} {258 0 0-124 {}} {131 0 0-130 {}}} SUCCS {{260 0 0-131 {}}} CYCLES {}}
set a(0-132) {NAME MAC:asn(acc.lpi) TYPE ASSIGN PAR 0-98 XREFS 474 LOC {1 0.34929774999999996 1 1.0 1 1.0 2 0.910898475} PREDS {{260 0 0-132 {}} {256 0 0-110 {}} {258 0 0-124 {}}} SUCCS {{262 0 0-110 {}} {260 0 0-132 {}}} CYCLES {}}
set a(0-133) {NAME MAC:asn(i#1.lpi) TYPE ASSIGN PAR 0-98 XREFS 475 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 2 0.6507022499999999} PREDS {{260 0 0-133 {}} {256 0 0-104 {}} {258 0 0-125 {}}} SUCCS {{262 0 0-104 {}} {260 0 0-133 {}}} CYCLES {}}
set a(0-134) {NAME MAC:asn(exit:MAC.lpi) TYPE ASSIGN PAR 0-98 XREFS 476 LOC {1 0.11770625 1 1.0 1 1.0 2 0.6507022499999999} PREDS {{260 0 0-134 {}} {256 0 0-99 {}} {256 0 0-101 {}} {256 0 0-107 {}} {258 0 0-129 {}}} SUCCS {{262 0 0-99 {}} {262 0 0-101 {}} {262 0 0-107 {}} {260 0 0-134 {}}} CYCLES {}}
set a(0-98) {CHI {0-99 0-100 0-101 0-102 0-103 0-104 0-105 0-106 0-107 0-108 0-109 0-110 0-111 0-112 0-113 0-114 0-115 0-116 0-117 0-118 0-119 0-120 0-121 0-122 0-123 0-124 0-125 0-126 0-127 0-128 0-129 0-130 0-131 0-132 0-133 0-134} ITERATIONS Infinite LATENCY 5 RESET_LATENCY 0 CSTEPS 2 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 5 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 2.0 CYCLES_IN 5 TOTAL_CYCLES_IN 5 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 5 NAME main TYPE LOOP DELAY {120.00 ns} PAR {} XREFS 477 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
set a(0-98-TOTALCYCLES) {5}
set a(0-98-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(3,2) 0-104 mgc_ioport.mgc_in_wire(1,40) 0-105 mgc_ioport.mgc_in_wire(2,40) 0-106 mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(8,2) 0-110 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(8,3,8) {0-116 0-122} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8) 0-123 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) 0-124 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,1,3) 0-125 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,4) 0-127 mgc_ioport.mgc_out_stdreg(3,8) 0-131}
set a(0-98-PROC_NAME) {core}
set a(0-98-HIER_NAME) {/dot_product/core}
set a(TOP) {0-98}
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