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// ----------------------------------------------------------------------
// HLS HDL: Verilog Netlister
// HLS Version: 2011a.126 Production Release
// HLS Date: Wed Aug 8 00:52:07 PDT 2012
//
// Generated by: mg3115@EEWS104A-015
// Generated date: Tue Mar 01 15:39:39 2016
// ----------------------------------------------------------------------
//
// ------------------------------------------------------------------
// Design Unit: dot_product_core
// ------------------------------------------------------------------
module dot_product_core (
clk, en, arst_n, input_a_rsc_mgc_in_wire_d, input_b_rsc_mgc_in_wire_d, output_rsc_mgc_out_stdreg_d
);
input clk;
input en;
input arst_n;
input [7:0] input_a_rsc_mgc_in_wire_d;
input [7:0] input_b_rsc_mgc_in_wire_d;
output [7:0] output_rsc_mgc_out_stdreg_d;
reg [7:0] output_rsc_mgc_out_stdreg_d;
// Interconnect Declarations
reg exit_MAC_lpi;
reg [7:0] acc_sva_1;
reg [2:0] i_1_sva_1;
wire [2:0] MAC_acc_itm;
wire [3:0] nl_MAC_acc_itm;
wire [7:0] acc_sva_2;
wire [8:0] nl_acc_sva_2;
wire [2:0] i_1_sva_2;
wire [3:0] nl_i_1_sva_2;
// Interconnect Declarations for Component Instantiations
assign nl_acc_sva_2 = (acc_sva_1 & (signext_8_1(~ exit_MAC_lpi))) + conv_s2s_16_8(input_a_rsc_mgc_in_wire_d
* input_b_rsc_mgc_in_wire_d);
assign acc_sva_2 = nl_acc_sva_2[7:0];
assign nl_i_1_sva_2 = (i_1_sva_1 & (signext_3_1(~ exit_MAC_lpi))) + 3'b1;
assign i_1_sva_2 = nl_i_1_sva_2[2:0];
assign nl_MAC_acc_itm = i_1_sva_2 + 3'b11;
assign MAC_acc_itm = nl_MAC_acc_itm[2:0];
always @(posedge clk or negedge arst_n) begin
if ( ~ arst_n ) begin
output_rsc_mgc_out_stdreg_d <= 8'b0;
acc_sva_1 <= 8'b0;
i_1_sva_1 <= 3'b0;
exit_MAC_lpi <= 1'b1;
end
else begin
if ( en ) begin
output_rsc_mgc_out_stdreg_d <= MUX_v_8_2_2({acc_sva_2 , output_rsc_mgc_out_stdreg_d},
MAC_acc_itm[2]);
acc_sva_1 <= acc_sva_2;
i_1_sva_1 <= i_1_sva_2;
exit_MAC_lpi <= ~ (MAC_acc_itm[2]);
end
end
end
function [7:0] signext_8_1;
input [0:0] vector;
begin
signext_8_1= {{7{vector[0]}}, vector};
end
endfunction
function [2:0] signext_3_1;
input [0:0] vector;
begin
signext_3_1= {{2{vector[0]}}, vector};
end
endfunction
function [7:0] MUX_v_8_2_2;
input [15:0] inputs;
input [0:0] sel;
reg [7:0] result;
begin
case (sel)
1'b0 : begin
result = inputs[15:8];
end
1'b1 : begin
result = inputs[7:0];
end
default : begin
result = inputs[15:8];
end
endcase
MUX_v_8_2_2 = result;
end
endfunction
function signed [7:0] conv_s2s_16_8 ;
input signed [15:0] vector ;
begin
conv_s2s_16_8 = vector[7:0];
end
endfunction
endmodule
// ------------------------------------------------------------------
// Design Unit: dot_product
// Generated from file(s):
// 2) $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
// ------------------------------------------------------------------
module dot_product (
input_a_rsc_z, input_b_rsc_z, output_rsc_z, clk, en, arst_n
);
input [7:0] input_a_rsc_z;
input [7:0] input_b_rsc_z;
output [7:0] output_rsc_z;
input clk;
input en;
input arst_n;
// Interconnect Declarations
wire [7:0] input_a_rsc_mgc_in_wire_d;
wire [7:0] input_b_rsc_mgc_in_wire_d;
wire [7:0] output_rsc_mgc_out_stdreg_d;
// Interconnect Declarations for Component Instantiations
mgc_in_wire #(.rscid(1),
.width(8)) input_a_rsc_mgc_in_wire (
.d(input_a_rsc_mgc_in_wire_d),
.z(input_a_rsc_z)
);
mgc_in_wire #(.rscid(2),
.width(8)) input_b_rsc_mgc_in_wire (
.d(input_b_rsc_mgc_in_wire_d),
.z(input_b_rsc_z)
);
mgc_out_stdreg #(.rscid(3),
.width(8)) output_rsc_mgc_out_stdreg (
.d(output_rsc_mgc_out_stdreg_d),
.z(output_rsc_z)
);
dot_product_core dot_product_core_inst (
.clk(clk),
.en(en),
.arst_n(arst_n),
.input_a_rsc_mgc_in_wire_d(input_a_rsc_mgc_in_wire_d),
.input_b_rsc_mgc_in_wire_d(input_b_rsc_mgc_in_wire_d),
.output_rsc_mgc_out_stdreg_d(output_rsc_mgc_out_stdreg_d)
);
endmodule
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