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--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" LPM_WIDTH=11 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources =
SUBDESIGN cmpr_vgc
(
aeb : output;
dataa[10..0] : input;
datab[10..0] : input;
)
VARIABLE
aeb_result_wire[0..0] : WIRE;
aneb_result_wire[0..0] : WIRE;
data_wire[29..0] : WIRE;
eq_wire : WIRE;
BEGIN
aeb = eq_wire;
aeb_result_wire[] = (! aneb_result_wire[]);
aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
data_wire[] = ( datab[10..10], dataa[10..10], datab[9..9], dataa[9..9], datab[8..8], dataa[8..8], datab[7..7], dataa[7..7], datab[6..6], dataa[6..6], datab[5..5], dataa[5..5], datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[28..28] $ data_wire[29..29]), ((data_wire[24..24] $ data_wire[25..25]) # (data_wire[26..26] $ data_wire[27..27])), ((data_wire[20..20] $ data_wire[21..21]) # (data_wire[22..22] $ data_wire[23..23])), ((data_wire[16..16] $ data_wire[17..17]) # (data_wire[18..18] $ data_wire[19..19])), ((data_wire[12..12] $ data_wire[13..13]) # (data_wire[14..14] $ data_wire[15..15])), ((data_wire[8..8] $ data_wire[9..9]) # (data_wire[10..10] $ data_wire[11..11])), (data_wire[6..6] # data_wire[7..7]), (((data_wire[2..2] # data_wire[3..3]) # data_wire[4..4]) # data_wire[5..5]));
eq_wire = aeb_result_wire[];
END;
--VALID FILE
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