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authorYann Herklotz <ymherklotz@gmail.com>2017-02-22 00:14:38 +0000
committerYann Herklotz <ymherklotz@gmail.com>2017-02-22 00:14:38 +0000
commite318230b35fc130d74f1b4c6b70bbb2d5afe6780 (patch)
tree1a1730eb8f35f6932ce82e349c2dba1c089b1b64 /BPC3011-Papilio_Pro-general.ucf
parent0446c43ffae38888dfad9120281acde6a7954509 (diff)
downloadFPGA_Playground-master.tar.gz
FPGA_Playground-master.zip
Working blinking lightHEADmaster
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+# UCF file for the Papilio Pro board
+# Generated by pin_converter, written by Kevin Lindsey
+# https://github.com/thelonious/papilio_pins/tree/development/pin_converter
+
+# Main board wing pin [] to FPGA pin Pxx map
+# -------C------- -------B------- -------A-------
+# [GND] [C00] P114 [GND] [B00] P99 P100 [A15]
+# [2V5] [C01] P115 [2V5] [B01] P97 P98 [A14]
+# [3V3] [C02] P116 [3V3] [B02] P92 P93 [A13]
+# [5V0] [C03] P117 [5V0] [B03] P87 P88 [A12]
+# [C04] P118 [B04] P84 P85 [A11] [5V0]
+# [C05] P119 [B05] P82 P83 [A10] [3V3]
+# [C06] P120 [B06] P80 P81 [A09] [2V5]
+# [C07] P121 [B07] P78 P79 [A08] [GND]
+# [GND] [C08] P123 [GND] [B08] P74 P75 [A07]
+# [2V5] [C09] P124 [2V5] [B09] P95 P67 [A06]
+# [3V3] [C10] P126 [3V3] [B10] P62 P66 [A05]
+# [5V0] [C11] P127 [5V0] [B11] P59 P61 [A04]
+# [C12] P131 [B12] P57 P58 [A03] [5V0]
+# [C13] P132 [B13] P55 P56 [A02] [3V3]
+# [C14] P133 [B14] P50 P51 [A01] [2V5]
+# [C15] P134 [B15] P47 P48 [A00] [GND]
+
+## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.
+CONFIG PROHIBIT=P144;
+CONFIG PROHIBIT=P69;
+CONFIG PROHIBIT=P60;
+
+NET CLK LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLK
+NET RX LOC="P101" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RX
+#NET TX LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TX
+NET A(0) LOC="P48" | IOSTANDARD=LVTTL; # A0
+NET A(1) LOC="P51" | IOSTANDARD=LVTTL; # A1
+NET A(2) LOC="P56" | IOSTANDARD=LVTTL; # A2
+NET A(3) LOC="P58" | IOSTANDARD=LVTTL; # A3
+NET A(4) LOC="P61" | IOSTANDARD=LVTTL; # A4
+NET A(5) LOC="P66" | IOSTANDARD=LVTTL; # A5
+NET A(6) LOC="P67" | IOSTANDARD=LVTTL; # A6
+NET A(7) LOC="P75" | IOSTANDARD=LVTTL; # A7
+NET A(8) LOC="P79" | IOSTANDARD=LVTTL; # A8
+NET A(9) LOC="P81" | IOSTANDARD=LVTTL; # A9
+NET A(10) LOC="P83" | IOSTANDARD=LVTTL; # A10
+NET A(11) LOC="P85" | IOSTANDARD=LVTTL; # A11
+NET A(12) LOC="P88" | IOSTANDARD=LVTTL; # A12
+NET A(13) LOC="P93" | IOSTANDARD=LVTTL; # A13
+NET A(14) LOC="P98" | IOSTANDARD=LVTTL; # A14
+NET A(15) LOC="P100" | IOSTANDARD=LVTTL; # A15
+NET B(0) LOC="P99" | IOSTANDARD=LVTTL; # B0
+NET B(1) LOC="P97" | IOSTANDARD=LVTTL; # B1
+NET B(2) LOC="P92" | IOSTANDARD=LVTTL; # B2
+NET B(3) LOC="P87" | IOSTANDARD=LVTTL; # B3
+NET B(4) LOC="P84" | IOSTANDARD=LVTTL; # B4
+NET B(5) LOC="P82" | IOSTANDARD=LVTTL; # B5
+NET B(6) LOC="P80" | IOSTANDARD=LVTTL; # B6
+NET B(7) LOC="P78" | IOSTANDARD=LVTTL; # B7
+NET B(8) LOC="P74" | IOSTANDARD=LVTTL; # B8
+NET B(9) LOC="P95" | IOSTANDARD=LVTTL; # B9
+NET B(10) LOC="P62" | IOSTANDARD=LVTTL; # B10
+NET B(11) LOC="P59" | IOSTANDARD=LVTTL; # B11
+NET B(12) LOC="P57" | IOSTANDARD=LVTTL; # B12
+NET B(13) LOC="P55" | IOSTANDARD=LVTTL; # B13
+NET B(14) LOC="P50" | IOSTANDARD=LVTTL; # B14
+NET B(15) LOC="P47" | IOSTANDARD=LVTTL; # B15
+NET C(0) LOC="P114" | IOSTANDARD=LVTTL; # C0
+NET C(1) LOC="P115" | IOSTANDARD=LVTTL; # C1
+NET C(2) LOC="P116" | IOSTANDARD=LVTTL; # C2
+NET C(3) LOC="P117" | IOSTANDARD=LVTTL; # C3
+NET C(4) LOC="P118" | IOSTANDARD=LVTTL; # C4
+NET C(5) LOC="P119" | IOSTANDARD=LVTTL; # C5
+NET C(6) LOC="P120" | IOSTANDARD=LVTTL; # C6
+NET C(7) LOC="P121" | IOSTANDARD=LVTTL; # C7
+NET C(8) LOC="P123" | IOSTANDARD=LVTTL; # C8
+NET C(9) LOC="P124" | IOSTANDARD=LVTTL; # C9
+NET C(10) LOC="P126" | IOSTANDARD=LVTTL; # C10
+NET C(11) LOC="P127" | IOSTANDARD=LVTTL; # C11
+NET C(12) LOC="P131" | IOSTANDARD=LVTTL; # C12
+NET C(13) LOC="P132" | IOSTANDARD=LVTTL; # C13
+NET C(14) LOC="P133" | IOSTANDARD=LVTTL; # C14
+NET C(15) LOC="P134" | IOSTANDARD=LVTTL; # C15
+NET SDRAM_ADDR(0) LOC="P140" | IOSTANDARD=LVTTL; # SDRAM_ADDR0
+NET SDRAM_ADDR(1) LOC="P139" | IOSTANDARD=LVTTL; # SDRAM_ADDR1
+NET SDRAM_ADDR(2) LOC="P138" | IOSTANDARD=LVTTL; # SDRAM_ADDR2
+NET SDRAM_ADDR(3) LOC="P137" | IOSTANDARD=LVTTL; # SDRAM_ADDR3
+NET SDRAM_ADDR(4) LOC="P46" | IOSTANDARD=LVTTL; # SDRAM_ADDR4
+NET SDRAM_ADDR(5) LOC="P45" | IOSTANDARD=LVTTL; # SDRAM_ADDR5
+NET SDRAM_ADDR(6) LOC="P44" | IOSTANDARD=LVTTL; # SDRAM_ADDR6
+NET SDRAM_ADDR(7) LOC="P43" | IOSTANDARD=LVTTL; # SDRAM_ADDR7
+NET SDRAM_ADDR(8) LOC="P41" | IOSTANDARD=LVTTL; # SDRAM_ADDR8
+NET SDRAM_ADDR(9) LOC="P40" | IOSTANDARD=LVTTL; # SDRAM_ADDR9
+NET SDRAM_ADDR(10) LOC="P141" | IOSTANDARD=LVTTL; # SDRAM_ADDR10
+NET SDRAM_ADDR(11) LOC="P35" | IOSTANDARD=LVTTL; # SDRAM_ADDR11
+NET SDRAM_ADDR(12) LOC="P34" | IOSTANDARD=LVTTL; # SDRAM_ADDR12
+NET SDRAM_DATA(0) LOC="P9" | IOSTANDARD=LVTTL; # SDRAM_DATA0
+NET SDRAM_DATA(1) LOC="P10" | IOSTANDARD=LVTTL; # SDRAM_DATA1
+NET SDRAM_DATA(2) LOC="P11" | IOSTANDARD=LVTTL; # SDRAM_DATA2
+NET SDRAM_DATA(3) LOC="P12" | IOSTANDARD=LVTTL; # SDRAM_DATA3
+NET SDRAM_DATA(4) LOC="P14" | IOSTANDARD=LVTTL; # SDRAM_DATA4
+NET SDRAM_DATA(5) LOC="P15" | IOSTANDARD=LVTTL; # SDRAM_DATA5
+NET SDRAM_DATA(6) LOC="P16" | IOSTANDARD=LVTTL; # SDRAM_DATA6
+NET SDRAM_DATA(7) LOC="P8" | IOSTANDARD=LVTTL; # SDRAM_DATA7
+NET SDRAM_DATA(8) LOC="P21" | IOSTANDARD=LVTTL; # SDRAM_DATA8
+NET SDRAM_DATA(9) LOC="P22" | IOSTANDARD=LVTTL; # SDRAM_DATA9
+NET SDRAM_DATA(10) LOC="P23" | IOSTANDARD=LVTTL; # SDRAM_DATA10
+NET SDRAM_DATA(11) LOC="P24" | IOSTANDARD=LVTTL; # SDRAM_DATA11
+NET SDRAM_DATA(12) LOC="P26" | IOSTANDARD=LVTTL; # SDRAM_DATA12
+NET SDRAM_DATA(13) LOC="P27" | IOSTANDARD=LVTTL; # SDRAM_DATA13
+NET SDRAM_DATA(14) LOC="P29" | IOSTANDARD=LVTTL; # SDRAM_DATA14
+NET SDRAM_DATA(15) LOC="P30" | IOSTANDARD=LVTTL; # SDRAM_DATA15
+NET SDRAM_DQML LOC="P7" | IOSTANDARD=LVTTL; # SDRAM_DQML
+NET SDRAM_DQMH LOC="P17" | IOSTANDARD=LVTTL; # SDRAM_DQMH
+NET SDRAM_BA(0) LOC="P143" | IOSTANDARD=LVTTL; # SDRAM_BA0
+NET SDRAM_BA(1) LOC="P142" | IOSTANDARD=LVTTL; # SDRAM_BA1
+NET SDRAM_nWE LOC="P6" | IOSTANDARD=LVTTL; # SDRAM_nWE
+NET SDRAM_nCAS LOC="P5" | IOSTANDARD=LVTTL; # SDRAM_nCAS
+NET SDRAM_nRAS LOC="P2" | IOSTANDARD=LVTTL; # SDRAM_nRAS
+NET SDRAM_CS LOC="P1" | IOSTANDARD=LVTTL; # SDRAM_CS
+NET SDRAM_CLK LOC="P32" | IOSTANDARD=LVTTL; # SDRAM_CLK
+NET SDRAM_CKE LOC="P33" | IOSTANDARD=LVTTL; # SDRAM_CKE
+NET LED1 LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; # LED1
+NET JTAG_TMS LOC="P107" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TMS
+NET JTAG_TCK LOC="P109" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TCK
+NET JTAG_TDI LOC="P110" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDI
+NET JTAG_TDO LOC="P106" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDO
+NET FLASH_CS LOC="P38" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CS
+NET FLASH_CK LOC="P70" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CK
+NET FLASH_SI LOC="P64" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SI
+#NET FLASH_SO LOC="P65" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO
generated by cgit (git 2.34.1) at 2024-05-28 20:54:03 +0000