Working blinking lightHEAD master

author: Yann Herklotz <ymherklotz@gmail.com> 2017-02-22 00:14:38 +0000
committer: Yann Herklotz <ymherklotz@gmail.com> 2017-02-22 00:14:38 +0000
commit: e318230b35fc130d74f1b4c6b70bbb2d5afe6780 (patch)
tree: 1a1730eb8f35f6932ce82e349c2dba1c089b1b64
parent: 0446c43ffae38888dfad9120281acde6a7954509 (diff)
download: FPGA_Playground-master.tar.gz
FPGA_Playground-master.zip
122 files changed, 16283 insertions, 265 deletions
diff --git a/BPC3011-Papilio_Pro-general.ucf b/BPC3011-Papilio_Pro-general.ucf
new file mode 100644
index 0000000..845fdf2
--- /dev/null
+++ b/BPC3011-Papilio_Pro-general.ucf
@@ -0,0 +1,127 @@
+# UCF file for the Papilio Pro board
+# Generated by pin_converter, written by Kevin Lindsey
+# https://github.com/thelonious/papilio_pins/tree/development/pin_converter
+
+# Main board wing pin [] to FPGA pin Pxx map
+# -------C-------    -------B-------    -------A-------
+# [GND] [C00] P114   [GND] [B00] P99    P100 [A15]
+# [2V5] [C01] P115   [2V5] [B01] P97    P98 [A14]
+# [3V3] [C02] P116   [3V3] [B02] P92    P93 [A13]
+# [5V0] [C03] P117   [5V0] [B03] P87    P88 [A12]
+#       [C04] P118         [B04] P84    P85 [A11] [5V0]
+#       [C05] P119         [B05] P82    P83 [A10] [3V3]
+#       [C06] P120         [B06] P80    P81 [A09] [2V5]
+#       [C07] P121         [B07] P78    P79 [A08] [GND]
+# [GND] [C08] P123   [GND] [B08] P74    P75 [A07]
+# [2V5] [C09] P124   [2V5] [B09] P95    P67 [A06]
+# [3V3] [C10] P126   [3V3] [B10] P62    P66 [A05]
+# [5V0] [C11] P127   [5V0] [B11] P59    P61 [A04]
+#       [C12] P131         [B12] P57    P58 [A03] [5V0]
+#       [C13] P132         [B13] P55    P56 [A02] [3V3]
+#       [C14] P133         [B14] P50    P51 [A01] [2V5]
+#       [C15] P134         [B15] P47    P48 [A00] [GND]
+
+## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.
+CONFIG PROHIBIT=P144;
+CONFIG PROHIBIT=P69;
+CONFIG PROHIBIT=P60;
+
+NET CLK            LOC="P94"  | IOSTANDARD=LVTTL | PERIOD=31.25ns;               # CLK
+NET RX             LOC="P101" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # RX
+#NET TX             LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TX
+NET A(0)           LOC="P48"  | IOSTANDARD=LVTTL;                                # A0
+NET A(1)           LOC="P51"  | IOSTANDARD=LVTTL;                                # A1
+NET A(2)           LOC="P56"  | IOSTANDARD=LVTTL;                                # A2
+NET A(3)           LOC="P58"  | IOSTANDARD=LVTTL;                                # A3
+NET A(4)           LOC="P61"  | IOSTANDARD=LVTTL;                                # A4
+NET A(5)           LOC="P66"  | IOSTANDARD=LVTTL;                                # A5
+NET A(6)           LOC="P67"  | IOSTANDARD=LVTTL;                                # A6
+NET A(7)           LOC="P75"  | IOSTANDARD=LVTTL;                                # A7
+NET A(8)           LOC="P79"  | IOSTANDARD=LVTTL;                                # A8
+NET A(9)           LOC="P81"  | IOSTANDARD=LVTTL;                                # A9
+NET A(10)          LOC="P83"  | IOSTANDARD=LVTTL;                                # A10
+NET A(11)          LOC="P85"  | IOSTANDARD=LVTTL;                                # A11
+NET A(12)          LOC="P88"  | IOSTANDARD=LVTTL;                                # A12
+NET A(13)          LOC="P93"  | IOSTANDARD=LVTTL;                                # A13
+NET A(14)          LOC="P98"  | IOSTANDARD=LVTTL;                                # A14
+NET A(15)          LOC="P100" | IOSTANDARD=LVTTL;                                # A15
+NET B(0)           LOC="P99"  | IOSTANDARD=LVTTL;                                # B0
+NET B(1)           LOC="P97"  | IOSTANDARD=LVTTL;                                # B1
+NET B(2)           LOC="P92"  | IOSTANDARD=LVTTL;                                # B2
+NET B(3)           LOC="P87"  | IOSTANDARD=LVTTL;                                # B3
+NET B(4)           LOC="P84"  | IOSTANDARD=LVTTL;                                # B4
+NET B(5)           LOC="P82"  | IOSTANDARD=LVTTL;                                # B5
+NET B(6)           LOC="P80"  | IOSTANDARD=LVTTL;                                # B6
+NET B(7)           LOC="P78"  | IOSTANDARD=LVTTL;                                # B7
+NET B(8)           LOC="P74"  | IOSTANDARD=LVTTL;                                # B8
+NET B(9)           LOC="P95"  | IOSTANDARD=LVTTL;                                # B9
+NET B(10)          LOC="P62"  | IOSTANDARD=LVTTL;                                # B10
+NET B(11)          LOC="P59"  | IOSTANDARD=LVTTL;                                # B11
+NET B(12)          LOC="P57"  | IOSTANDARD=LVTTL;                                # B12
+NET B(13)          LOC="P55"  | IOSTANDARD=LVTTL;                                # B13
+NET B(14)          LOC="P50"  | IOSTANDARD=LVTTL;                                # B14
+NET B(15)          LOC="P47"  | IOSTANDARD=LVTTL;                                # B15
+NET C(0)           LOC="P114" | IOSTANDARD=LVTTL;                                # C0
+NET C(1)           LOC="P115" | IOSTANDARD=LVTTL;                                # C1
+NET C(2)           LOC="P116" | IOSTANDARD=LVTTL;                                # C2
+NET C(3)           LOC="P117" | IOSTANDARD=LVTTL;                                # C3
+NET C(4)           LOC="P118" | IOSTANDARD=LVTTL;                                # C4
+NET C(5)           LOC="P119" | IOSTANDARD=LVTTL;                                # C5
+NET C(6)           LOC="P120" | IOSTANDARD=LVTTL;                                # C6
+NET C(7)           LOC="P121" | IOSTANDARD=LVTTL;                                # C7
+NET C(8)           LOC="P123" | IOSTANDARD=LVTTL;                                # C8
+NET C(9)           LOC="P124" | IOSTANDARD=LVTTL;                                # C9
+NET C(10)          LOC="P126" | IOSTANDARD=LVTTL;                                # C10
+NET C(11)          LOC="P127" | IOSTANDARD=LVTTL;                                # C11
+NET C(12)          LOC="P131" | IOSTANDARD=LVTTL;                                # C12
+NET C(13)          LOC="P132" | IOSTANDARD=LVTTL;                                # C13
+NET C(14)          LOC="P133" | IOSTANDARD=LVTTL;                                # C14
+NET C(15)          LOC="P134" | IOSTANDARD=LVTTL;                                # C15
+NET SDRAM_ADDR(0)  LOC="P140" | IOSTANDARD=LVTTL;                                # SDRAM_ADDR0
+NET SDRAM_ADDR(1)  LOC="P139" | IOSTANDARD=LVTTL;                                # SDRAM_ADDR1
+NET SDRAM_ADDR(2)  LOC="P138" | IOSTANDARD=LVTTL;                                # SDRAM_ADDR2
+NET SDRAM_ADDR(3)  LOC="P137" | IOSTANDARD=LVTTL;                                # SDRAM_ADDR3
+NET SDRAM_ADDR(4)  LOC="P46"  | IOSTANDARD=LVTTL;                                # SDRAM_ADDR4
+NET SDRAM_ADDR(5)  LOC="P45"  | IOSTANDARD=LVTTL;                                # SDRAM_ADDR5
+NET SDRAM_ADDR(6)  LOC="P44"  | IOSTANDARD=LVTTL;                                # SDRAM_ADDR6
+NET SDRAM_ADDR(7)  LOC="P43"  | IOSTANDARD=LVTTL;                                # SDRAM_ADDR7
+NET SDRAM_ADDR(8)  LOC="P41"  | IOSTANDARD=LVTTL;                                # SDRAM_ADDR8
+NET SDRAM_ADDR(9)  LOC="P40"  | IOSTANDARD=LVTTL;                                # SDRAM_ADDR9
+NET SDRAM_ADDR(10) LOC="P141" | IOSTANDARD=LVTTL;                                # SDRAM_ADDR10
+NET SDRAM_ADDR(11) LOC="P35"  | IOSTANDARD=LVTTL;                                # SDRAM_ADDR11
+NET SDRAM_ADDR(12) LOC="P34"  | IOSTANDARD=LVTTL;                                # SDRAM_ADDR12
+NET SDRAM_DATA(0)  LOC="P9"   | IOSTANDARD=LVTTL;                                # SDRAM_DATA0
+NET SDRAM_DATA(1)  LOC="P10"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA1
+NET SDRAM_DATA(2)  LOC="P11"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA2
+NET SDRAM_DATA(3)  LOC="P12"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA3
+NET SDRAM_DATA(4)  LOC="P14"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA4
+NET SDRAM_DATA(5)  LOC="P15"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA5
+NET SDRAM_DATA(6)  LOC="P16"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA6
+NET SDRAM_DATA(7)  LOC="P8"   | IOSTANDARD=LVTTL;                                # SDRAM_DATA7
+NET SDRAM_DATA(8)  LOC="P21"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA8
+NET SDRAM_DATA(9)  LOC="P22"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA9
+NET SDRAM_DATA(10) LOC="P23"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA10
+NET SDRAM_DATA(11) LOC="P24"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA11
+NET SDRAM_DATA(12) LOC="P26"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA12
+NET SDRAM_DATA(13) LOC="P27"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA13
+NET SDRAM_DATA(14) LOC="P29"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA14
+NET SDRAM_DATA(15) LOC="P30"  | IOSTANDARD=LVTTL;                                # SDRAM_DATA15
+NET SDRAM_DQML     LOC="P7"   | IOSTANDARD=LVTTL;                                # SDRAM_DQML
+NET SDRAM_DQMH     LOC="P17"  | IOSTANDARD=LVTTL;                                # SDRAM_DQMH
+NET SDRAM_BA(0)    LOC="P143" | IOSTANDARD=LVTTL;                                # SDRAM_BA0
+NET SDRAM_BA(1)    LOC="P142" | IOSTANDARD=LVTTL;                                # SDRAM_BA1
+NET SDRAM_nWE      LOC="P6"   | IOSTANDARD=LVTTL;                                # SDRAM_nWE
+NET SDRAM_nCAS     LOC="P5"   | IOSTANDARD=LVTTL;                                # SDRAM_nCAS
+NET SDRAM_nRAS     LOC="P2"   | IOSTANDARD=LVTTL;                                # SDRAM_nRAS
+NET SDRAM_CS       LOC="P1"   | IOSTANDARD=LVTTL;                                # SDRAM_CS
+NET SDRAM_CLK      LOC="P32"  | IOSTANDARD=LVTTL;                                # SDRAM_CLK
+NET SDRAM_CKE      LOC="P33"  | IOSTANDARD=LVTTL;                                # SDRAM_CKE
+NET LED1           LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;          # LED1
+NET JTAG_TMS       LOC="P107" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # JTAG_TMS
+NET JTAG_TCK       LOC="P109" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # JTAG_TCK
+NET JTAG_TDI       LOC="P110" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # JTAG_TDI
+NET JTAG_TDO       LOC="P106" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # JTAG_TDO
+NET FLASH_CS       LOC="P38"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # FLASH_CS
+NET FLASH_CK       LOC="P70"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # FLASH_CK
+NET FLASH_SI       LOC="P64"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # FLASH_SI
+#NET FLASH_SO       LOC="P65"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO
diff --git a/FPGA-led-lights.gise b/FPGA-led-lights.gise
index 481f264..d852a79 100644
--- a/FPGA-led-lights.gise
+++ b/FPGA-led-lights.gise
@@ -22,64 +22,195 @@
   <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FPGA-led-lights.xise"/>
 
   <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="led.bgn" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="led.bit" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="led.bld"/>
     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="led.cmd_log"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="led.drc" xil_pn:subbranch="FPGAConfiguration"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="led.lso"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="led.ncd" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="led.ngc"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="led.ngd"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="led.ngr"/>
+    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="led.pad"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="led.par" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="led.pcf" xil_pn:subbranch="Map"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="led.prj"/>
+    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="led.ptwx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="led.stx"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="led.syr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="led.twr" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="led.twx" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="led.unroutes" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="led.ut" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:fileType="FILE_XPI" xil_pn:name="led.xpi"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="led.xst"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="led_envsettings.html"/>
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="led_guide.ncd" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="led_map.map" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="led_map.mrp" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="led_map.ncd" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="led_map.ngm" xil_pn:subbranch="Map"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="led_map.xrpt"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="led_ngdbuild.xrpt"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="led_pad.csv" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="led_pad.txt" xil_pn:subbranch="Par"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="led_par.xrpt"/>
     <file xil_pn:fileType="FILE_HTML" xil_pn:name="led_summary.html"/>
+    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="led_summary.xml"/>
+    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="led_usage.xml"/>
     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="led_xst.xrpt"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_4"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
+    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
     <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
   </files>
 
   <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1487546128">
+    <transform xil_pn:end_ts="1487712773" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1487712773">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6442174705589123182" xil_pn:start_ts="1487546129">
+    <transform xil_pn:end_ts="1487712773" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="2687710351385008554" xil_pn:start_ts="1487712773">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1227048648073386772" xil_pn:start_ts="1487546129">
+    <transform xil_pn:end_ts="1487713076" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8564384985097914375" xil_pn:start_ts="1487713076">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1487546129">
+    <transform xil_pn:end_ts="1487712773" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1487712773">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="2590979178147000940" xil_pn:start_ts="1487546129">
+    <transform xil_pn:end_ts="1487712773" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="2590979178147000940" xil_pn:start_ts="1487712773">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="5199527252420087910" xil_pn:start_ts="1487546129">
+    <transform xil_pn:end_ts="1487712773" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1487712773">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-421007744913001546" xil_pn:start_ts="1487546129">
+    <transform xil_pn:end_ts="1487713076" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8229807836551992707" xil_pn:start_ts="1487713076">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1487546132" xil_pn:in_ck="131819641" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-9170951106228638093" xil_pn:start_ts="1487546129">
-      <status xil_pn:value="FailedRun"/>
+    <transform xil_pn:end_ts="1487715017" xil_pn:in_ck="131819641" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="4753490412739147880" xil_pn:start_ts="1487715011">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
       <outfile xil_pn:name="led.lso"/>
+      <outfile xil_pn:name="led.ngc"/>
+      <outfile xil_pn:name="led.ngr"/>
       <outfile xil_pn:name="led.prj"/>
+      <outfile xil_pn:name="led.stx"/>
       <outfile xil_pn:name="led.syr"/>
       <outfile xil_pn:name="led.xst"/>
       <outfile xil_pn:name="led_xst.xrpt"/>
       <outfile xil_pn:name="webtalk_pn.xml"/>
       <outfile xil_pn:name="xst"/>
     </transform>
-    <transform xil_pn:end_ts="1487546132" xil_pn:in_ck="8586762664122563020" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3734212952602903" xil_pn:start_ts="1487546132">
+    <transform xil_pn:end_ts="1487715399" xil_pn:in_ck="4834887014787387356" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3734212952602903" xil_pn:start_ts="1487715399">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1487715404" xil_pn:in_ck="-6554730637971917129" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-5807652207078553553" xil_pn:start_ts="1487715399">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <outfile xil_pn:name="_ngo"/>
+      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+      <outfile xil_pn:name="led.bld"/>
+      <outfile xil_pn:name="led.ngd"/>
+      <outfile xil_pn:name="led_ngdbuild.xrpt"/>
+    </transform>
+    <transform xil_pn:end_ts="1487715414" xil_pn:in_ck="-6554730637971917128" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1487715407">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="OutputChanged"/>
+      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
+      <outfile xil_pn:name="led.pcf"/>
+      <outfile xil_pn:name="led_map.map"/>
+      <outfile xil_pn:name="led_map.mrp"/>
+      <outfile xil_pn:name="led_map.ncd"/>
+      <outfile xil_pn:name="led_map.ngm"/>
+      <outfile xil_pn:name="led_map.xrpt"/>
+      <outfile xil_pn:name="led_summary.xml"/>
+      <outfile xil_pn:name="led_usage.xml"/>
+    </transform>
+    <transform xil_pn:end_ts="1487715423" xil_pn:in_ck="-8547227296926146095" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1487715414">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
+      <outfile xil_pn:name="led.ncd"/>
+      <outfile xil_pn:name="led.pad"/>
+      <outfile xil_pn:name="led.par"/>
+      <outfile xil_pn:name="led.ptwx"/>
+      <outfile xil_pn:name="led.unroutes"/>
+      <outfile xil_pn:name="led.xpi"/>
+      <outfile xil_pn:name="led_pad.csv"/>
+      <outfile xil_pn:name="led_pad.txt"/>
+      <outfile xil_pn:name="led_par.xrpt"/>
+    </transform>
+    <transform xil_pn:end_ts="1487715430" xil_pn:in_ck="143551583704" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="5341574683187206424" xil_pn:start_ts="1487715423">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+      <outfile xil_pn:name="led.bgn"/>
+      <outfile xil_pn:name="led.bit"/>
+      <outfile xil_pn:name="led.drc"/>
+      <outfile xil_pn:name="led.ut"/>
+      <outfile xil_pn:name="usage_statistics_webtalk.html"/>
+      <outfile xil_pn:name="webtalk.log"/>
+      <outfile xil_pn:name="webtalk_pn.xml"/>
+    </transform>
+    <transform xil_pn:end_ts="1487713792" xil_pn:in_ck="-3553499765603855836" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1487713790">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="InputAdded"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="InputRemoved"/>
+    </transform>
+    <transform xil_pn:end_ts="1487715423" xil_pn:in_ck="-6554730637971917260" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1487715419">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
+      <outfile xil_pn:name="led.twr"/>
+      <outfile xil_pn:name="led.twx"/>
+    </transform>
+    <transform xil_pn:end_ts="1487713747" xil_pn:in_ck="-3553499765603855704" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1487713741">
+      <status xil_pn:value="FailedRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="InputAdded"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="InputRemoved"/>
     </transform>
   </transforms>
 
diff --git a/FPGA-led-lights.xise b/FPGA-led-lights.xise
index c727728..1e233b5 100644
--- a/FPGA-led-lights.xise
+++ b/FPGA-led-lights.xise
@@ -19,17 +19,19 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
-    <file xil_pn:name="../../Downloads/BPC3011-Papilio_Pro-general.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    <file xil_pn:name="BPC3011-Papilio_Pro-general.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
     </file>
   </files>
 
   <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
     <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -45,8 +47,8 @@
     <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
     <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
     <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -59,40 +61,50 @@
     <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
     <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
     <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc3s250e" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
     <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
     <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
     <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
     <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -102,6 +114,8 @@
     <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
     <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
     <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -120,6 +134,7 @@
     <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
@@ -141,6 +156,8 @@
     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
@@ -150,26 +167,35 @@
     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
     <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
     <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
     <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
     <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
@@ -190,20 +216,25 @@
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="led_map.v" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="led_timesim.v" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="led_synthesis.v" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="led_translate.v" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
     <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -214,10 +245,12 @@
     <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
     <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
@@ -231,10 +264,10 @@
     <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
     <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
     <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
@@ -250,7 +283,10 @@
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
@@ -265,12 +301,13 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
@@ -278,7 +315,7 @@
     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
     <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -291,19 +328,24 @@
     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
     <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -312,7 +354,7 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="FPGA-led-lights" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
diff --git a/_ngo/netlist.lst b/_ngo/netlist.lst
new file mode 100644
index 0000000..e8fb2da
--- /dev/null
+++ b/_ngo/netlist.lst
@@ -0,0 +1,2 @@
+/home/yannherklotz/Github/FPGA-led-lights/led.ngc 1487715017
+OK
diff --git a/_xmsgs/bitgen.xmsgs b/_xmsgs/bitgen.xmsgs
new file mode 100644
index 0000000..f84336a
--- /dev/null
+++ b/_xmsgs/bitgen.xmsgs
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+</messages>
+
diff --git a/_xmsgs/map.xmsgs b/_xmsgs/map.xmsgs
new file mode 100644
index 0000000..a457d4d
--- /dev/null
+++ b/_xmsgs/map.xmsgs
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="MapLib" num="564" delta="old" >The following environment variables are currently set:
+</msg>
+
+<msg type="info" file="MapLib" num="591" delta="old" ><arg fmt="%s" index="1">XIL_MAP_LOCWARN</arg> 	Value: <arg fmt="%s" index="2">1</arg>
+</msg>
+
+<msg type="info" file="MapLib" num="159" delta="old" >Net Timing constraints on signal <arg fmt="%s" index="1">CLK</arg> are pushed forward through input buffer.
+</msg>
+
+<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
+</msg>
+
+<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
+</msg>
+
+<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
+</msg>
+
+<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
+</msg>
+
+<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
+</msg>
+
+</messages>
+
diff --git a/_xmsgs/ngdbuild.xmsgs b/_xmsgs/ngdbuild.xmsgs
new file mode 100644
index 0000000..29ca303
--- /dev/null
+++ b/_xmsgs/ngdbuild.xmsgs
@@ -0,0 +1,1327 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET RX             LOC=&quot;P101&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(30)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">RX</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET RX             LOC=&quot;P101&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(30)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL |&gt; [BPC3011-Papilio_Pro-general.ucf(30)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">RX</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;DRIVE=8 |&gt; [BPC3011-Papilio_Pro-general.ucf(30)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">RX</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;SLEW=FAST;&gt; [BPC3011-Papilio_Pro-general.ucf(30)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">RX</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(0)           LOC=&quot;P48&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(32)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(0)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(0)           LOC=&quot;P48&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(32)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(32)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(0)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(1)           LOC=&quot;P51&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(33)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(1)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(1)           LOC=&quot;P51&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(33)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(33)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(1)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(2)           LOC=&quot;P56&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(34)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(2)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(2)           LOC=&quot;P56&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(34)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(34)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(2)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(3)           LOC=&quot;P58&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(35)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(3)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(3)           LOC=&quot;P58&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(35)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(35)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(3)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(4)           LOC=&quot;P61&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(36)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(4)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(4)           LOC=&quot;P61&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(36)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(36)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(4)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(5)           LOC=&quot;P66&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(37)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(5)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(5)           LOC=&quot;P66&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(37)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(37)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(5)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(6)           LOC=&quot;P67&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(38)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(6)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(6)           LOC=&quot;P67&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(38)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(38)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(6)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(7)           LOC=&quot;P75&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(39)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(7)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(7)           LOC=&quot;P75&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(39)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(39)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(7)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(8)           LOC=&quot;P79&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(40)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(8)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(8)           LOC=&quot;P79&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(40)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(40)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(8)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(9)           LOC=&quot;P81&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(41)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(9)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(9)           LOC=&quot;P81&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(41)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(41)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(9)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(10)          LOC=&quot;P83&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(42)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(10)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(10)          LOC=&quot;P83&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(42)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(42)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(10)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(11)          LOC=&quot;P85&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(43)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(11)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(11)          LOC=&quot;P85&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(43)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(43)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(11)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(12)          LOC=&quot;P88&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(44)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(12)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(12)          LOC=&quot;P88&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(44)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(44)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(12)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(13)          LOC=&quot;P93&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(45)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(13)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(13)          LOC=&quot;P93&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(45)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(45)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(13)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(14)          LOC=&quot;P98&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(46)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(14)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(14)          LOC=&quot;P98&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(46)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(46)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(14)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET A(15)          LOC=&quot;P100&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(47)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(15)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET A(15)          LOC=&quot;P100&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(47)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(47)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">A(15)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(0)           LOC=&quot;P99&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(48)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(0)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(0)           LOC=&quot;P99&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(48)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(48)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(0)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(1)           LOC=&quot;P97&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(49)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(1)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(1)           LOC=&quot;P97&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(49)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(49)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(1)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(2)           LOC=&quot;P92&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(50)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(2)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(2)           LOC=&quot;P92&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(50)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(50)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(2)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(3)           LOC=&quot;P87&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(51)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(3)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(3)           LOC=&quot;P87&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(51)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(51)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(3)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(4)           LOC=&quot;P84&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(52)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(4)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(4)           LOC=&quot;P84&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(52)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(52)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(4)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(5)           LOC=&quot;P82&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(53)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(5)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(5)           LOC=&quot;P82&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(53)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(53)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(5)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(6)           LOC=&quot;P80&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(54)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(6)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(6)           LOC=&quot;P80&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(54)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(54)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(6)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(7)           LOC=&quot;P78&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(55)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(7)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(7)           LOC=&quot;P78&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(55)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(55)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(7)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(8)           LOC=&quot;P74&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(56)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(8)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(8)           LOC=&quot;P74&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(56)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(56)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(8)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(9)           LOC=&quot;P95&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(57)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(9)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(9)           LOC=&quot;P95&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(57)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(57)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(9)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(10)          LOC=&quot;P62&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(58)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(10)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(10)          LOC=&quot;P62&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(58)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(58)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(10)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(11)          LOC=&quot;P59&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(59)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(11)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(11)          LOC=&quot;P59&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(59)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(59)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(11)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(12)          LOC=&quot;P57&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(60)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(12)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(12)          LOC=&quot;P57&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(60)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(60)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(12)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(13)          LOC=&quot;P55&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(61)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(13)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(13)          LOC=&quot;P55&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(61)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(61)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(13)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(14)          LOC=&quot;P50&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(62)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(14)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(14)          LOC=&quot;P50&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(62)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(62)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(14)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET B(15)          LOC=&quot;P47&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(63)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(15)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET B(15)          LOC=&quot;P47&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(63)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(63)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">B(15)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(0)           LOC=&quot;P114&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(64)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(0)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(0)           LOC=&quot;P114&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(64)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(64)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(0)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(1)           LOC=&quot;P115&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(65)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(1)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(1)           LOC=&quot;P115&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(65)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(65)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(1)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(2)           LOC=&quot;P116&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(66)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(2)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(2)           LOC=&quot;P116&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(66)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(66)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(2)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(3)           LOC=&quot;P117&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(67)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(3)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(3)           LOC=&quot;P117&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(67)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(67)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(3)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(4)           LOC=&quot;P118&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(68)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(4)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(4)           LOC=&quot;P118&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(68)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(68)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(4)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(5)           LOC=&quot;P119&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(69)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(5)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(5)           LOC=&quot;P119&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(69)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(69)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(5)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(6)           LOC=&quot;P120&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(70)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(6)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(6)           LOC=&quot;P120&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(70)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(70)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(6)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(7)           LOC=&quot;P121&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(71)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(7)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(7)           LOC=&quot;P121&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(71)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(71)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(7)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(8)           LOC=&quot;P123&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(72)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(8)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(8)           LOC=&quot;P123&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(72)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(72)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(8)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(9)           LOC=&quot;P124&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(73)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(9)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(9)           LOC=&quot;P124&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(73)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(73)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(9)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(10)          LOC=&quot;P126&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(74)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(10)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(10)          LOC=&quot;P126&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(74)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(74)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(10)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(11)          LOC=&quot;P127&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(75)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(11)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(11)          LOC=&quot;P127&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(75)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(75)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(11)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(12)          LOC=&quot;P131&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(76)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(12)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(12)          LOC=&quot;P131&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(76)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(76)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(12)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(13)          LOC=&quot;P132&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(77)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(13)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(13)          LOC=&quot;P132&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(77)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(77)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(13)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(14)          LOC=&quot;P133&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(78)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(14)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(14)          LOC=&quot;P133&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(78)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(78)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(14)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET C(15)          LOC=&quot;P134&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(79)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(15)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET C(15)          LOC=&quot;P134&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(79)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(79)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">C(15)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(0)  LOC=&quot;P140&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(80)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(0)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(0)  LOC=&quot;P140&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(80)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(80)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(0)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(1)  LOC=&quot;P139&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(81)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(1)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(1)  LOC=&quot;P139&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(81)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(81)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(1)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(2)  LOC=&quot;P138&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(82)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(2)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(2)  LOC=&quot;P138&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(82)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(82)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(2)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(3)  LOC=&quot;P137&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(83)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(3)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(3)  LOC=&quot;P137&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(83)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(83)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(3)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(4)  LOC=&quot;P46&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(84)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(4)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(4)  LOC=&quot;P46&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(84)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(84)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(4)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(5)  LOC=&quot;P45&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(85)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(5)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(5)  LOC=&quot;P45&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(85)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(85)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(5)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(6)  LOC=&quot;P44&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(86)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(6)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(6)  LOC=&quot;P44&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(86)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(86)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(6)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(7)  LOC=&quot;P43&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(87)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(7)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(7)  LOC=&quot;P43&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(87)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(87)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(7)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(8)  LOC=&quot;P41&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(88)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(8)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(8)  LOC=&quot;P41&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(88)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(88)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(8)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(9)  LOC=&quot;P40&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(89)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(9)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(9)  LOC=&quot;P40&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(89)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(89)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(9)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(10) LOC=&quot;P141&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(90)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(10)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(10) LOC=&quot;P141&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(90)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(90)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(10)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(11) LOC=&quot;P35&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(91)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(11)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(11) LOC=&quot;P35&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(91)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(91)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(11)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_ADDR(12) LOC=&quot;P34&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(92)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(12)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_ADDR(12) LOC=&quot;P34&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(92)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(92)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_ADDR(12)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(0)  LOC=&quot;P9&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(93)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(0)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(0)  LOC=&quot;P9&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(93)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(93)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(0)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(1)  LOC=&quot;P10&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(94)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(1)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(1)  LOC=&quot;P10&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(94)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(94)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(1)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(2)  LOC=&quot;P11&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(95)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(2)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(2)  LOC=&quot;P11&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(95)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(95)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(2)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(3)  LOC=&quot;P12&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(96)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(3)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(3)  LOC=&quot;P12&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(96)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(96)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(3)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(4)  LOC=&quot;P14&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(97)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(4)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(4)  LOC=&quot;P14&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(97)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(97)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(4)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(5)  LOC=&quot;P15&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(98)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(5)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(5)  LOC=&quot;P15&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(98)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(98)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(5)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(6)  LOC=&quot;P16&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(99)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(6)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(6)  LOC=&quot;P16&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(99)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(99)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(6)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(7)  LOC=&quot;P8&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(100)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(7)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(7)  LOC=&quot;P8&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(100)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(100)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(7)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(8)  LOC=&quot;P21&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(101)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(8)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(8)  LOC=&quot;P21&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(101)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(101)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(8)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(9)  LOC=&quot;P22&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(102)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(9)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(9)  LOC=&quot;P22&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(102)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(102)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(9)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(10) LOC=&quot;P23&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(103)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(10)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(10) LOC=&quot;P23&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(103)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(103)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(10)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(11) LOC=&quot;P24&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(104)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(11)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(11) LOC=&quot;P24&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(104)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(104)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(11)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(12) LOC=&quot;P26&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(105)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(12)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(12) LOC=&quot;P26&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(105)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(105)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(12)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(13) LOC=&quot;P27&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(106)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(13)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(13) LOC=&quot;P27&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(106)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(106)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(13)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(14) LOC=&quot;P29&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(107)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(14)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(14) LOC=&quot;P29&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(107)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(107)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(14)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DATA(15) LOC=&quot;P30&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(108)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(15)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DATA(15) LOC=&quot;P30&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(108)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(108)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DATA(15)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DQML     LOC=&quot;P7&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(109)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DQML</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DQML     LOC=&quot;P7&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(109)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(109)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DQML</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_DQMH     LOC=&quot;P17&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(110)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DQMH</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_DQMH     LOC=&quot;P17&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(110)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(110)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_DQMH</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_BA(0)    LOC=&quot;P143&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(111)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_BA(0)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_BA(0)    LOC=&quot;P143&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(111)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(111)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_BA(0)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_BA(1)    LOC=&quot;P142&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(112)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_BA(1)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_BA(1)    LOC=&quot;P142&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(112)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(112)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_BA(1)</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_nWE      LOC=&quot;P6&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(113)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_nWE</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_nWE      LOC=&quot;P6&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(113)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(113)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_nWE</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_nCAS     LOC=&quot;P5&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(114)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_nCAS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_nCAS     LOC=&quot;P5&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(114)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(114)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_nCAS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_nRAS     LOC=&quot;P2&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(115)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_nRAS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_nRAS     LOC=&quot;P2&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(115)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(115)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_nRAS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_CS       LOC=&quot;P1&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(116)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_CS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_CS       LOC=&quot;P1&quot;   |&gt; [BPC3011-Papilio_Pro-general.ucf(116)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(116)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_CS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_CLK      LOC=&quot;P32&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(117)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_CLK</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_CLK      LOC=&quot;P32&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(117)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(117)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_CLK</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET SDRAM_CKE      LOC=&quot;P33&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(118)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_CKE</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET SDRAM_CKE      LOC=&quot;P33&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(118)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL;&gt; [BPC3011-Papilio_Pro-general.ucf(118)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">SDRAM_CKE</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET JTAG_TMS       LOC=&quot;P107&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(120)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TMS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET JTAG_TMS       LOC=&quot;P107&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(120)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL |&gt; [BPC3011-Papilio_Pro-general.ucf(120)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TMS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;DRIVE=8 |&gt; [BPC3011-Papilio_Pro-general.ucf(120)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TMS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;SLEW=FAST;&gt; [BPC3011-Papilio_Pro-general.ucf(120)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TMS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET JTAG_TCK       LOC=&quot;P109&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(121)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TCK</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET JTAG_TCK       LOC=&quot;P109&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(121)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL |&gt; [BPC3011-Papilio_Pro-general.ucf(121)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TCK</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;DRIVE=8 |&gt; [BPC3011-Papilio_Pro-general.ucf(121)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TCK</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;SLEW=FAST;&gt; [BPC3011-Papilio_Pro-general.ucf(121)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TCK</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET JTAG_TDI       LOC=&quot;P110&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(122)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TDI</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET JTAG_TDI       LOC=&quot;P110&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(122)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL |&gt; [BPC3011-Papilio_Pro-general.ucf(122)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TDI</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;DRIVE=8 |&gt; [BPC3011-Papilio_Pro-general.ucf(122)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TDI</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;SLEW=FAST;&gt; [BPC3011-Papilio_Pro-general.ucf(122)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TDI</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET JTAG_TDO       LOC=&quot;P106&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(123)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TDO</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET JTAG_TDO       LOC=&quot;P106&quot; |&gt; [BPC3011-Papilio_Pro-general.ucf(123)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL |&gt; [BPC3011-Papilio_Pro-general.ucf(123)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TDO</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;DRIVE=8 |&gt; [BPC3011-Papilio_Pro-general.ucf(123)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TDO</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;SLEW=FAST;&gt; [BPC3011-Papilio_Pro-general.ucf(123)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">JTAG_TDO</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET FLASH_CS       LOC=&quot;P38&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(124)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">FLASH_CS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET FLASH_CS       LOC=&quot;P38&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(124)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL |&gt; [BPC3011-Papilio_Pro-general.ucf(124)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">FLASH_CS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;DRIVE=8 |&gt; [BPC3011-Papilio_Pro-general.ucf(124)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">FLASH_CS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;SLEW=FAST;&gt; [BPC3011-Papilio_Pro-general.ucf(124)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">FLASH_CS</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET FLASH_CK       LOC=&quot;P70&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(125)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">FLASH_CK</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET FLASH_CK       LOC=&quot;P70&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(125)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL |&gt; [BPC3011-Papilio_Pro-general.ucf(125)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">FLASH_CK</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;DRIVE=8 |&gt; [BPC3011-Papilio_Pro-general.ucf(125)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">FLASH_CK</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;SLEW=FAST;&gt; [BPC3011-Papilio_Pro-general.ucf(125)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">FLASH_CK</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;NET FLASH_SI       LOC=&quot;P64&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(126)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">FLASH_SI</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET FLASH_SI       LOC=&quot;P64&quot;  |&gt; [BPC3011-Papilio_Pro-general.ucf(126)]&apos; could not be found and so the Locate constraint will be removed.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD=LVTTL |&gt; [BPC3011-Papilio_Pro-general.ucf(126)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">FLASH_SI</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;DRIVE=8 |&gt; [BPC3011-Papilio_Pro-general.ucf(126)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">FLASH_SI</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="59" delta="old" >Constraint <arg fmt="%s" index="1">&lt;SLEW=FAST;&gt; [BPC3011-Papilio_Pro-general.ucf(126)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">FLASH_SI</arg>&quot; not found.  Please verify that:
+1. The specified design element actually exists in the original design.
+2. The specified object is spelled correctly in the constraint source file.
+</msg>
+
+<msg type="info" file="ConstraintSystem" num="0" >The Period constraint &lt;PERIOD=31.25ns;&gt; [BPC3011-Papilio_Pro-general.ucf(29)], is specified using the Net Period method which is not recommended. Please use the Timespec PERIOD method.
+</msg>
+
+</messages>
+
diff --git a/_xmsgs/par.xmsgs b/_xmsgs/par.xmsgs
new file mode 100644
index 0000000..f84336a
--- /dev/null
+++ b/_xmsgs/par.xmsgs
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+</messages>
+
diff --git a/_xmsgs/trce.xmsgs b/_xmsgs/trce.xmsgs
new file mode 100644
index 0000000..b8e4b55
--- /dev/null
+++ b/_xmsgs/trce.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
+
+<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
+
+<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
+
+</messages>
+
diff --git a/_xmsgs/xdl.xmsgs b/_xmsgs/xdl.xmsgs
new file mode 100644
index 0000000..2950d90
--- /dev/null
+++ b/_xmsgs/xdl.xmsgs
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="XDL" num="213" delta="new" >The resulting xdl output will not have LUT equation strings or RAM INIT strings.
+</msg>
+
+</messages>
+
diff --git a/_xmsgs/xst.xmsgs b/_xmsgs/xst.xmsgs
index e32e993..8e4df2b 100644
--- a/_xmsgs/xst.xmsgs
+++ b/_xmsgs/xst.xmsgs
@@ -5,7 +5,13 @@
      behavior or data corruption.  It is strongly advised that
      users do not edit the contents of this file. -->
 <messages>
-<msg type="error" file="Xst" num="0" delta="new" ><arg fmt="%s" index="1">&quot;led.v&quot; line 21: </arg>Module &lt;<arg fmt="%s" index="2">led</arg>&gt; has no port.
+<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">count_26</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">led</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">count_24</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">led</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">count_25</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">led</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
 </msg>
 
 </messages>
diff --git a/a.out b/a.out
new file mode 100755
index 0000000..cfc9082
--- /dev/null
+++ b/a.out
@@ -0,0 +1,49 @@
+#! /usr/bin/vvp
+:ivl_version "10.1 (stable)" "(v10_1)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x13edb40 .scope module, "led" "led" 2 21;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "CLK"
+    .port_info 1 /OUTPUT 1 "LED1"
+o0x7f70a6ad5018 .functor BUFZ 1, C4<z>; HiZ drive
+v0x13edd20_0 .net "CLK", 0 0, o0x7f70a6ad5018;  0 drivers
+v0x14450f0_0 .var "LED1", 0 0;
+v0x14451b0_0 .var "count", 26 0;
+E_0x13ee450 .event posedge, v0x13edd20_0;
+    .scope S_0x13edb40;
+T_0 ;
+    %pushi/vec4 16000000, 0, 27;
+    %store/vec4 v0x14451b0_0, 0, 27;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x14450f0_0, 0, 1;
+    %end;
+    .thread T_0;
+    .scope S_0x13edb40;
+T_1 ;
+    %wait E_0x13ee450;
+    %load/vec4 v0x14451b0_0;
+    %cmpi/e 0, 0, 27;
+    %jmp/0xz  T_1.0, 4;
+    %load/vec4 v0x14450f0_0;
+    %inv;
+    %assign/vec4 v0x14450f0_0, 0;
+    %pushi/vec4 16000000, 0, 27;
+    %assign/vec4 v0x14451b0_0, 0;
+    %jmp T_1.1;
+T_1.0 ;
+    %load/vec4 v0x14451b0_0;
+    %subi 1, 0, 27;
+    %assign/vec4 v0x14451b0_0, 0;
+T_1.1 ;
+    %jmp T_1;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    "led.v";
diff --git a/iseconfig/FPGA-led-lights.projectmgr b/iseconfig/FPGA-led-lights.projectmgr
index 1bf392f..4cff5f6 100644
--- a/iseconfig/FPGA-led-lights.projectmgr
+++ b/iseconfig/FPGA-led-lights.projectmgr
@@ -27,7 +27,7 @@
       </SelectedItems>
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f1000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f10000000100000000</ViewHeaderState>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000185000000010000000100000000000000000000000064ffffffff000000810000000000000001000001850000000100000000</ViewHeaderState>
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
       <CurrentItem/>
    </ItemView>
@@ -47,7 +47,9 @@
          <ClosedNodesVersion>1</ClosedNodesVersion>
          <ClosedNode>work</ClosedNode>
       </ClosedNodes>
-      <SelectedItems/>
+      <SelectedItems>
+         <SelectedItem>work</SelectedItem>
+      </SelectedItems>
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000125000000010001000100000000000000000000000064ffffffff000000810000000000000001000001250000000100000000</ViewHeaderState>
@@ -60,31 +62,32 @@
          <ClosedNode>Configure Target Device</ClosedNode>
          <ClosedNode>Design Utilities</ClosedNode>
          <ClosedNode>Implement Design</ClosedNode>
+         <ClosedNode>Implement Design/Map</ClosedNode>
+         <ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
+         <ClosedNode>Implement Design/Translate</ClosedNode>
          <ClosedNode>Synthesize - XST</ClosedNode>
-         <ClosedNode>User Constraints</ClosedNode>
       </ClosedNodes>
       <SelectedItems>
          <SelectedItem></SelectedItem>
       </SelectedItems>
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f1000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f10000000100000000</ViewHeaderState>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000185000000010000000100000000000000000000000064ffffffff000000810000000000000001000001850000000100000000</ViewHeaderState>
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
       <CurrentItem></CurrentItem>
    </ItemView>
    <ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
       <ClosedNodes>
          <ClosedNodesVersion>1</ClosedNodesVersion>
-         <ClosedNode>User Constraints</ClosedNode>
       </ClosedNodes>
       <SelectedItems>
-         <SelectedItem></SelectedItem>
+         <SelectedItem/>
       </SelectedItems>
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f1000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f10000000100000000</ViewHeaderState>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000185000000010000000100000000000000000000000064ffffffff000000810000000000000001000001850000000100000000</ViewHeaderState>
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem></CurrentItem>
+      <CurrentItem/>
    </ItemView>
    <SourceProcessView>000000ff0000000000000002000001510000012001000000060100000002</SourceProcessView>
    <CurrentView>Implementation</CurrentView>
diff --git a/iseconfig/led.xreport b/iseconfig/led.xreport
index 9fc68e7..771a349 100644
--- a/iseconfig/led.xreport
+++ b/iseconfig/led.xreport
@@ -1,9 +1,9 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2017-02-20T16:00:35</DateModified>
+  <DateModified>2017-02-21T23:44:54</DateModified>
   <ModuleName>led</ModuleName>
-  <SummaryTimeStamp>Unknown</SummaryTimeStamp>
+  <SummaryTimeStamp>2017-02-21T22:10:44</SummaryTimeStamp>
   <SavedFilePath>/home/yannherklotz/Github/FPGA-led-lights/iseconfig/led.xreport</SavedFilePath>
   <ImplementationReportsDirectory>/home/yannherklotz/Github/FPGA-led-lights/</ImplementationReportsDirectory>
   <DateInitialized>2017-02-19T23:10:42</DateInitialized>
diff --git a/led b/led
new file mode 100755
index 0000000..dc3b1a4
--- /dev/null
+++ b/led
@@ -0,0 +1,49 @@
+#! /usr/bin/vvp
+:ivl_version "10.1 (stable)" "(v10_1)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x2024b40 .scope module, "led" "led" 2 21;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "CLK"
+    .port_info 1 /OUTPUT 1 "LED1"
+o0x7fb1922e4018 .functor BUFZ 1, C4<z>; HiZ drive
+v0x2024d20_0 .net "CLK", 0 0, o0x7fb1922e4018;  0 drivers
+v0x207c0f0_0 .var "LED1", 0 0;
+v0x207c1b0_0 .var "count", 26 0;
+E_0x2025450 .event posedge, v0x2024d20_0;
+    .scope S_0x2024b40;
+T_0 ;
+    %pushi/vec4 16000000, 0, 27;
+    %store/vec4 v0x207c1b0_0, 0, 27;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x207c0f0_0, 0, 1;
+    %end;
+    .thread T_0;
+    .scope S_0x2024b40;
+T_1 ;
+    %wait E_0x2025450;
+    %load/vec4 v0x207c1b0_0;
+    %cmpi/e 0, 0, 27;
+    %jmp/0xz  T_1.0, 4;
+    %load/vec4 v0x207c0f0_0;
+    %inv;
+    %assign/vec4 v0x207c0f0_0, 0;
+    %pushi/vec4 16000000, 0, 27;
+    %assign/vec4 v0x207c1b0_0, 0;
+    %jmp T_1.1;
+T_1.0 ;
+    %load/vec4 v0x207c1b0_0;
+    %subi 1, 0, 27;
+    %assign/vec4 v0x207c1b0_0, 0;
+T_1.1 ;
+    %jmp T_1;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    "led.v";
diff --git a/led.bgn b/led.bgn
new file mode 100644
index 0000000..c7f61ae
--- /dev/null
+++ b/led.bgn
@@ -0,0 +1,134 @@
+Release 14.7 - Bitgen P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Loading device for application Rf_Device from file '6slx9.nph' in environment
+/opt/Xilinx/14.7/ISE_DS/ISE/.
+   "led" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
+Opened constraints file led.pcf.
+
+Tue Feb 21 22:17:07 2017
+
+/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 led.ncd 
+
+Summary of Bitgen Options:
++----------------------+----------------------+
+| Option Name          | Current Setting      |
++----------------------+----------------------+
+| Compress             | (Not Specified)*     |
++----------------------+----------------------+
+| Readback             | (Not Specified)*     |
++----------------------+----------------------+
+| CRC                  | Enable**             |
++----------------------+----------------------+
+| DebugBitstream       | No**                 |
++----------------------+----------------------+
+| ConfigRate           | 2**                  |
++----------------------+----------------------+
+| StartupClk           | Cclk**               |
++----------------------+----------------------+
+| DonePin              | Pullup*              |
++----------------------+----------------------+
+| ProgPin              | Pullup**             |
++----------------------+----------------------+
+| TckPin               | Pullup**             |
++----------------------+----------------------+
+| TdiPin               | Pullup**             |
++----------------------+----------------------+
+| TdoPin               | Pullup**             |
++----------------------+----------------------+
+| TmsPin               | Pullup**             |
++----------------------+----------------------+
+| UnusedPin            | Pulldown**           |
++----------------------+----------------------+
+| GWE_cycle            | 6**                  |
++----------------------+----------------------+
+| GTS_cycle            | 5**                  |
++----------------------+----------------------+
+| LCK_cycle            | NoWait**             |
++----------------------+----------------------+
+| DONE_cycle           | 4**                  |
++----------------------+----------------------+
+| Persist              | No*                  |
++----------------------+----------------------+
+| DriveDone            | No**                 |
++----------------------+----------------------+
+| DonePipe             | Yes                  |
++----------------------+----------------------+
+| Security             | None**               |
++----------------------+----------------------+
+| UserID               | 0xFFFFFFFF**         |
++----------------------+----------------------+
+| ActiveReconfig       | No*                  |
++----------------------+----------------------+
+| Partial              | (Not Specified)*     |
++----------------------+----------------------+
+| Encrypt              | No*                  |
++----------------------+----------------------+
+| Key0                 | pick*                |
++----------------------+----------------------+
+| StartCBC             | pick*                |
++----------------------+----------------------+
+| KeyFile              | (Not Specified)*     |
++----------------------+----------------------+
+| drive_awake          | No**                 |
++----------------------+----------------------+
+| Reset_on_err         | No**                 |
++----------------------+----------------------+
+| suspend_filter       | Yes*                 |
++----------------------+----------------------+
+| en_sw_gsr            | No**                 |
++----------------------+----------------------+
+| en_suspend           | No*                  |
++----------------------+----------------------+
+| sw_clk               | Startupclk**         |
++----------------------+----------------------+
+| sw_gwe_cycle         | 5**                  |
++----------------------+----------------------+
+| sw_gts_cycle         | 4**                  |
++----------------------+----------------------+
+| multipin_wakeup      | No**                 |
++----------------------+----------------------+
+| wakeup_mask          | 0x00*                |
++----------------------+----------------------+
+| ExtMasterCclk_en     | No**                 |
++----------------------+----------------------+
+| ExtMasterCclk_divide | 1*                   |
++----------------------+----------------------+
+| CrcCoverage          | No*                  |
++----------------------+----------------------+
+| glutmask             | Yes*                 |
++----------------------+----------------------+
+| next_config_addr     | 0x00000000*          |
++----------------------+----------------------+
+| next_config_new_mode | No*                  |
++----------------------+----------------------+
+| next_config_boot_mode | 001*                 |
++----------------------+----------------------+
+| next_config_register_write | Enable*              |
++----------------------+----------------------+
+| next_config_reboot   | Enable*              |
++----------------------+----------------------+
+| golden_config_addr   | 0x00000000*          |
++----------------------+----------------------+
+| failsafe_user        | 0x0000*              |
++----------------------+----------------------+
+| TIMER_CFG            | 0xFFFF               |
++----------------------+----------------------+
+| spi_buswidth         | 1**                  |
++----------------------+----------------------+
+| TimeStamp            | Default*             |
++----------------------+----------------------+
+| IEEE1532             | No*                  |
++----------------------+----------------------+
+| Binary               | No**                 |
++----------------------+----------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+There were 0 CONFIG constraint(s) processed from led.pcf.
+
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Creating bit map...
+Saving bit stream in "led.bit".
+Bitstream generation is complete.
diff --git a/led.bit b/led.bit
new file mode 100644
index 0000000..eca8bc9
--- /dev/null
+++ b/led.bit
diff --git a/led.bld b/led.bld
new file mode 100644
index 0000000..c59934e
--- /dev/null
+++ b/led.bld
@@ -0,0 +1,1657 @@
+Release 14.7 ngdbuild P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
+ise -dd _ngo -aul -nt timestamp -uc BPC3011-Papilio_Pro-general.ucf -p
+xc6slx9-tqg144-2 led.ngc led.ngd
+
+Reading NGO file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" ...
+Gathering constraint information from source properties...
+Done.
+
+Annotating constraints to design from ucf file "BPC3011-Papilio_Pro-general.ucf"
+...
+Resolving constraint associations...
+Checking Constraint Associations...
+INFO:ConstraintSystem:59 - Constraint <NET RX             LOC="P101" |>
+   [BPC3011-Papilio_Pro-general.ucf(30)]: NET "RX" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET RX             LOC="P101" |> [BPC3011-Papilio_Pro-general.ucf(30)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL |>
+   [BPC3011-Papilio_Pro-general.ucf(30)]: NET "RX" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <DRIVE=8 |>
+   [BPC3011-Papilio_Pro-general.ucf(30)]: NET "RX" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <SLEW=FAST;>
+   [BPC3011-Papilio_Pro-general.ucf(30)]: NET "RX" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(0)           LOC="P48"  |>
+   [BPC3011-Papilio_Pro-general.ucf(32)]: NET "A(0)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(0)           LOC="P48"  |> [BPC3011-Papilio_Pro-general.ucf(32)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(32)]: NET "A(0)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(1)           LOC="P51"  |>
+   [BPC3011-Papilio_Pro-general.ucf(33)]: NET "A(1)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(1)           LOC="P51"  |> [BPC3011-Papilio_Pro-general.ucf(33)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(33)]: NET "A(1)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(2)           LOC="P56"  |>
+   [BPC3011-Papilio_Pro-general.ucf(34)]: NET "A(2)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(2)           LOC="P56"  |> [BPC3011-Papilio_Pro-general.ucf(34)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(34)]: NET "A(2)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(3)           LOC="P58"  |>
+   [BPC3011-Papilio_Pro-general.ucf(35)]: NET "A(3)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(3)           LOC="P58"  |> [BPC3011-Papilio_Pro-general.ucf(35)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(35)]: NET "A(3)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(4)           LOC="P61"  |>
+   [BPC3011-Papilio_Pro-general.ucf(36)]: NET "A(4)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(4)           LOC="P61"  |> [BPC3011-Papilio_Pro-general.ucf(36)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(36)]: NET "A(4)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(5)           LOC="P66"  |>
+   [BPC3011-Papilio_Pro-general.ucf(37)]: NET "A(5)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(5)           LOC="P66"  |> [BPC3011-Papilio_Pro-general.ucf(37)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(37)]: NET "A(5)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(6)           LOC="P67"  |>
+   [BPC3011-Papilio_Pro-general.ucf(38)]: NET "A(6)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(6)           LOC="P67"  |> [BPC3011-Papilio_Pro-general.ucf(38)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(38)]: NET "A(6)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(7)           LOC="P75"  |>
+   [BPC3011-Papilio_Pro-general.ucf(39)]: NET "A(7)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(7)           LOC="P75"  |> [BPC3011-Papilio_Pro-general.ucf(39)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(39)]: NET "A(7)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(8)           LOC="P79"  |>
+   [BPC3011-Papilio_Pro-general.ucf(40)]: NET "A(8)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(8)           LOC="P79"  |> [BPC3011-Papilio_Pro-general.ucf(40)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(40)]: NET "A(8)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(9)           LOC="P81"  |>
+   [BPC3011-Papilio_Pro-general.ucf(41)]: NET "A(9)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(9)           LOC="P81"  |> [BPC3011-Papilio_Pro-general.ucf(41)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(41)]: NET "A(9)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(10)          LOC="P83"  |>
+   [BPC3011-Papilio_Pro-general.ucf(42)]: NET "A(10)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(10)          LOC="P83"  |> [BPC3011-Papilio_Pro-general.ucf(42)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(42)]: NET "A(10)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(11)          LOC="P85"  |>
+   [BPC3011-Papilio_Pro-general.ucf(43)]: NET "A(11)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(11)          LOC="P85"  |> [BPC3011-Papilio_Pro-general.ucf(43)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(43)]: NET "A(11)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(12)          LOC="P88"  |>
+   [BPC3011-Papilio_Pro-general.ucf(44)]: NET "A(12)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(12)          LOC="P88"  |> [BPC3011-Papilio_Pro-general.ucf(44)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(44)]: NET "A(12)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(13)          LOC="P93"  |>
+   [BPC3011-Papilio_Pro-general.ucf(45)]: NET "A(13)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(13)          LOC="P93"  |> [BPC3011-Papilio_Pro-general.ucf(45)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(45)]: NET "A(13)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(14)          LOC="P98"  |>
+   [BPC3011-Papilio_Pro-general.ucf(46)]: NET "A(14)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(14)          LOC="P98"  |> [BPC3011-Papilio_Pro-general.ucf(46)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(46)]: NET "A(14)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET A(15)          LOC="P100" |>
+   [BPC3011-Papilio_Pro-general.ucf(47)]: NET "A(15)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET A(15)          LOC="P100" |> [BPC3011-Papilio_Pro-general.ucf(47)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(47)]: NET "A(15)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(0)           LOC="P99"  |>
+   [BPC3011-Papilio_Pro-general.ucf(48)]: NET "B(0)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(0)           LOC="P99"  |> [BPC3011-Papilio_Pro-general.ucf(48)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(48)]: NET "B(0)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(1)           LOC="P97"  |>
+   [BPC3011-Papilio_Pro-general.ucf(49)]: NET "B(1)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(1)           LOC="P97"  |> [BPC3011-Papilio_Pro-general.ucf(49)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(49)]: NET "B(1)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(2)           LOC="P92"  |>
+   [BPC3011-Papilio_Pro-general.ucf(50)]: NET "B(2)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(2)           LOC="P92"  |> [BPC3011-Papilio_Pro-general.ucf(50)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(50)]: NET "B(2)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(3)           LOC="P87"  |>
+   [BPC3011-Papilio_Pro-general.ucf(51)]: NET "B(3)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(3)           LOC="P87"  |> [BPC3011-Papilio_Pro-general.ucf(51)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(51)]: NET "B(3)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(4)           LOC="P84"  |>
+   [BPC3011-Papilio_Pro-general.ucf(52)]: NET "B(4)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(4)           LOC="P84"  |> [BPC3011-Papilio_Pro-general.ucf(52)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(52)]: NET "B(4)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(5)           LOC="P82"  |>
+   [BPC3011-Papilio_Pro-general.ucf(53)]: NET "B(5)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(5)           LOC="P82"  |> [BPC3011-Papilio_Pro-general.ucf(53)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(53)]: NET "B(5)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(6)           LOC="P80"  |>
+   [BPC3011-Papilio_Pro-general.ucf(54)]: NET "B(6)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(6)           LOC="P80"  |> [BPC3011-Papilio_Pro-general.ucf(54)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(54)]: NET "B(6)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(7)           LOC="P78"  |>
+   [BPC3011-Papilio_Pro-general.ucf(55)]: NET "B(7)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(7)           LOC="P78"  |> [BPC3011-Papilio_Pro-general.ucf(55)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(55)]: NET "B(7)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(8)           LOC="P74"  |>
+   [BPC3011-Papilio_Pro-general.ucf(56)]: NET "B(8)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(8)           LOC="P74"  |> [BPC3011-Papilio_Pro-general.ucf(56)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(56)]: NET "B(8)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(9)           LOC="P95"  |>
+   [BPC3011-Papilio_Pro-general.ucf(57)]: NET "B(9)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(9)           LOC="P95"  |> [BPC3011-Papilio_Pro-general.ucf(57)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(57)]: NET "B(9)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(10)          LOC="P62"  |>
+   [BPC3011-Papilio_Pro-general.ucf(58)]: NET "B(10)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(10)          LOC="P62"  |> [BPC3011-Papilio_Pro-general.ucf(58)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(58)]: NET "B(10)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(11)          LOC="P59"  |>
+   [BPC3011-Papilio_Pro-general.ucf(59)]: NET "B(11)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(11)          LOC="P59"  |> [BPC3011-Papilio_Pro-general.ucf(59)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(59)]: NET "B(11)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(12)          LOC="P57"  |>
+   [BPC3011-Papilio_Pro-general.ucf(60)]: NET "B(12)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(12)          LOC="P57"  |> [BPC3011-Papilio_Pro-general.ucf(60)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(60)]: NET "B(12)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(13)          LOC="P55"  |>
+   [BPC3011-Papilio_Pro-general.ucf(61)]: NET "B(13)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(13)          LOC="P55"  |> [BPC3011-Papilio_Pro-general.ucf(61)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(61)]: NET "B(13)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(14)          LOC="P50"  |>
+   [BPC3011-Papilio_Pro-general.ucf(62)]: NET "B(14)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(14)          LOC="P50"  |> [BPC3011-Papilio_Pro-general.ucf(62)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(62)]: NET "B(14)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET B(15)          LOC="P47"  |>
+   [BPC3011-Papilio_Pro-general.ucf(63)]: NET "B(15)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET B(15)          LOC="P47"  |> [BPC3011-Papilio_Pro-general.ucf(63)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(63)]: NET "B(15)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(0)           LOC="P114" |>
+   [BPC3011-Papilio_Pro-general.ucf(64)]: NET "C(0)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(0)           LOC="P114" |> [BPC3011-Papilio_Pro-general.ucf(64)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(64)]: NET "C(0)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(1)           LOC="P115" |>
+   [BPC3011-Papilio_Pro-general.ucf(65)]: NET "C(1)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(1)           LOC="P115" |> [BPC3011-Papilio_Pro-general.ucf(65)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(65)]: NET "C(1)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(2)           LOC="P116" |>
+   [BPC3011-Papilio_Pro-general.ucf(66)]: NET "C(2)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(2)           LOC="P116" |> [BPC3011-Papilio_Pro-general.ucf(66)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(66)]: NET "C(2)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(3)           LOC="P117" |>
+   [BPC3011-Papilio_Pro-general.ucf(67)]: NET "C(3)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(3)           LOC="P117" |> [BPC3011-Papilio_Pro-general.ucf(67)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(67)]: NET "C(3)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(4)           LOC="P118" |>
+   [BPC3011-Papilio_Pro-general.ucf(68)]: NET "C(4)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(4)           LOC="P118" |> [BPC3011-Papilio_Pro-general.ucf(68)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(68)]: NET "C(4)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(5)           LOC="P119" |>
+   [BPC3011-Papilio_Pro-general.ucf(69)]: NET "C(5)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(5)           LOC="P119" |> [BPC3011-Papilio_Pro-general.ucf(69)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(69)]: NET "C(5)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(6)           LOC="P120" |>
+   [BPC3011-Papilio_Pro-general.ucf(70)]: NET "C(6)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(6)           LOC="P120" |> [BPC3011-Papilio_Pro-general.ucf(70)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(70)]: NET "C(6)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(7)           LOC="P121" |>
+   [BPC3011-Papilio_Pro-general.ucf(71)]: NET "C(7)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(7)           LOC="P121" |> [BPC3011-Papilio_Pro-general.ucf(71)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(71)]: NET "C(7)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(8)           LOC="P123" |>
+   [BPC3011-Papilio_Pro-general.ucf(72)]: NET "C(8)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(8)           LOC="P123" |> [BPC3011-Papilio_Pro-general.ucf(72)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(72)]: NET "C(8)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(9)           LOC="P124" |>
+   [BPC3011-Papilio_Pro-general.ucf(73)]: NET "C(9)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(9)           LOC="P124" |> [BPC3011-Papilio_Pro-general.ucf(73)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(73)]: NET "C(9)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(10)          LOC="P126" |>
+   [BPC3011-Papilio_Pro-general.ucf(74)]: NET "C(10)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(10)          LOC="P126" |> [BPC3011-Papilio_Pro-general.ucf(74)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(74)]: NET "C(10)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(11)          LOC="P127" |>
+   [BPC3011-Papilio_Pro-general.ucf(75)]: NET "C(11)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(11)          LOC="P127" |> [BPC3011-Papilio_Pro-general.ucf(75)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(75)]: NET "C(11)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(12)          LOC="P131" |>
+   [BPC3011-Papilio_Pro-general.ucf(76)]: NET "C(12)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(12)          LOC="P131" |> [BPC3011-Papilio_Pro-general.ucf(76)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(76)]: NET "C(12)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(13)          LOC="P132" |>
+   [BPC3011-Papilio_Pro-general.ucf(77)]: NET "C(13)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(13)          LOC="P132" |> [BPC3011-Papilio_Pro-general.ucf(77)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(77)]: NET "C(13)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(14)          LOC="P133" |>
+   [BPC3011-Papilio_Pro-general.ucf(78)]: NET "C(14)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(14)          LOC="P133" |> [BPC3011-Papilio_Pro-general.ucf(78)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(78)]: NET "C(14)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET C(15)          LOC="P134" |>
+   [BPC3011-Papilio_Pro-general.ucf(79)]: NET "C(15)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET C(15)          LOC="P134" |> [BPC3011-Papilio_Pro-general.ucf(79)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(79)]: NET "C(15)" not found.  Please verify
+   that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(0)  LOC="P140" |>
+   [BPC3011-Papilio_Pro-general.ucf(80)]: NET "SDRAM_ADDR(0)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(0)  LOC="P140" |> [BPC3011-Papilio_Pro-general.ucf(80)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(80)]: NET "SDRAM_ADDR(0)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(1)  LOC="P139" |>
+   [BPC3011-Papilio_Pro-general.ucf(81)]: NET "SDRAM_ADDR(1)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(1)  LOC="P139" |> [BPC3011-Papilio_Pro-general.ucf(81)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(81)]: NET "SDRAM_ADDR(1)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(2)  LOC="P138" |>
+   [BPC3011-Papilio_Pro-general.ucf(82)]: NET "SDRAM_ADDR(2)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(2)  LOC="P138" |> [BPC3011-Papilio_Pro-general.ucf(82)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(82)]: NET "SDRAM_ADDR(2)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(3)  LOC="P137" |>
+   [BPC3011-Papilio_Pro-general.ucf(83)]: NET "SDRAM_ADDR(3)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(3)  LOC="P137" |> [BPC3011-Papilio_Pro-general.ucf(83)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(83)]: NET "SDRAM_ADDR(3)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(4)  LOC="P46"  |>
+   [BPC3011-Papilio_Pro-general.ucf(84)]: NET "SDRAM_ADDR(4)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(4)  LOC="P46"  |> [BPC3011-Papilio_Pro-general.ucf(84)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(84)]: NET "SDRAM_ADDR(4)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(5)  LOC="P45"  |>
+   [BPC3011-Papilio_Pro-general.ucf(85)]: NET "SDRAM_ADDR(5)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(5)  LOC="P45"  |> [BPC3011-Papilio_Pro-general.ucf(85)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(85)]: NET "SDRAM_ADDR(5)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(6)  LOC="P44"  |>
+   [BPC3011-Papilio_Pro-general.ucf(86)]: NET "SDRAM_ADDR(6)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(6)  LOC="P44"  |> [BPC3011-Papilio_Pro-general.ucf(86)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(86)]: NET "SDRAM_ADDR(6)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(7)  LOC="P43"  |>
+   [BPC3011-Papilio_Pro-general.ucf(87)]: NET "SDRAM_ADDR(7)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(7)  LOC="P43"  |> [BPC3011-Papilio_Pro-general.ucf(87)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(87)]: NET "SDRAM_ADDR(7)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(8)  LOC="P41"  |>
+   [BPC3011-Papilio_Pro-general.ucf(88)]: NET "SDRAM_ADDR(8)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(8)  LOC="P41"  |> [BPC3011-Papilio_Pro-general.ucf(88)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(88)]: NET "SDRAM_ADDR(8)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(9)  LOC="P40"  |>
+   [BPC3011-Papilio_Pro-general.ucf(89)]: NET "SDRAM_ADDR(9)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(9)  LOC="P40"  |> [BPC3011-Papilio_Pro-general.ucf(89)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(89)]: NET "SDRAM_ADDR(9)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(10) LOC="P141" |>
+   [BPC3011-Papilio_Pro-general.ucf(90)]: NET "SDRAM_ADDR(10)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(10) LOC="P141" |> [BPC3011-Papilio_Pro-general.ucf(90)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(90)]: NET "SDRAM_ADDR(10)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(11) LOC="P35"  |>
+   [BPC3011-Papilio_Pro-general.ucf(91)]: NET "SDRAM_ADDR(11)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(11) LOC="P35"  |> [BPC3011-Papilio_Pro-general.ucf(91)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(91)]: NET "SDRAM_ADDR(11)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_ADDR(12) LOC="P34"  |>
+   [BPC3011-Papilio_Pro-general.ucf(92)]: NET "SDRAM_ADDR(12)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_ADDR(12) LOC="P34"  |> [BPC3011-Papilio_Pro-general.ucf(92)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(92)]: NET "SDRAM_ADDR(12)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(0)  LOC="P9"   |>
+   [BPC3011-Papilio_Pro-general.ucf(93)]: NET "SDRAM_DATA(0)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(0)  LOC="P9"   |> [BPC3011-Papilio_Pro-general.ucf(93)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(93)]: NET "SDRAM_DATA(0)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(1)  LOC="P10"  |>
+   [BPC3011-Papilio_Pro-general.ucf(94)]: NET "SDRAM_DATA(1)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(1)  LOC="P10"  |> [BPC3011-Papilio_Pro-general.ucf(94)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(94)]: NET "SDRAM_DATA(1)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(2)  LOC="P11"  |>
+   [BPC3011-Papilio_Pro-general.ucf(95)]: NET "SDRAM_DATA(2)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(2)  LOC="P11"  |> [BPC3011-Papilio_Pro-general.ucf(95)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(95)]: NET "SDRAM_DATA(2)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(3)  LOC="P12"  |>
+   [BPC3011-Papilio_Pro-general.ucf(96)]: NET "SDRAM_DATA(3)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(3)  LOC="P12"  |> [BPC3011-Papilio_Pro-general.ucf(96)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(96)]: NET "SDRAM_DATA(3)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(4)  LOC="P14"  |>
+   [BPC3011-Papilio_Pro-general.ucf(97)]: NET "SDRAM_DATA(4)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(4)  LOC="P14"  |> [BPC3011-Papilio_Pro-general.ucf(97)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(97)]: NET "SDRAM_DATA(4)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(5)  LOC="P15"  |>
+   [BPC3011-Papilio_Pro-general.ucf(98)]: NET "SDRAM_DATA(5)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(5)  LOC="P15"  |> [BPC3011-Papilio_Pro-general.ucf(98)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(98)]: NET "SDRAM_DATA(5)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(6)  LOC="P16"  |>
+   [BPC3011-Papilio_Pro-general.ucf(99)]: NET "SDRAM_DATA(6)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(6)  LOC="P16"  |> [BPC3011-Papilio_Pro-general.ucf(99)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(99)]: NET "SDRAM_DATA(6)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(7)  LOC="P8"   |>
+   [BPC3011-Papilio_Pro-general.ucf(100)]: NET "SDRAM_DATA(7)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(7)  LOC="P8"   |> [BPC3011-Papilio_Pro-general.ucf(100)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(100)]: NET "SDRAM_DATA(7)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(8)  LOC="P21"  |>
+   [BPC3011-Papilio_Pro-general.ucf(101)]: NET "SDRAM_DATA(8)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(8)  LOC="P21"  |> [BPC3011-Papilio_Pro-general.ucf(101)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(101)]: NET "SDRAM_DATA(8)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(9)  LOC="P22"  |>
+   [BPC3011-Papilio_Pro-general.ucf(102)]: NET "SDRAM_DATA(9)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(9)  LOC="P22"  |> [BPC3011-Papilio_Pro-general.ucf(102)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(102)]: NET "SDRAM_DATA(9)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(10) LOC="P23"  |>
+   [BPC3011-Papilio_Pro-general.ucf(103)]: NET "SDRAM_DATA(10)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(10) LOC="P23"  |> [BPC3011-Papilio_Pro-general.ucf(103)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(103)]: NET "SDRAM_DATA(10)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(11) LOC="P24"  |>
+   [BPC3011-Papilio_Pro-general.ucf(104)]: NET "SDRAM_DATA(11)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(11) LOC="P24"  |> [BPC3011-Papilio_Pro-general.ucf(104)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(104)]: NET "SDRAM_DATA(11)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(12) LOC="P26"  |>
+   [BPC3011-Papilio_Pro-general.ucf(105)]: NET "SDRAM_DATA(12)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(12) LOC="P26"  |> [BPC3011-Papilio_Pro-general.ucf(105)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(105)]: NET "SDRAM_DATA(12)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(13) LOC="P27"  |>
+   [BPC3011-Papilio_Pro-general.ucf(106)]: NET "SDRAM_DATA(13)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(13) LOC="P27"  |> [BPC3011-Papilio_Pro-general.ucf(106)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(106)]: NET "SDRAM_DATA(13)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(14) LOC="P29"  |>
+   [BPC3011-Papilio_Pro-general.ucf(107)]: NET "SDRAM_DATA(14)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(14) LOC="P29"  |> [BPC3011-Papilio_Pro-general.ucf(107)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(107)]: NET "SDRAM_DATA(14)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DATA(15) LOC="P30"  |>
+   [BPC3011-Papilio_Pro-general.ucf(108)]: NET "SDRAM_DATA(15)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DATA(15) LOC="P30"  |> [BPC3011-Papilio_Pro-general.ucf(108)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(108)]: NET "SDRAM_DATA(15)" not found. 
+   Please verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DQML     LOC="P7"   |>
+   [BPC3011-Papilio_Pro-general.ucf(109)]: NET "SDRAM_DQML" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DQML     LOC="P7"   |> [BPC3011-Papilio_Pro-general.ucf(109)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(109)]: NET "SDRAM_DQML" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_DQMH     LOC="P17"  |>
+   [BPC3011-Papilio_Pro-general.ucf(110)]: NET "SDRAM_DQMH" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_DQMH     LOC="P17"  |> [BPC3011-Papilio_Pro-general.ucf(110)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(110)]: NET "SDRAM_DQMH" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_BA(0)    LOC="P143" |>
+   [BPC3011-Papilio_Pro-general.ucf(111)]: NET "SDRAM_BA(0)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_BA(0)    LOC="P143" |> [BPC3011-Papilio_Pro-general.ucf(111)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(111)]: NET "SDRAM_BA(0)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_BA(1)    LOC="P142" |>
+   [BPC3011-Papilio_Pro-general.ucf(112)]: NET "SDRAM_BA(1)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_BA(1)    LOC="P142" |> [BPC3011-Papilio_Pro-general.ucf(112)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(112)]: NET "SDRAM_BA(1)" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_nWE      LOC="P6"   |>
+   [BPC3011-Papilio_Pro-general.ucf(113)]: NET "SDRAM_nWE" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_nWE      LOC="P6"   |> [BPC3011-Papilio_Pro-general.ucf(113)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(113)]: NET "SDRAM_nWE" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_nCAS     LOC="P5"   |>
+   [BPC3011-Papilio_Pro-general.ucf(114)]: NET "SDRAM_nCAS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_nCAS     LOC="P5"   |> [BPC3011-Papilio_Pro-general.ucf(114)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(114)]: NET "SDRAM_nCAS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_nRAS     LOC="P2"   |>
+   [BPC3011-Papilio_Pro-general.ucf(115)]: NET "SDRAM_nRAS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_nRAS     LOC="P2"   |> [BPC3011-Papilio_Pro-general.ucf(115)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(115)]: NET "SDRAM_nRAS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_CS       LOC="P1"   |>
+   [BPC3011-Papilio_Pro-general.ucf(116)]: NET "SDRAM_CS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_CS       LOC="P1"   |> [BPC3011-Papilio_Pro-general.ucf(116)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(116)]: NET "SDRAM_CS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_CLK      LOC="P32"  |>
+   [BPC3011-Papilio_Pro-general.ucf(117)]: NET "SDRAM_CLK" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_CLK      LOC="P32"  |> [BPC3011-Papilio_Pro-general.ucf(117)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(117)]: NET "SDRAM_CLK" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET SDRAM_CKE      LOC="P33"  |>
+   [BPC3011-Papilio_Pro-general.ucf(118)]: NET "SDRAM_CKE" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET SDRAM_CKE      LOC="P33"  |> [BPC3011-Papilio_Pro-general.ucf(118)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL;>
+   [BPC3011-Papilio_Pro-general.ucf(118)]: NET "SDRAM_CKE" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET JTAG_TMS       LOC="P107" |>
+   [BPC3011-Papilio_Pro-general.ucf(120)]: NET "JTAG_TMS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET JTAG_TMS       LOC="P107" |> [BPC3011-Papilio_Pro-general.ucf(120)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL |>
+   [BPC3011-Papilio_Pro-general.ucf(120)]: NET "JTAG_TMS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <DRIVE=8 |>
+   [BPC3011-Papilio_Pro-general.ucf(120)]: NET "JTAG_TMS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <SLEW=FAST;>
+   [BPC3011-Papilio_Pro-general.ucf(120)]: NET "JTAG_TMS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET JTAG_TCK       LOC="P109" |>
+   [BPC3011-Papilio_Pro-general.ucf(121)]: NET "JTAG_TCK" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET JTAG_TCK       LOC="P109" |> [BPC3011-Papilio_Pro-general.ucf(121)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL |>
+   [BPC3011-Papilio_Pro-general.ucf(121)]: NET "JTAG_TCK" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <DRIVE=8 |>
+   [BPC3011-Papilio_Pro-general.ucf(121)]: NET "JTAG_TCK" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <SLEW=FAST;>
+   [BPC3011-Papilio_Pro-general.ucf(121)]: NET "JTAG_TCK" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET JTAG_TDI       LOC="P110" |>
+   [BPC3011-Papilio_Pro-general.ucf(122)]: NET "JTAG_TDI" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET JTAG_TDI       LOC="P110" |> [BPC3011-Papilio_Pro-general.ucf(122)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL |>
+   [BPC3011-Papilio_Pro-general.ucf(122)]: NET "JTAG_TDI" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <DRIVE=8 |>
+   [BPC3011-Papilio_Pro-general.ucf(122)]: NET "JTAG_TDI" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <SLEW=FAST;>
+   [BPC3011-Papilio_Pro-general.ucf(122)]: NET "JTAG_TDI" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET JTAG_TDO       LOC="P106" |>
+   [BPC3011-Papilio_Pro-general.ucf(123)]: NET "JTAG_TDO" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET JTAG_TDO       LOC="P106" |> [BPC3011-Papilio_Pro-general.ucf(123)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL |>
+   [BPC3011-Papilio_Pro-general.ucf(123)]: NET "JTAG_TDO" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <DRIVE=8 |>
+   [BPC3011-Papilio_Pro-general.ucf(123)]: NET "JTAG_TDO" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <SLEW=FAST;>
+   [BPC3011-Papilio_Pro-general.ucf(123)]: NET "JTAG_TDO" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET FLASH_CS       LOC="P38"  |>
+   [BPC3011-Papilio_Pro-general.ucf(124)]: NET "FLASH_CS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET FLASH_CS       LOC="P38"  |> [BPC3011-Papilio_Pro-general.ucf(124)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL |>
+   [BPC3011-Papilio_Pro-general.ucf(124)]: NET "FLASH_CS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <DRIVE=8 |>
+   [BPC3011-Papilio_Pro-general.ucf(124)]: NET "FLASH_CS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <SLEW=FAST;>
+   [BPC3011-Papilio_Pro-general.ucf(124)]: NET "FLASH_CS" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET FLASH_CK       LOC="P70"  |>
+   [BPC3011-Papilio_Pro-general.ucf(125)]: NET "FLASH_CK" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET FLASH_CK       LOC="P70"  |> [BPC3011-Papilio_Pro-general.ucf(125)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL |>
+   [BPC3011-Papilio_Pro-general.ucf(125)]: NET "FLASH_CK" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <DRIVE=8 |>
+   [BPC3011-Papilio_Pro-general.ucf(125)]: NET "FLASH_CK" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <SLEW=FAST;>
+   [BPC3011-Papilio_Pro-general.ucf(125)]: NET "FLASH_CK" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <NET FLASH_SI       LOC="P64"  |>
+   [BPC3011-Papilio_Pro-general.ucf(126)]: NET "FLASH_SI" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET FLASH_SI       LOC="P64"  |> [BPC3011-Papilio_Pro-general.ucf(126)]'
+   could not be found and so the Locate constraint will be removed.
+
+INFO:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL |>
+   [BPC3011-Papilio_Pro-general.ucf(126)]: NET "FLASH_SI" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <DRIVE=8 |>
+   [BPC3011-Papilio_Pro-general.ucf(126)]: NET "FLASH_SI" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem:59 - Constraint <SLEW=FAST;>
+   [BPC3011-Papilio_Pro-general.ucf(126)]: NET "FLASH_SI" not found.  Please
+   verify that:
+   1. The specified design element actually exists in the original design.
+   2. The specified object is spelled correctly in the constraint source file.
+
+INFO:ConstraintSystem - The Period constraint <PERIOD=31.25ns;>
+   [BPC3011-Papilio_Pro-general.ucf(29)], is specified using the Net Period
+   method which is not recommended. Please use the Timespec PERIOD method.
+
+Done...
+
+Checking expanded design ...
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+NGDBUILD Design Results Summary:
+  Number of errors:     0
+  Number of warnings:  95
+
+Total memory usage is 400388 kilobytes
+
+Writing NGD file "led.ngd" ...
+Total REAL time to NGDBUILD completion:  2 sec
+Total CPU time to NGDBUILD completion:   2 sec
+
+Writing NGDBUILD log file "led.bld"...
diff --git a/led.cmd_log b/led.cmd_log
index 1e860a3..a73950e 100644
--- a/led.cmd_log
+++ b/led.cmd_log
@@ -1 +1,131 @@
 xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o led_map.ncd led.ngd led.pcf 
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o led_map.ncd led.ngd led.pcf 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o led_map.ncd led.ngd led.pcf 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o led_map.ncd led.ngd led.pcf 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -t 1 led_map.ncd led.ncd led.pcf 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -t 1 led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -t 1 led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -t 1 led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc3s250e-vq100-4 led.ngc led.ngd  
+map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -t 1 led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-3 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-3 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc /home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf 
+bitgen -intstyle ise -f led.ut led.ncd 
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc BPC3011-Papilio_Pro-general.ucf -p xc6slx9-tqg144-2 led.ngc led.ngd  
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf -ucf BPC3011-Papilio_Pro-general.ucf 
+bitgen -intstyle ise -f led.ut led.ncd 
diff --git a/led.drc b/led.drc
new file mode 100644
index 0000000..d361f6a
--- /dev/null
+++ b/led.drc
@@ -0,0 +1,8 @@
+Release 14.7 Drc P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Tue Feb 21 22:17:07 2017
+
+drc -z led.ncd led.pcf
+
+DRC detected 0 errors and 0 warnings.
diff --git a/led.ncd b/led.ncd
new file mode 100644
index 0000000..bc25375
--- /dev/null
+++ b/led.ncd
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
+###5788:XlxV32DM    3fff    1684eNrNWmtz2ziW/SuqKX/opNsO8SD4wMTVEkk7qugVSXY7s7VhkRSZaNex3LYynVSc/Pa5AEiCoiBZdtVudadFXJz7wL0geAjIOsJ28R1Z/Gia/3t5v1zd+B10QjtHmB/jlB9/vF6lyXW8ul17/Hh5s75ff7vOM6TlzvI+7xzfdr5m7P76q3e8/vMjovQYd47/6hxfrz4uM+HcWRVF53h13fm0/Pipc7zuoM7x13XH6hzf5R+X9+v8Ll58ub1eZskaUlDWdx3aaYyvwM9lu7xT7W3ZXmdlf/VXXkKrznW+iD8ntyc32ULIJzcfVXubFR0CJdzB5TpLuM4TgM/isrpmXMWCzu0dsrkxUZikNcm5KHVzPupKy3y3Msl0Jgv+qndxdj68uIqv8HvM+KtJN6REtY4F6tmgH0TxFcLvibvZ9Ta6dNOYos0u3uySRpdsRiabkclmZLIZmWxGpptae6vbNGagRRwRjk4swskJEheccPs36zeH/IZJQ6Yu4l2S8G4nS+7uvnWyT8nypnO/Tu7Wy5uPnb+W60+l5vOXr51/DLPVl5t1XF6//dM6/QfmXQQfDB8CHwofGz6M8i7MPkjvEO9h3gOjHhj1wKgHRj0w6jGb9wbj4K2jmqv38Mz0hufTuDufT/u9i3k04xQQEaf3zuPilsr7Kuwu+oMwnnen5xFcgjcZ7+XX9x3rhMBzMMllzxe2sbikqh90p9P3NFGdN91pCNMo5f64F/dhnLzRHYFjofvjizkAngIGF3Nbi8xVIqytcqBpdB7PpogHmAdQeQCVB1B5AJUHUHnAoIKgG8aX/eiP+DKazvrjkc1leoQH/RGYvAVh8NYTF1kC1FSLchKKRr8vGsoDKAHcxgTcxsNhfz6PwgTE2RxmqjeIwALKgODvHB5Moy6oGQ/e90f9+YIHq8+39QQmqitn0CtlmIWsFOVaG2z0rhAPMQ+h2hCqDaHaEKoNodqQER72LXFB4oLFhVAeyhsbvst4dHY2ns7jQXQZDRb8fDDudQfxYHzeD1Cx2T2x2gCCqWwh1jZksMLbENmG6DZkb0NsG3K2IXcb8trlbGeFt8vB2+Vg3I5E2gBtA3YbYG3AaQNuG/AQ72Pet+AzcjkskVfiOfKUJB6hRIrq6XGkDI8JMHF/Fs3jYTTsRdNYPv5xrz8K+6PzV0Dir/qwZN/0o6l4tN/H3cH5OBiPZjHGlAtVTRDxRDw8s3k0mseT6XgSz0AxEgQhzMqI8fz9JEIu3xUU1uymStozCfZH82g6gnong3jaHZ1HwNoCH43DSNkp52l0Fk2jETCweKYpH0QhjCiuJ1CvJ6V4DHMAqdVyfJtk/xujVCF39+vb1ZrxwbgbRqHDBbO86qJKwJVAKoFWgl0JDB6wYXcSB8Nw0B9F8XgyB2aZJRIcjsOLQbSQ8rw/jGbz7nCSym5JQeCc3EJB2zwv4rZAZEaREcVGlBhRakRtI8qMqGNEXSPqnRoKNhaBjQVjsy02hTWCxARSE2ibQGYCHRPomkAon26C11/W8t4mRhgeiMvYMvogsw/a54PNPnifDzH7kH0+1OxD9/nYZh97nw8z+7B9Po7Zx9nn45p93H0+ntnHq3yIQXmKPBO6exRsXjl438rB5pWD945jXjl438rB5pWDyZ4ZwMYZwHs8iNFj3xjU6EH3eNhGD3uPBzN6sD0ejtHD2ePhGj3cPR6e0WPXivy6uhOvIrqNoh0wMsPYDBMzTM2wbYaZGXbMsGuGvVNT7eZqsLl2vMPaXDsmxhGxETXbUiNqG1FmRB0j6hpR7zTlIytG1knXhr2P6qCTnu7gk0B3yEmoO7TpYzd9WNPHafq4TR+v4YOthg9GDR+MGz6YNH2o8klEp1RIuYnbKpSUmYokZadh7zbsPWXv8FE0/2M8fYv4GPMxbMzH8Nofw5lsDGeyMZzHxnAeGwuniThbwJkHwXlxQmCH2w1gH2rVcrV9ZHzSDd5GIYE2ROI6be8wkc0n4azcyJ+PwmrrDY+3ERf7ZRGp1skBh7CNLxrgxax7Hm2EvgwCY+gGLkO3fcTQw/MpbLUFHo7huKAOwPHF6GIWhfGkP5qpoWH64inMD4TKakDs9BPVOw/jfqhMJ+Gw2jrDHEukP4q7s1n/fBTDvrpMQ4DRFZxRYFuvzgwqsDz9NyflMgpk9kirxXCz96Og6dIstnKxG2qVUSzOMuUcb+BTOJNN3sbBeDiZd89TJY9mc1g8QA3QCyNZwOh8GM/GF9MgUvDZtHs+i+fjuBfB8Q8OPYVAwapxmABArJX5m+kFHH/gzNSDWX4rvnuI5bcbQOwTGMYzqWDOhQ4yvlutV+KrhfLhPhnbm2jPiAYVSjdQ+fUGTBkc6EzwCdqMEhpiI2MeyJgH0nlsoKa42BgXG+PiOm6hQXoiTttNM4WcwFyKVVShQHIXZ+cnY8TfeXya33+5XsObNKlE1JRRQ8YNmTRk2pDthswastOQ3YbsndYpNIbCjRRwE2+kAC+p2hVrsYFSLdpaZFp0tOhq0TvFfAZMOYOneAZMOQNCVF9xwbE7q0Ux/7rHoFeb9ZAWtXOP1ua9DefehnOgnQOsRVKbBxvOgXBe1D35nSawdtWvFnYdKNQxQ51bqHMLN8KHjdyuXnWRFrEWiRapFm0tskyL8g1V9c7OaqOejt3TsXs6dk/H7unYPR27txG714gd6NiBjh3o2IGOHejYgY4dbMQOGrFDHTvUsUMdO9SxQx071LHDjdjh2ZnDZ5+S2zy2cj6vX1ziVVHIfsnI8t1B2wi8JqMprFwFX4q/AggOhldnsYlNYdU0gSGsmkZ/Nonk639evrL6wwnk15+rKPONd928eqnIBAb93gzxq4RfhW9U7jNXypBloNDZm+4kKlHhk0qpCrjgV33YTlwdX4W9jnWCOrP5hRK6s6DfZ/xqkcb9BTgtPse95c1iefMRMhW9YfI/q7vL/E78na2Cljca4u8dnn1eXC9vcpfL/SMwX1pL8d3aKzvAgrWItAh7YEvL6is7u9aShpaUWqfW0oaWllq31tp6EKZFR4tuw90t3XGt9Rpar9SiqkZdgDgfWFpWdqTWooYWlVpaaxvF463icaN4XBXPtiGnqBB6qt54VZb4tJJILdFasmuJ1ZJTS24twUSUI/wXZv8td1QoXsX5n1+S6xjHq39idoqtxywQRo+aIOw+blPeiepGHWD6hLDkcFP7cFN2uKkD78fHTONDCiprt7BzoCk+2JIdbOk8vi7w4+sCH3CzsS7YPdQWH27KDjd1H7+D+JA7iOvV6xxoSg62pAdbOgdbuo/fa/L4vSYHzAypOeBgU3K4qX24qXO4qff4qiAHFVSV/vh9IQc/1+TgVUGqOTrU0j3Y0nt8/dDHJ5HGBzwv9OB6aVUFe8yyui8HGpJDDe1DDdmhhl5ZtdgNl0L5x9FKUW1zgE2LWiptahWqVaitwrUKt1WkVpG2itYq2lbZtcpuq1itYm2VU6uctsqtVW5b5dUqr1RV04Ra01Q9rTGupwm3pwnX04Tb04TracLtacL1NGHSSgK3kiCVgrQUtFLQlsKuFHZLwSoFaymcSuG0FG6lcFsKr1JUc0i5+HUZ4cv7nPDrHM4a9Q/MPn4mfFUUhN8mdy6/h+s6uWGMq9/lObz8nR7sqR/Caf8yEr9O6I2vfNefDaI/4DKGywUcr0ahT2bz7jx6eBhDOwq709AfXM7nA2Lxh0F3HryJx9P47MyH/2dTcZAvG8sXXwLK3z34XSE+PDzmgrZdHA4D26+tSkAPKBMSe/3LL1388pcugQ992bVfvHjxa5e9aKspfOyXoBBq8uKBJJX6p9RVIUqbF79Kl59d/CtciLjYv/5UqhcPwKbKWbiVarpho4cXEcrkdPQHRCo1ky5CByhtoz8FjJ0S/tlFMic56EuVOVi8rBPzlCH0H+Ck+/Dw0N+8Vz9+//3WLjz+++9fMfX8M9/20feZXfhJ6sML0keEZHa+8AlDC/L9BqW5jzg0hc/4EUozH6Up/zGzU5MD47PE8jHNfGsD97hw2MbTnfhCJAegj3cmB+kkkE6y4EckhyALfpN4vu0mWZrZiB8lrgSPkkT4gjUlACT833OEIZz85y72hU/BgfB3CMKj7z+gzUR7hIgHgfiRjYQazCw1EEoKEAohiHxyoUJy9qhd5UX4N0Qtn8Bx/huwtRQGCCdQ55Ej8nP4jQ3D8B9vxLZ8kDh++v0IZciHATHoU6gWGqiHqZ6jGls1mWoS1aSq8WTco4WPZVyy4P9CKYUhGfIhBwHZIguoXI2V1z6ujPAjFbcDyoVp8in5/ifMFP9TvIjAlfKlbcO9eoNSzL8gAoNanK+8dAtLYflgf+HDDWGwtChMDsUQQlSDCNxtLOYu9RmEhGQsH1CwdRiHfg59vsKFaJaEaa0HWuJILUmllhZam4PWtqTW9lSzkEYsrY1cG4xYJrUOEk2KFgu5/MDzu8rNcUSmIkMCE2ETlSplfIWwKB8mCWUEBNJ0coUTgyVAXL9Q/+VViKQM4TSrTbAuFrY7ZWDktrPJNrKhhmwWbjuZhcqDLSq31JgBMmbgtTJw0aMZ5LiVgYvLDPKnZ5CK+5M3gxFYxpT67vcC+cAEReanjo8s5KfwOFvYB48f7YkXYyFYA4laA5ZqyhWRq0YtMccqx0dli8uWlC2VZsjBZUvKtsKrRaHYrZl4NVcY1jOq5jdpW7mPzy9tz69Xzm+xf34Naww2DtDi768FxTs2fw3BxXb7xz2iea1xLP5apAopCM2iUBqwxQv+gaXSfFGbM2EO9QveuUfyiStHAP784Cg0aaCEf7A9idoNFPMPRIa2m7aIfwAC+nEvF4YC4ZH6YC9EMahMDMsiVFFUZlcmIRa0qEKmWchi8tpHFEMFuHAUBs+SjkNknKSK4+o4uYxDah8Rh8g5zEpQCDoSlpG8UgWUU0daSCesnUQoLFBHzcwHnHOlEIM6TIHE4XJcgblqDj7YcBNETRIrnVkmb7DAfqSZWHi57zVY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+\ No newline at end of file
diff --git a/led.ngc b/led.ngc
new file mode 100644
index 0000000..b051105
--- /dev/null
+++ b/led.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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diff --git a/led.ngd b/led.ngd
new file mode 100644
index 0000000..f47e249
--- /dev/null
+++ b/led.ngd
@@ -0,0 +1,3 @@
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+\ No newline at end of file
diff --git a/led.ngr b/led.ngr
new file mode 100644
index 0000000..a74c874
--- /dev/null
+++ b/led.ngr
@@ -0,0 +1,3 @@
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<2=lh1e5>4>2:pa4<72;q6jn4>2:?52?>b3-3?6io4n81956=z{l:1<7<t=g`957=:>?03h6*64;fb?k?428>0q~ji:1818`f28801;858b9'=1<ci2d2?7?:;|qga?6=:r7m57?=;<45>=d<,0>1hl5a92822>{tlm0;6?u2f9826>;1>32j7)7;:ec8j<5=9>1vim50;0x9c6=9;16:;479:&:0?bf3g386<64}rf0>5<5s4o>6<<4=749<5=#1=0om6`63;3:?xud03:1>v3j4;31?8012>?0(4:5d`9m=6<6i2wx:>4?:3y>27<6:27=8786;|q`4?6=9mq6:?4j;<g7>27<5l?1;<52f1845>;a03=:70h6:6389cg=?816jo481:?eg?1634lo6:?4=gg934=:m?02=63j7;52?8c?2>;01h75909>ad<0927nn79>;<g`>27<5ln1;<52ed8:5>;bn3=:70h>:8389c4=1816j>461:?e0??634l>6:?4=g4934=:n>0<=63l7;a3?xud93:1>v3l2;4:?8e02j;0q~m=:1818e42?301n95c39~yx{zHIIp=o:5e4da31>4uIJIw=sO@Qy~DE
+\ No newline at end of file
diff --git a/led.pad b/led.pad
new file mode 100644
index 0000000..c9d913a
--- /dev/null
+++ b/led.pad
@@ -0,0 +1,174 @@
+Release 14.7 - par P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Tue Feb 21 22:16:59 2017
+
+
+# NOTE: This file is designed to be imported into a spreadsheet program
+# such as Microsoft Excel for viewing, printing and sorting. The |
+# character is used as the data field separator. This file is also designed
+# to support parsing.
+#
+INPUT FILE:       led_map.ncd
+OUTPUT FILE:      led.pad
+PART TYPE:        xc6slx9
+SPEED GRADE:      -2
+PACKAGE:          tqg144
+
+Pinout by Pin Number:
+
+-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
+Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
+P1||IOBS|IO_L83N_VREF_3|UNUSED||3|||||||||
+P2||IOBM|IO_L83P_3|UNUSED||3|||||||||
+P3|||GND||||||||||||
+P4|||VCCO_3|||3|||||any******||||
+P5||IOBS|IO_L52N_3|UNUSED||3|||||||||
+P6||IOBM|IO_L52P_3|UNUSED||3|||||||||
+P7||IOBS|IO_L51N_3|UNUSED||3|||||||||
+P8||IOBM|IO_L51P_3|UNUSED||3|||||||||
+P9||IOBS|IO_L50N_3|UNUSED||3|||||||||
+P10||IOBM|IO_L50P_3|UNUSED||3|||||||||
+P11||IOBS|IO_L49N_3|UNUSED||3|||||||||
+P12||IOBM|IO_L49P_3|UNUSED||3|||||||||
+P13|||GND||||||||||||
+P14||IOBS|IO_L44N_GCLK20_3|UNUSED||3|||||||||
+P15||IOBM|IO_L44P_GCLK21_3|UNUSED||3|||||||||
+P16||IOBS|IO_L43N_GCLK22_IRDY2_3|UNUSED||3|||||||||
+P17||IOBM|IO_L43P_GCLK23_3|UNUSED||3|||||||||
+P18|||VCCO_3|||3|||||any******||||
+P19|||VCCINT||||||||1.2||||
+P20|||VCCAUX||||||||2.5||||
+P21||IOBS|IO_L42N_GCLK24_3|UNUSED||3|||||||||
+P22||IOBM|IO_L42P_GCLK25_TRDY2_3|UNUSED||3|||||||||
+P23||IOBS|IO_L41N_GCLK26_3|UNUSED||3|||||||||
+P24||IOBM|IO_L41P_GCLK27_3|UNUSED||3|||||||||
+P25|||GND||||||||||||
+P26||IOBS|IO_L37N_3|UNUSED||3|||||||||
+P27||IOBM|IO_L37P_3|UNUSED||3|||||||||
+P28|||VCCINT||||||||1.2||||
+P29||IOBS|IO_L36N_3|UNUSED||3|||||||||
+P30||IOBM|IO_L36P_3|UNUSED||3|||||||||
+P31|||VCCO_3|||3|||||any******||||
+P32||IOBS|IO_L2N_3|UNUSED||3|||||||||
+P33||IOBM|IO_L2P_3|UNUSED||3|||||||||
+P34||IOBS|IO_L1N_VREF_3|UNUSED||3|||||||||
+P35||IOBM|IO_L1P_3|UNUSED||3|||||||||
+P36|||VCCAUX||||||||2.5||||
+P37|||PROGRAM_B_2||||||||||||
+P38||IOBS|IO_L65N_CSO_B_2|UNUSED||2|||||||||
+P39||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
+P40||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
+P41||IOBM|IO_L64P_D8_2|UNUSED||2|||||||||
+P42|||VCCO_2|||2|||||any******||||
+P43||IOBS|IO_L62N_D6_2|UNUSED||2|||||||||
+P44||IOBM|IO_L62P_D5_2|UNUSED||2|||||||||
+P45||IOBS|IO_L49N_D4_2|UNUSED||2|||||||||
+P46||IOBM|IO_L49P_D3_2|UNUSED||2|||||||||
+P47||IOBS|IO_L48N_RDWR_B_VREF_2|UNUSED||2|||||||||
+P48||IOBM|IO_L48P_D7_2|UNUSED||2|||||||||
+P49|||GND||||||||||||
+P50||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2|||||||||
+P51||IOBM|IO_L31P_GCLK31_D14_2|UNUSED||2|||||||||
+P52|||VCCINT||||||||1.2||||
+P53|||VCCAUX||||||||2.5||||
+P54|||GND||||||||||||
+P55||IOBS|IO_L30N_GCLK0_USERCCLK_2|UNUSED||2|||||||||
+P56||IOBM|IO_L30P_GCLK1_D13_2|UNUSED||2|||||||||
+P57||IOBS|IO_L14N_D12_2|UNUSED||2|||||||||
+P58||IOBM|IO_L14P_D11_2|UNUSED||2|||||||||
+P59||IOBS|IO_L13N_D10_2|UNUSED||2|||||||||
+P60||IOBM|IO_L13P_M1_2|UNUSED||2||||||PROHIBITED|||
+P61||IOBS|IO_L12N_D2_MISO3_2|UNUSED||2|||||||||
+P62||IOBM|IO_L12P_D1_MISO2_2|UNUSED||2|||||||||
+P63|||VCCO_2|||2|||||any******||||
+P64||IOBS|IO_L3N_MOSI_CSI_B_MISO0_2|UNUSED||2|||||||||
+P65||IOBM|IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED||2|||||||||
+P66||IOBS|IO_L2N_CMPMOSI_2|UNUSED||2|||||||||
+P67||IOBM|IO_L2P_CMPCLK_2|UNUSED||2|||||||||
+P68|||GND||||||||||||
+P69||IOBS|IO_L1N_M0_CMPMISO_2|UNUSED||2||||||PROHIBITED|||
+P70||IOBM|IO_L1P_CCLK_2|UNUSED||2|||||||||
+P71|||DONE_2||||||||||||
+P72|||CMPCS_B_2||||||||||||
+P73|||SUSPEND||||||||||||
+P74||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1|||||||||
+P75||IOBM|IO_L74P_AWAKE_1|UNUSED||1|||||||||
+P76|||VCCO_1|||1|||||any******||||
+P77|||GND||||||||||||
+P78||IOBS|IO_L47N_1|UNUSED||1|||||||||
+P79||IOBM|IO_L47P_1|UNUSED||1|||||||||
+P80||IOBS|IO_L46N_1|UNUSED||1|||||||||
+P81||IOBM|IO_L46P_1|UNUSED||1|||||||||
+P82||IOBS|IO_L45N_1|UNUSED||1|||||||||
+P83||IOBM|IO_L45P_1|UNUSED||1|||||||||
+P84||IOBS|IO_L43N_GCLK4_1|UNUSED||1|||||||||
+P85||IOBM|IO_L43P_GCLK5_1|UNUSED||1|||||||||
+P86|||VCCO_1|||1|||||any******||||
+P87||IOBS|IO_L42N_GCLK6_TRDY1_1|UNUSED||1|||||||||
+P88||IOBM|IO_L42P_GCLK7_1|UNUSED||1|||||||||
+P89|||VCCINT||||||||1.2||||
+P90|||VCCAUX||||||||2.5||||
+P91|||GND||||||||||||
+P92||IOBS|IO_L41N_GCLK8_1|UNUSED||1|||||||||
+P93||IOBM|IO_L41P_GCLK9_IRDY1_1|UNUSED||1|||||||||
+P94|CLK|IOB|IO_L40N_GCLK10_1|INPUT|LVTTL|1||||NONE||LOCATED|NO|NONE|
+P95||IOBM|IO_L40P_GCLK11_1|UNUSED||1|||||||||
+P96|||GND||||||||||||
+P97||IOBS|IO_L34N_1|UNUSED||1|||||||||
+P98||IOBM|IO_L34P_1|UNUSED||1|||||||||
+P99||IOBS|IO_L33N_1|UNUSED||1|||||||||
+P100||IOBM|IO_L33P_1|UNUSED||1|||||||||
+P101||IOBS|IO_L32N_1|UNUSED||1|||||||||
+P102||IOBM|IO_L32P_1|UNUSED||1|||||||||
+P103|||VCCO_1|||1|||||any******||||
+P104||IOBS|IO_L1N_VREF_1|UNUSED||1|||||||||
+P105||IOBM|IO_L1P_1|UNUSED||1|||||||||
+P106|||TDO||||||||||||
+P107|||TMS||||||||||||
+P108|||GND||||||||||||
+P109|||TCK||||||||||||
+P110|||TDI||||||||||||
+P111||IOBS|IO_L66N_SCP0_0|UNUSED||0|||||||||
+P112|LED1|IOB|IO_L66P_SCP1_0|OUTPUT|LVTTL|0|8|SLOW||||LOCATED|NO|NONE|
+P113|||GND||||||||||||
+P114||IOBS|IO_L65N_SCP2_0|UNUSED||0|||||||||
+P115||IOBM|IO_L65P_SCP3_0|UNUSED||0|||||||||
+P116||IOBS|IO_L64N_SCP4_0|UNUSED||0|||||||||
+P117||IOBM|IO_L64P_SCP5_0|UNUSED||0|||||||||
+P118||IOBS|IO_L63N_SCP6_0|UNUSED||0|||||||||
+P119||IOBM|IO_L63P_SCP7_0|UNUSED||0|||||||||
+P120||IOBS|IO_L62N_VREF_0|UNUSED||0|||||||||
+P121||IOBM|IO_L62P_0|UNUSED||0|||||||||
+P122|||VCCO_0|||0|||||3.30||||
+P123||IOBS|IO_L37N_GCLK12_0|UNUSED||0|||||||||
+P124||IOBM|IO_L37P_GCLK13_0|UNUSED||0|||||||||
+P125|||VCCO_0|||0|||||3.30||||
+P126||IOBS|IO_L36N_GCLK14_0|UNUSED||0|||||||||
+P127||IOBM|IO_L36P_GCLK15_0|UNUSED||0|||||||||
+P128|||VCCINT||||||||1.2||||
+P129|||VCCAUX||||||||2.5||||
+P130|||GND||||||||||||
+P131||IOBS|IO_L35N_GCLK16_0|UNUSED||0|||||||||
+P132||IOBM|IO_L35P_GCLK17_0|UNUSED||0|||||||||
+P133||IOBS|IO_L34N_GCLK18_0|UNUSED||0|||||||||
+P134||IOBM|IO_L34P_GCLK19_0|UNUSED||0|||||||||
+P135|||VCCO_0|||0|||||3.30||||
+P136|||GND||||||||||||
+P137||IOBS|IO_L4N_0|UNUSED||0|||||||||
+P138||IOBM|IO_L4P_0|UNUSED||0|||||||||
+P139||IOBS|IO_L3N_0|UNUSED||0|||||||||
+P140||IOBM|IO_L3P_0|UNUSED||0|||||||||
+P141||IOBS|IO_L2N_0|UNUSED||0|||||||||
+P142||IOBM|IO_L2P_0|UNUSED||0|||||||||
+P143||IOBS|IO_L1N_VREF_0|UNUSED||0|||||||||
+P144||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0||||||PROHIBITED|||
+
+-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
+
+* Default value.
+** This default Pullup/Pulldown value can be overridden in Bitgen. 
+****** Special VCCO requirements may apply. Please consult the device 
+       family datasheet for specific guideline on VCCO requirements. 
+
+
diff --git a/led.par b/led.par
new file mode 100644
index 0000000..a86afaf
--- /dev/null
+++ b/led.par
@@ -0,0 +1,181 @@
+Release 14.7 par P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+yann-arch::  Tue Feb 21 22:16:56 2017
+
+par -w -intstyle ise -ol high -mt off led_map.ncd led.ncd led.pcf 
+
+
+Constraints file: led.pcf.
+Loading device for application Rf_Device from file '6slx9.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
+   "led" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
+
+Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
+Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
+
+
+Device speed data version:  "PRODUCTION 1.23 2013-10-13".
+
+
+
+Device Utilization Summary:
+
+Slice Logic Utilization:
+  Number of Slice Registers:                    25 out of  11,440    1%
+    Number used as Flip Flops:                  25
+    Number used as Latches:                      0
+    Number used as Latch-thrus:                  0
+    Number used as AND/OR logics:                0
+  Number of Slice LUTs:                         57 out of   5,720    1%
+    Number used as logic:                       57 out of   5,720    1%
+      Number using O6 output only:              34
+      Number using O5 output only:               1
+      Number using O5 and O6:                   22
+      Number used as ROM:                        0
+    Number used as Memory:                       0 out of   1,440    0%
+
+Slice Logic Distribution:
+  Number of occupied Slices:                    15 out of   1,430    1%
+  Number of MUXCYs used:                        24 out of   2,860    1%
+  Number of LUT Flip Flop pairs used:           57
+    Number with an unused Flip Flop:            32 out of      57   56%
+    Number with an unused LUT:                   0 out of      57    0%
+    Number of fully used LUT-FF pairs:          25 out of      57   43%
+    Number of slice register sites lost
+      to control set restrictions:               0 out of  11,440    0%
+
+  A LUT Flip Flop pair for this architecture represents one LUT paired with
+  one Flip Flop within a slice.  A control set is a unique combination of
+  clock, reset, set, and enable signals for a registered element.
+  The Slice Logic Distribution report is not meaningful if the design is
+  over-mapped for a non-slice resource or if Placement fails.
+
+IO Utilization:
+  Number of bonded IOBs:                         2 out of     102    1%
+    Number of LOCed IOBs:                        2 out of       2  100%
+
+Specific Feature Utilization:
+  Number of RAMB16BWERs:                         0 out of      32    0%
+  Number of RAMB8BWERs:                          0 out of      64    0%
+  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
+  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
+  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
+    Number used as BUFGs:                        1
+    Number used as BUFGMUX:                      0
+  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
+  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
+  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
+  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
+  Number of BSCANs:                              0 out of       4    0%
+  Number of BUFHs:                               0 out of     128    0%
+  Number of BUFPLLs:                             0 out of       8    0%
+  Number of BUFPLL_MCBs:                         0 out of       4    0%
+  Number of DSP48A1s:                            0 out of      16    0%
+  Number of ICAPs:                               0 out of       1    0%
+  Number of MCBs:                                0 out of       2    0%
+  Number of PCILOGICSEs:                         0 out of       2    0%
+  Number of PLL_ADVs:                            0 out of       2    0%
+  Number of PMVs:                                0 out of       1    0%
+  Number of STARTUPs:                            0 out of       1    0%
+  Number of SUSPEND_SYNCs:                       0 out of       1    0%
+
+
+Overall effort level (-ol):   High 
+Router effort level (-rl):    High 
+
+Starting initial Timing Analysis.  REAL time: 2 secs 
+Finished initial Timing Analysis.  REAL time: 2 secs 
+
+Starting Router
+
+
+Phase  1  : 235 unrouted;      REAL time: 2 secs 
+
+Phase  2  : 203 unrouted;      REAL time: 3 secs 
+
+Phase  3  : 78 unrouted;      REAL time: 3 secs 
+
+Phase  4  : 78 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 3 secs 
+
+Updating file: led.ncd with current fully routed design.
+
+Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 3 secs 
+
+Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 3 secs 
+
+Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 3 secs 
+
+Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 3 secs 
+
+Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 3 secs 
+
+Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 3 secs 
+Total REAL time to Router completion: 3 secs 
+Total CPU time to Router completion: 3 secs 
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+Generating "PAR" statistics.
+
+**************************
+Generating Clock Report
+**************************
+
++---------------------+--------------+------+------+------------+-------------+
+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
++---------------------+--------------+------+------+------------+-------------+
+|           CLK_BUFGP |  BUFGMUX_X2Y2| No   |    8 |  0.005     |  1.395      |
++---------------------+--------------+------+------+------------+-------------+
+
+* Net Skew is the difference between the minimum and maximum routing
+only delays for the net. Note this is different from Clock Skew which
+is reported in TRCE timing report. Clock Skew is the difference between
+the minimum and maximum path delays which includes logic delays.
+
+* The fanout is the number of component pins not the individual BEL loads,
+for example SLICE loads not FF loads.
+
+Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
+
+Asterisk (*) preceding a constraint indicates it was not met.
+   This may be due to a setup or hold violation.
+
+----------------------------------------------------------------------------------------------------------
+  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
+                                            |             |    Slack   | Achievable | Errors |    Score   
+----------------------------------------------------------------------------------------------------------
+  NET "CLK_BUFGP/IBUFG" PERIOD = 31.25 ns H | SETUP       |    27.555ns|     3.695ns|       0|           0
+  IGH 50%                                   | HOLD        |     0.418ns|            |       0|           0
+----------------------------------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+Generating Pad Report.
+
+All signals are completely routed.
+
+Total REAL time to PAR completion: 3 secs 
+Total CPU time to PAR completion: 3 secs 
+
+Peak Memory Usage:  607 MB
+
+Placer: Placement generated during map.
+Routing: Completed - No errors found.
+Timing: Completed - No errors found.
+
+Number of error messages: 0
+Number of warning messages: 0
+Number of info messages: 0
+
+Writing design to file led.ncd
+
+
+
+PAR done!
diff --git a/led.pcf b/led.pcf
new file mode 100644
index 0000000..d505459
--- /dev/null
+++ b/led.pcf
@@ -0,0 +1,13 @@
+//! **************************************************************************
+// Written by: Map P.20131013 on Tue Feb 21 22:16:54 2017
+//! **************************************************************************
+
+SCHEMATIC START;
+PROHIBIT = SITE "P144";
+PROHIBIT = SITE "P69";
+PROHIBIT = SITE "P60";
+COMP "LED1" LOCATE = SITE "P112" LEVEL 1;
+COMP "CLK" LOCATE = SITE "P94" LEVEL 1;
+NET "CLK_BUFGP/IBUFG" PERIOD = 31.25 ns HIGH 50%;
+SCHEMATIC END;
+
diff --git a/led.ptwx b/led.ptwx
new file mode 100644
index 0000000..ab35e6c
--- /dev/null
+++ b/led.ptwx
@@ -0,0 +1,332 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE twReport [
+<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
+					twDebug*, twFoot?, twClientInfo?)>
+<!ATTLIST twReport version CDATA "10,4">
+<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
+<!ELEMENT twExecVer (#PCDATA)>
+<!ELEMENT twCopyright (#PCDATA)>
+<!ELEMENT twCmdLine (#PCDATA)>
+<!ELEMENT twDesign (#PCDATA)>
+<!ELEMENT twPCF (#PCDATA)>
+<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
+<!ELEMENT twDevName (#PCDATA)>
+<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
+<!ELEMENT twSpeedGrade (#PCDATA)>
+<!ELEMENT twSpeedVer (#PCDATA)>
+<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
+<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
+<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
+<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
+<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
+<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
+<!ELEMENT twItemLimit (#PCDATA)>
+<!ELEMENT twUnconst EMPTY>
+<!ELEMENT twUnconstLimit (#PCDATA)>
+<!ELEMENT twEnvVar EMPTY>
+<!ATTLIST twEnvVar name CDATA #REQUIRED>
+<!ATTLIST twEnvVar description CDATA #REQUIRED>
+<!ELEMENT twWarn (#PCDATA)>
+<!ELEMENT twInfo (#PCDATA)>
+<!ELEMENT twDebug (#PCDATA)>
+<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
+<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
+<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
+<!ELEMENT twProc (#PCDATA)>
+<!ELEMENT twTemp (#PCDATA)>
+<!ELEMENT twVolt (#PCDATA)>
+<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
+<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
+<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
+<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
+<!ELEMENT twCycles (twSigConn+)>
+<!ATTLIST twCycles twNum CDATA #REQUIRED>
+<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
+<!ELEMENT twSig (#PCDATA)>
+<!ELEMENT twDriver (#PCDATA)>
+<!ELEMENT twLoad (#PCDATA)> 
+<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
+<!ATTLIST twConst twConstType (NET | 
+							   NETDELAY | 
+							   NETSKEW | 
+							   PATH |
+							   DEFPERIOD |
+							   UNCONSTPATH |
+							   DEFPATH | 
+							   PATH2SETUP |
+							   UNCONSTPATH2SETUP | 
+							   PATHCLASS | 
+							   PATHDELAY | 
+							   PERIOD |
+							   FREQUENCY |
+							   PATHBLOCK |
+							   OFFSET |
+							   OFFSETIN |
+							   OFFSETINCLOCK | 
+							   UNCONSTOFFSETINCLOCK |
+							   OFFSETINDELAY |
+							   OFFSETINMOD |
+							   OFFSETOUT |
+							   OFFSETOUTCLOCK |
+							   UNCONSTOFFSETOUTCLOCK | 
+							   OFFSETOUTDELAY |
+							   OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
+<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
+					   twEndPtCnt?,
+					   twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
+<!ELEMENT twConstName (#PCDATA)>
+<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
+<!ATTLIST twConstHead uID CDATA #IMPLIED>
+<!ELEMENT twItemCnt (#PCDATA)>
+<!ELEMENT twErrCnt (#PCDATA)>
+<!ELEMENT twErrCntEndPt (#PCDATA)>
+<!ELEMENT twErrCntSetup (#PCDATA)>
+<!ELEMENT twErrCntHold (#PCDATA)>
+<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
+<!ELEMENT twEndPtCnt (#PCDATA)>
+<!ELEMENT twPathErrCnt (#PCDATA)>
+<!ELEMENT twMinPer (#PCDATA) >
+<!ELEMENT twFootnote EMPTY>
+<!ATTLIST twFootnote number CDATA #REQUIRED>
+<!ELEMENT twMaxDel (#PCDATA)>
+<!ELEMENT twMaxFreq (#PCDATA)>
+<!ELEMENT twMinOff (#PCDATA)>
+<!ELEMENT twMaxOff (#PCDATA)>
+<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
+<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
+<!ELEMENT twTIGName (#PCDATA)>
+<!ELEMENT twInstantiated (#PCDATA)>
+<!ELEMENT twBlocked (#PCDATA)>
+<!ELEMENT twRacePathRpt (twRacePath+)>
+<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
+<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
+<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
+						twSimpleMinPath CDATA #IMPLIED>
+<!ELEMENT twTotDel (#PCDATA)>
+<!ELEMENT twSrc (#PCDATA)>
+<!ATTLIST twSrc BELType CDATA #IMPLIED>
+<!ELEMENT twDest (#PCDATA)>
+<!ATTLIST twDest BELType CDATA #IMPLIED>
+<!ELEMENT twDel (#PCDATA)>
+<!ELEMENT twSUTime (#PCDATA)>
+<!ELEMENT twTotPathDel (#PCDATA)>
+<!ELEMENT twClkSkew (#PCDATA)>
+<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
+<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
+<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
+<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
+<!ELEMENT twSlack (#PCDATA)>
+<!ELEMENT twDelConst (#PCDATA)>
+<!ELEMENT tw2Phase EMPTY>
+<!ELEMENT twClkUncert (#PCDATA)>
+<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
+					  fDCMJit CDATA #IMPLIED
+					  fPhaseErr CDATA #IMPLIED
+					  sEqu CDATA #IMPLIED>
+<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
+<!ELEMENT twPathRptBanner (#PCDATA)>
+<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
+<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
+<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
+<!ELEMENT twOff (#PCDATA)>
+<!ELEMENT twGuaranteed EMPTY>
+<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
+<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
+<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
+<!ELEMENT twClkDel (#PCDATA)>
+<!ELEMENT twClkSrc (#PCDATA)>
+<!ELEMENT twClkDest (#PCDATA)>
+<!ELEMENT twGuarInSetup (#PCDATA)>
+<!ELEMENT twOffSrc (#PCDATA)>
+<!ELEMENT twOffDest (#PCDATA)>
+<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
+<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
+<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
+<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
+<!ELEMENT twDataDel (#PCDATA)>
+<!ELEMENT twDataSrc (#PCDATA)>
+<!ELEMENT twDataDest (#PCDATA)>
+<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
+<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twLogLvls (#PCDATA)>
+<!ELEMENT twSrcSite (#PCDATA)>
+<!ELEMENT twSrcClk (#PCDATA)>
+<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
+<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
+<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
+<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
+<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
+<!ELEMENT twDelInfo (#PCDATA)>
+<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
+<!ELEMENT twSite (#PCDATA)>
+<!ELEMENT twDelType (#PCDATA)>
+<!ELEMENT twFanCnt (#PCDATA)>
+<!ELEMENT twComp (#PCDATA)>
+<!ELEMENT twNet (#PCDATA)>
+<!ELEMENT twBEL (#PCDATA)>
+<!ELEMENT twLogDel (#PCDATA)>
+<!ELEMENT twRouteDel (#PCDATA)>
+<!ELEMENT twDestClk (#PCDATA)>
+<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
+<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
+<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
+<!ELEMENT twPctLog (#PCDATA)>
+<!ELEMENT twPctRoute (#PCDATA)>
+<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
+<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
+<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
+<!ELEMENT twTimeConst (#PCDATA)>
+<!ELEMENT twAbsSlack (#PCDATA)>
+<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
+<!ELEMENT twSkew (#PCDATA)>
+<!ELEMENT twDetNet (twNetDel*)>
+<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
+<!ELEMENT twNetDelInfo (#PCDATA)>
+<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
+<!ELEMENT twDetSkewNet (twNetSkew*)>
+<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
+<!ELEMENT twClkSkewLimit  EMPTY>
+<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
+		         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
+<!ELEMENT twConstRollupTable (twConstRollup*)>
+<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
+<!ELEMENT twConstRollup  EMPTY>
+<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
+<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
+<!ELEMENT twConstList (twConstListItem)*>
+<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
+<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
+<!ELEMENT twNotMet EMPTY>
+<!ELEMENT twReqVal (#PCDATA)>
+<!ELEMENT twActVal (#PCDATA)>
+<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
+<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
+<!ELEMENT twConstStats (twConstName)>
+<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
+<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
+<!ATTLIST twConstStats twActual CDATA #IMPLIED>
+<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
+<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
+<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
+<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
+<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
+<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
+<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
+<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
+<!ELEMENT twConstData EMPTY>
+<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
+					  best CDATA #IMPLIED requested CDATA #IMPLIED
+					  errors CDATA #IMPLIED
+					  score CDATA #IMPLIED>
+<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
+<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
+<!ELEMENT twTimeGrpName (#PCDATA)>
+<!ELEMENT twCompList (twCompName+)>
+<!ELEMENT twCompName (#PCDATA)>
+<!ELEMENT twSigList (twSigName+)>
+<!ELEMENT twSigName (#PCDATA)>
+<!ELEMENT twBELList (twBELName+)>
+<!ELEMENT twBELName (#PCDATA)>
+<!ELEMENT twBlockList (twBlockName+)>
+<!ELEMENT twBlockName (#PCDATA)>
+<!ELEMENT twMacList (twMacName+)>
+<!ELEMENT twMacName (#PCDATA)>
+<!ELEMENT twPinList (twPinName+)>
+<!ELEMENT twPinName (#PCDATA)>
+<!ELEMENT twUnmetConstCnt (#PCDATA)>
+<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
+<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
+<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
+<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
+<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
+<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
+<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
+<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
+<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
+<!ELEMENT twSU2ClkTime (#PCDATA)>
+<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twH2ClkTime (#PCDATA)>
+<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
+<!ELEMENT twClk2Pad (twDest, twTime)>
+<!ELEMENT twTime (#PCDATA)>
+<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
+<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
+<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
+<!ELEMENT twClk2Out EMPTY>
+<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
+<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
+<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
+<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
+<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
+<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
+<!ELEMENT twRiseRise (#PCDATA)>
+<!ELEMENT twFallRise (#PCDATA)>
+<!ELEMENT twRiseFall (#PCDATA)>
+<!ELEMENT twFallFall (#PCDATA)>
+<!ELEMENT twPad2PadList (twPad2Pad+)>
+<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
+<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
+<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
+<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
+<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
+<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
+<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
+<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
+<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
+<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
+<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
+<!ELEMENT twOffOutTblRow EMPTY>
+<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
+<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
+<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
+<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
+<!ELEMENT twNonDedClk (#PCDATA)>
+<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
+<!ELEMENT twScore (#PCDATA)>
+<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
+<!ELEMENT twPathCnt (#PCDATA)>
+<!ELEMENT twNetCnt (#PCDATA)>
+<!ELEMENT twConnCnt (#PCDATA)>
+<!ELEMENT twPct (#PCDATA)>
+<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
+<!ELEMENT twMaxCombDel (#PCDATA)>
+<!ELEMENT twMaxFromToDel (#PCDATA)>
+<!ELEMENT twMaxNetDel (#PCDATA)>
+<!ELEMENT twMaxNetSkew (#PCDATA)>
+<!ELEMENT twMaxInAfterClk (#PCDATA)>
+<!ELEMENT twMinInBeforeClk (#PCDATA)>
+<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
+<!ELEMENT twMinOutAfterClk (#PCDATA)>
+<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
+<!ELEMENT twTimestamp (#PCDATA)>
+<!ELEMENT twFootnoteExplanation EMPTY>
+<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
+<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
+<!ELEMENT twClientInfo (twClientName, twAttrList?)>
+<!ELEMENT twClientName (#PCDATA)>
+<!ELEMENT twAttrList (twAttrListItem)*>
+<!ELEMENT twAttrListItem (twName, twValue*)>
+<!ELEMENT twName (#PCDATA)>
+<!ELEMENT twValue (#PCDATA)>
+]>
+<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">NET &quot;CLK_BUFGP/IBUFG&quot; PERIOD = 31.25 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="27.555" best="3.695" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.418" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="4">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
diff --git a/led.stx b/led.stx
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/led.stx
diff --git a/led.syr b/led.syr
index 5e4ba5c..96c59cf 100644
--- a/led.syr
+++ b/led.syr
@@ -5,7 +5,7 @@ Parameter TMPDIR set to xst/projnav.tmp
 
 
 Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.03 secs
+Total CPU time to Xst completion: 0.02 secs
  
 --> 
 Parameter xsthdpdir set to xst
@@ -19,19 +19,24 @@ Reading design: led.prj
 
 TABLE OF CONTENTS
   1) Synthesis Options Summary
-  2) HDL Compilation
-  3) Design Hierarchy Analysis
-  4) HDL Analysis
-  5) HDL Synthesis
-     5.1) HDL Synthesis Report
-  6) Advanced HDL Synthesis
-     6.1) Advanced HDL Synthesis Report
-  7) Low Level Synthesis
-  8) Partition Report
-  9) Final Report
-	9.1) Device utilization summary
-	9.2) Partition Resource Summary
-	9.3) TIMING REPORT
+  2) HDL Parsing
+  3) HDL Elaboration
+  4) HDL Synthesis
+       4.1) HDL Synthesis Report
+  5) Advanced HDL Synthesis
+       5.1) Advanced HDL Synthesis Report
+  6) Low Level Synthesis
+  7) Partition Report
+  8) Design Summary
+       8.1) Primitive and Black Box Usage
+       8.2) Device utilization summary
+       8.3) Partition Resource Summary
+       8.4) Timing Report
+            8.4.1) Clock Information
+            8.4.2) Asynchronous Control Signals Information
+            8.4.3) Timing Summary
+            8.4.4) Timing Details
+            8.4.5) Cross Clock Domains Report
 
 
 =========================================================================
@@ -39,13 +44,12 @@ TABLE OF CONTENTS
 =========================================================================
 ---- Source Parameters
 Input File Name                    : "led.prj"
-Input Format                       : mixed
 Ignore Synthesis Constraint File   : NO
 
 ---- Target Parameters
 Output File Name                   : "led"
 Output Format                      : NGC
-Target Device                      : xc3s250e-4-vq100
+Target Device                      : xc6slx9-2-tqg144
 
 ---- Source Options
 Top Module Name                    : led
@@ -56,35 +60,32 @@ FSM Style                          : LUT
 RAM Extraction                     : Yes
 RAM Style                          : Auto
 ROM Extraction                     : Yes
-Mux Style                          : Auto
-Decoder Extraction                 : YES
-Priority Encoder Extraction        : Yes
 Shift Register Extraction          : YES
-Logical Shifter Extraction         : YES
-XOR Collapsing                     : YES
 ROM Style                          : Auto
-Mux Extraction                     : Yes
 Resource Sharing                   : YES
 Asynchronous To Synchronous        : NO
-Multiplier Style                   : Auto
+Shift Register Minimum Size        : 2
+Use DSP Block                      : Auto
 Automatic Register Balancing       : No
 
 ---- Target Options
+LUT Combining                      : Auto
+Reduce Control Sets                : Auto
 Add IO Buffers                     : YES
-Global Maximum Fanout              : 500
-Add Generic Clock Buffer(BUFG)     : 24
+Global Maximum Fanout              : 100000
+Add Generic Clock Buffer(BUFG)     : 16
 Register Duplication               : YES
-Slice Packing                      : YES
 Optimize Instantiated Primitives   : NO
-Use Clock Enable                   : Yes
-Use Synchronous Set                : Yes
-Use Synchronous Reset              : Yes
+Use Clock Enable                   : Auto
+Use Synchronous Set                : Auto
+Use Synchronous Reset              : Auto
 Pack IO Registers into IOBs        : Auto
 Equivalent register Removal        : YES
 
 ---- General Options
 Optimization Goal                  : Speed
 Optimization Effort                : 1
+Power Reduction                    : NO
 Keep Hierarchy                     : No
 Netlist Hierarchy                  : As_Optimized
 RTL Output                         : Yes
@@ -97,7 +98,7 @@ Bus Delimiter                      : <>
 Case Specifier                     : Maintain
 Slice Utilization Ratio            : 100
 BRAM Utilization Ratio             : 100
-Verilog 2001                       : YES
+DSP48 Utilization Ratio            : 100
 Auto BRAM Packing                  : NO
 Slice Utilization Ratio Delta      : 5
 
@@ -105,24 +106,275 @@ Slice Utilization Ratio Delta      : 5
 
 
 =========================================================================
-*                          HDL Compilation                              *
+*                          HDL Parsing                                  *
+=========================================================================
+Analyzing Verilog file "/home/yannherklotz/Github/FPGA-led-lights/led.v" into library work
+Parsing module <led>.
+
+=========================================================================
+*                            HDL Elaboration                            *
+=========================================================================
+
+Elaborating module <led>.
+
+=========================================================================
+*                           HDL Synthesis                               *
+=========================================================================
+
+Synthesizing Unit <led>.
+    Related source file is "/home/yannherklotz/Github/FPGA-led-lights/led.v".
+    Found 27-bit register for signal <count>.
+    Found 1-bit register for signal <LED1>.
+    Found 27-bit subtractor for signal <count[26]_GND_1_o_sub_3_OUT> created at line 41.
+    Summary:
+	inferred   1 Adder/Subtractor(s).
+	inferred  28 D-type flip-flop(s).
+Unit <led> synthesized.
+
+=========================================================================
+HDL Synthesis Report
+
+Macro Statistics
+# Adders/Subtractors                                   : 1
+ 27-bit subtractor                                     : 1
+# Registers                                            : 2
+ 1-bit register                                        : 1
+ 27-bit register                                       : 1
+
+=========================================================================
+
+=========================================================================
+*                       Advanced HDL Synthesis                          *
+=========================================================================
+
+
+Synthesizing (advanced) Unit <led>.
+The following registers are absorbed into counter <count>: 1 register on signal <count>.
+Unit <led> synthesized (advanced).
+
+=========================================================================
+Advanced HDL Synthesis Report
+
+Macro Statistics
+# Counters                                             : 1
+ 27-bit down counter                                   : 1
+# Registers                                            : 1
+ Flip-Flops                                            : 1
+
+=========================================================================
+
+=========================================================================
+*                         Low Level Synthesis                           *
+=========================================================================
+
+Optimizing unit <led> ...
+WARNING:Xst:1293 - FF/Latch <count_26> has a constant value of 0 in block <led>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <count_24> has a constant value of 0 in block <led>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <count_25> has a constant value of 0 in block <led>. This FF/Latch will be trimmed during the optimization process.
+
+Mapping all equations...
+Building and optimizing final netlist ...
+Found area constraint ratio of 100 (+ 5) on block led, actual ratio is 0.
+
+Final Macro Processing ...
+
+=========================================================================
+Final Register Report
+
+Macro Statistics
+# Registers                                            : 25
+ Flip-Flops                                            : 25
+
+=========================================================================
+
+=========================================================================
+*                           Partition Report                            *
 =========================================================================
-Compiling verilog file "led.v" in library work
-Module <led> compiled
-No errors in compilation
-Analysis of file <"led.prj"> succeeded.
- 
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
 
 =========================================================================
-*                     Design Hierarchy Analysis                         *
+*                            Design Summary                             *
+=========================================================================
+
+Top Level Output File Name         : led.ngc
+
+Primitive and Black Box Usage:
+------------------------------
+# BELS                             : 106
+#      GND                         : 1
+#      INV                         : 23
+#      LUT1                        : 1
+#      LUT5                        : 25
+#      LUT6                        : 8
+#      MUXCY                       : 23
+#      VCC                         : 1
+#      XORCY                       : 24
+# FlipFlops/Latches                : 25
+#      FD                          : 25
+# Clock Buffers                    : 1
+#      BUFGP                       : 1
+# IO Buffers                       : 1
+#      OBUF                        : 1
+
+Device utilization summary:
+---------------------------
+
+Selected Device : 6slx9tqg144-2 
+
+
+Slice Logic Utilization: 
+ Number of Slice Registers:              25  out of  11440     0%  
+ Number of Slice LUTs:                   57  out of   5720     0%  
+    Number used as Logic:                57  out of   5720     0%  
+
+Slice Logic Distribution: 
+ Number of LUT Flip Flop pairs used:     57
+   Number with an unused Flip Flop:      32  out of     57    56%  
+   Number with an unused LUT:             0  out of     57     0%  
+   Number of fully used LUT-FF pairs:    25  out of     57    43%  
+   Number of unique control sets:         1
+
+IO Utilization: 
+ Number of IOs:                           2
+ Number of bonded IOBs:                   2  out of    102     1%  
+
+Specific Feature Utilization:
+ Number of BUFG/BUFGCTRLs:                1  out of     16     6%  
+
+---------------------------
+Partition Resource Summary:
+---------------------------
+
+  No Partitions were found in this design.
+
+---------------------------
+
+
 =========================================================================
-ERROR:Xst - "led.v" line 21: Module <led> has no port.
+Timing Report
+
+NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
+      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
+      GENERATED AFTER PLACE-and-ROUTE.
+
+Clock Information:
+------------------
+-----------------------------------+------------------------+-------+
+Clock Signal                       | Clock buffer(FF name)  | Load  |
+-----------------------------------+------------------------+-------+
+CLK                                | BUFGP                  | 25    |
+-----------------------------------+------------------------+-------+
+
+Asynchronous Control Signals Information:
+----------------------------------------
+No asynchronous control signals found in this design
+
+Timing Summary:
+---------------
+Speed Grade: -2
+
+   Minimum period: 3.825ns (Maximum Frequency: 261.472MHz)
+   Minimum input arrival time before clock: No path found
+   Maximum output required time after clock: 4.162ns
+   Maximum combinational path delay: No path found
+
+Timing Details:
+---------------
+All values displayed in nanoseconds (ns)
+
+=========================================================================
+Timing constraint: Default period analysis for Clock 'CLK'
+  Clock period: 3.825ns (frequency: 261.472MHz)
+  Total number of paths / destination ports: 901 / 25
+-------------------------------------------------------------------------
+Delay:               3.825ns (Levels of Logic = 22)
+  Source:            count_0 (FF)
+  Destination:       count_19 (FF)
+  Source Clock:      CLK rising
+  Destination Clock: CLK rising
+
+  Data Path: count_0 to count_19
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FD:C->Q               3   0.525   0.766  count_0 (count_0)
+     LUT1:I0->O            1   0.254   0.000  Mcount_count_cy<0>_rt (Mcount_count_cy<0>_rt)
+     MUXCY:S->O            1   0.215   0.000  Mcount_count_cy<0> (Mcount_count_cy<0>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<1> (Mcount_count_cy<1>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<2> (Mcount_count_cy<2>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<3> (Mcount_count_cy<3>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<4> (Mcount_count_cy<4>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<5> (Mcount_count_cy<5>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<6> (Mcount_count_cy<6>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<7> (Mcount_count_cy<7>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<8> (Mcount_count_cy<8>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<9> (Mcount_count_cy<9>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<10> (Mcount_count_cy<10>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<11> (Mcount_count_cy<11>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<12> (Mcount_count_cy<12>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<13> (Mcount_count_cy<13>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<14> (Mcount_count_cy<14>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<15> (Mcount_count_cy<15>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<16> (Mcount_count_cy<16>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<17> (Mcount_count_cy<17>)
+     MUXCY:CI->O           1   0.023   0.000  Mcount_count_cy<18> (Mcount_count_cy<18>)
+     XORCY:CI->O           1   0.206   1.112  Mcount_count_xor<19> (Result<19>)
+     LUT5:I0->O            1   0.254   0.000  count_19_rstpot (count_19_rstpot)
+     FD:D                      0.074          count_19
+    ----------------------------------------
+    Total                      3.825ns (1.947ns logic, 1.878ns route)
+                                       (50.9% logic, 49.1% route)
+
+=========================================================================
+Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
+  Total number of paths / destination ports: 1 / 1
+-------------------------------------------------------------------------
+Offset:              4.162ns (Levels of Logic = 1)
+  Source:            LED1 (FF)
+  Destination:       LED1 (PAD)
+  Source Clock:      CLK rising
+
+  Data Path: LED1 to LED1
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FD:C->Q               2   0.525   0.725  LED1 (LED1_OBUF)
+     OBUF:I->O                 2.912          LED1_OBUF (LED1)
+    ----------------------------------------
+    Total                      4.162ns (3.437ns logic, 0.725ns route)
+                                       (82.6% logic, 17.4% route)
+
+=========================================================================
+
+Cross Clock Domains Report:
+--------------------------
+
+Clock to Setup on destination clock CLK
+---------------+---------+---------+---------+---------+
+               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
+Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
+---------------+---------+---------+---------+---------+
+CLK            |    3.825|         |         |         |
+---------------+---------+---------+---------+---------+
+
+=========================================================================
+
+
+Total REAL time to Xst completion: 4.00 secs
+Total CPU time to Xst completion: 4.11 secs
+ 
 --> 
 
 
-Total memory usage is 497212 kilobytes
+Total memory usage is 382892 kilobytes
 
-Number of errors   :    1 (   0 filtered)
-Number of warnings :    0 (   0 filtered)
+Number of errors   :    0 (   0 filtered)
+Number of warnings :    3 (   0 filtered)
 Number of infos    :    0 (   0 filtered)
 
diff --git a/led.twr b/led.twr
new file mode 100644
index 0000000..e2916b0
--- /dev/null
+++ b/led.twr
@@ -0,0 +1,670 @@
+--------------------------------------------------------------------------------
+Release 14.7 Trace  (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 2 -n
+3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf -ucf
+BPC3011-Papilio_Pro-general.ucf
+
+Design file:              led.ncd
+Physical constraint file: led.pcf
+Device,package,speed:     xc6slx9,tqg144,C,-2 (PRODUCTION 1.23 2013-10-13)
+Report level:             verbose report
+
+Environment Variable      Effect 
+--------------------      ------ 
+NONE                      No environment variables were set
+--------------------------------------------------------------------------------
+
+INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
+INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
+   option. All paths that are not constrained will be reported in the 
+   unconstrained paths section(s) of the report.
+INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
+   a 50 Ohm transmission line loading model.  For the details of this model, 
+   and for more information on accounting for different loading conditions, 
+   please see the device datasheet.
+
+================================================================================
+Timing constraint: NET "CLK_BUFGP/IBUFG" PERIOD = 31.25 ns HIGH 50%;
+For more information, see Period Analysis in the Timing Closure User Guide (UG612).
+
+ 901 paths analyzed, 125 endpoints analyzed, 0 failing endpoints
+ 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
+ Minimum period is   3.695ns.
+--------------------------------------------------------------------------------
+
+Paths for end point count_1 (SLICE_X13Y38.B1), 6 paths
+--------------------------------------------------------------------------------
+Slack (setup path):     27.555ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               count_9 (FF)
+  Destination:          count_1 (FF)
+  Requirement:          31.250ns
+  Data Path Delay:      3.645ns (Levels of Logic = 2)
+  Clock Path Skew:      -0.015ns (0.285 - 0.300)
+  Source Clock:         CLK_BUFGP rising at 0.000ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.035ns
+
+  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.000ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: count_9 to count_1
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X13Y40.BQ      Tcko                  0.430   count<11>
+                                                       count_9
+    SLICE_X14Y41.B3      net (fanout=3)        1.341   count<9>
+    SLICE_X14Y41.B       Tilo                  0.235   LED1_OBUF
+                                                       count[26]_GND_1_o_equal_2_o<26>4
+    SLICE_X13Y38.B1      net (fanout=19)       1.266   count[26]_GND_1_o_equal_2_o<26>3
+    SLICE_X13Y38.CLK     Tas                   0.373   count<3>
+                                                       count_1_rstpot
+                                                       count_1
+    -------------------------------------------------  ---------------------------
+    Total                                      3.645ns (1.038ns logic, 2.607ns route)
+                                                       (28.5% logic, 71.5% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path):     27.760ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               count_10 (FF)
+  Destination:          count_1 (FF)
+  Requirement:          31.250ns
+  Data Path Delay:      3.440ns (Levels of Logic = 2)
+  Clock Path Skew:      -0.015ns (0.285 - 0.300)
+  Source Clock:         CLK_BUFGP rising at 0.000ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.035ns
+
+  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.000ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: count_10 to count_1
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X13Y40.CQ      Tcko                  0.430   count<11>
+                                                       count_10
+    SLICE_X14Y41.B1      net (fanout=3)        1.136   count<10>
+    SLICE_X14Y41.B       Tilo                  0.235   LED1_OBUF
+                                                       count[26]_GND_1_o_equal_2_o<26>4
+    SLICE_X13Y38.B1      net (fanout=19)       1.266   count[26]_GND_1_o_equal_2_o<26>3
+    SLICE_X13Y38.CLK     Tas                   0.373   count<3>
+                                                       count_1_rstpot
+                                                       count_1
+    -------------------------------------------------  ---------------------------
+    Total                                      3.440ns (1.038ns logic, 2.402ns route)
+                                                       (30.2% logic, 69.8% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path):     27.948ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               count_11 (FF)
+  Destination:          count_1 (FF)
+  Requirement:          31.250ns
+  Data Path Delay:      3.252ns (Levels of Logic = 2)
+  Clock Path Skew:      -0.015ns (0.285 - 0.300)
+  Source Clock:         CLK_BUFGP rising at 0.000ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.035ns
+
+  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.000ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: count_11 to count_1
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X13Y40.DQ      Tcko                  0.430   count<11>
+                                                       count_11
+    SLICE_X14Y41.B2      net (fanout=3)        0.948   count<11>
+    SLICE_X14Y41.B       Tilo                  0.235   LED1_OBUF
+                                                       count[26]_GND_1_o_equal_2_o<26>4
+    SLICE_X13Y38.B1      net (fanout=19)       1.266   count[26]_GND_1_o_equal_2_o<26>3
+    SLICE_X13Y38.CLK     Tas                   0.373   count<3>
+                                                       count_1_rstpot
+                                                       count_1
+    -------------------------------------------------  ---------------------------
+    Total                                      3.252ns (1.038ns logic, 2.214ns route)
+                                                       (31.9% logic, 68.1% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point count_7 (SLICE_X13Y39.D2), 6 paths
+--------------------------------------------------------------------------------
+Slack (setup path):     27.560ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               count_9 (FF)
+  Destination:          count_7 (FF)
+  Requirement:          31.250ns
+  Data Path Delay:      3.638ns (Levels of Logic = 2)
+  Clock Path Skew:      -0.017ns (0.283 - 0.300)
+  Source Clock:         CLK_BUFGP rising at 0.000ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.035ns
+
+  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.000ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: count_9 to count_7
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X13Y40.BQ      Tcko                  0.430   count<11>
+                                                       count_9
+    SLICE_X14Y41.B3      net (fanout=3)        1.341   count<9>
+    SLICE_X14Y41.B       Tilo                  0.235   LED1_OBUF
+                                                       count[26]_GND_1_o_equal_2_o<26>4
+    SLICE_X13Y39.D2      net (fanout=19)       1.259   count[26]_GND_1_o_equal_2_o<26>3
+    SLICE_X13Y39.CLK     Tas                   0.373   count<7>
+                                                       count_7_rstpot
+                                                       count_7
+    -------------------------------------------------  ---------------------------
+    Total                                      3.638ns (1.038ns logic, 2.600ns route)
+                                                       (28.5% logic, 71.5% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path):     27.765ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               count_10 (FF)
+  Destination:          count_7 (FF)
+  Requirement:          31.250ns
+  Data Path Delay:      3.433ns (Levels of Logic = 2)
+  Clock Path Skew:      -0.017ns (0.283 - 0.300)
+  Source Clock:         CLK_BUFGP rising at 0.000ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.035ns
+
+  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.000ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: count_10 to count_7
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X13Y40.CQ      Tcko                  0.430   count<11>
+                                                       count_10
+    SLICE_X14Y41.B1      net (fanout=3)        1.136   count<10>
+    SLICE_X14Y41.B       Tilo                  0.235   LED1_OBUF
+                                                       count[26]_GND_1_o_equal_2_o<26>4
+    SLICE_X13Y39.D2      net (fanout=19)       1.259   count[26]_GND_1_o_equal_2_o<26>3
+    SLICE_X13Y39.CLK     Tas                   0.373   count<7>
+                                                       count_7_rstpot
+                                                       count_7
+    -------------------------------------------------  ---------------------------
+    Total                                      3.433ns (1.038ns logic, 2.395ns route)
+                                                       (30.2% logic, 69.8% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path):     27.953ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               count_11 (FF)
+  Destination:          count_7 (FF)
+  Requirement:          31.250ns
+  Data Path Delay:      3.245ns (Levels of Logic = 2)
+  Clock Path Skew:      -0.017ns (0.283 - 0.300)
+  Source Clock:         CLK_BUFGP rising at 0.000ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.035ns
+
+  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.000ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: count_11 to count_7
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X13Y40.DQ      Tcko                  0.430   count<11>
+                                                       count_11
+    SLICE_X14Y41.B2      net (fanout=3)        0.948   count<11>
+    SLICE_X14Y41.B       Tilo                  0.235   LED1_OBUF
+                                                       count[26]_GND_1_o_equal_2_o<26>4
+    SLICE_X13Y39.D2      net (fanout=19)       1.259   count[26]_GND_1_o_equal_2_o<26>3
+    SLICE_X13Y39.CLK     Tas                   0.373   count<7>
+                                                       count_7_rstpot
+                                                       count_7
+    -------------------------------------------------  ---------------------------
+    Total                                      3.245ns (1.038ns logic, 2.207ns route)
+                                                       (32.0% logic, 68.0% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point count_23 (SLICE_X13Y41.A1), 24 paths
+--------------------------------------------------------------------------------
+Slack (setup path):     27.618ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               count_1 (FF)
+  Destination:          count_23 (FF)
+  Requirement:          31.250ns
+  Data Path Delay:      3.580ns (Levels of Logic = 7)
+  Clock Path Skew:      -0.017ns (0.285 - 0.302)
+  Source Clock:         CLK_BUFGP rising at 0.000ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.035ns
+
+  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.000ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: count_1 to count_23
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X13Y38.BQ      Tcko                  0.430   count<3>
+                                                       count_1
+    SLICE_X12Y38.B1      net (fanout=3)        0.730   count<1>
+    SLICE_X12Y38.COUT    Topcyb                0.483   Mcount_count_cy<3>
+                                                       Mcount_count_lut<1>_INV_0
+                                                       Mcount_count_cy<3>
+    SLICE_X12Y39.CIN     net (fanout=1)        0.003   Mcount_count_cy<3>
+    SLICE_X12Y39.COUT    Tbyp                  0.093   Mcount_count_cy<7>
+                                                       Mcount_count_cy<7>
+    SLICE_X12Y40.CIN     net (fanout=1)        0.082   Mcount_count_cy<7>
+    SLICE_X12Y40.COUT    Tbyp                  0.093   Mcount_count_cy<11>
+                                                       Mcount_count_cy<11>
+    SLICE_X12Y41.CIN     net (fanout=1)        0.003   Mcount_count_cy<11>
+    SLICE_X12Y41.COUT    Tbyp                  0.093   Mcount_count_cy<15>
+                                                       Mcount_count_cy<15>
+    SLICE_X12Y42.CIN     net (fanout=1)        0.003   Mcount_count_cy<15>
+    SLICE_X12Y42.COUT    Tbyp                  0.093   Mcount_count_cy<19>
+                                                       Mcount_count_cy<19>
+    SLICE_X12Y43.CIN     net (fanout=1)        0.003   Mcount_count_cy<19>
+    SLICE_X12Y43.DMUX    Tcind                 0.320   Result<23>
+                                                       Mcount_count_xor<23>
+    SLICE_X13Y41.A1      net (fanout=1)        0.778   Result<23>
+    SLICE_X13Y41.CLK     Tas                   0.373   count<23>
+                                                       count_23_rstpot
+                                                       count_23
+    -------------------------------------------------  ---------------------------
+    Total                                      3.580ns (1.978ns logic, 1.602ns route)
+                                                       (55.3% logic, 44.7% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path):     27.628ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               count_0 (FF)
+  Destination:          count_23 (FF)
+  Requirement:          31.250ns
+  Data Path Delay:      3.570ns (Levels of Logic = 7)
+  Clock Path Skew:      -0.017ns (0.285 - 0.302)
+  Source Clock:         CLK_BUFGP rising at 0.000ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.035ns
+
+  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.000ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: count_0 to count_23
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X13Y38.AQ      Tcko                  0.430   count<3>
+                                                       count_0
+    SLICE_X12Y38.A2      net (fanout=3)        0.729   count<0>
+    SLICE_X12Y38.COUT    Topcya                0.474   Mcount_count_cy<3>
+                                                       count<0>_rt
+                                                       Mcount_count_cy<3>
+    SLICE_X12Y39.CIN     net (fanout=1)        0.003   Mcount_count_cy<3>
+    SLICE_X12Y39.COUT    Tbyp                  0.093   Mcount_count_cy<7>
+                                                       Mcount_count_cy<7>
+    SLICE_X12Y40.CIN     net (fanout=1)        0.082   Mcount_count_cy<7>
+    SLICE_X12Y40.COUT    Tbyp                  0.093   Mcount_count_cy<11>
+                                                       Mcount_count_cy<11>
+    SLICE_X12Y41.CIN     net (fanout=1)        0.003   Mcount_count_cy<11>
+    SLICE_X12Y41.COUT    Tbyp                  0.093   Mcount_count_cy<15>
+                                                       Mcount_count_cy<15>
+    SLICE_X12Y42.CIN     net (fanout=1)        0.003   Mcount_count_cy<15>
+    SLICE_X12Y42.COUT    Tbyp                  0.093   Mcount_count_cy<19>
+                                                       Mcount_count_cy<19>
+    SLICE_X12Y43.CIN     net (fanout=1)        0.003   Mcount_count_cy<19>
+    SLICE_X12Y43.DMUX    Tcind                 0.320   Result<23>
+                                                       Mcount_count_xor<23>
+    SLICE_X13Y41.A1      net (fanout=1)        0.778   Result<23>
+    SLICE_X13Y41.CLK     Tas                   0.373   count<23>
+                                                       count_23_rstpot
+                                                       count_23
+    -------------------------------------------------  ---------------------------
+    Total                                      3.570ns (1.969ns logic, 1.601ns route)
+                                                       (55.2% logic, 44.8% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path):     27.639ns (requirement - (data path - clock path skew + uncertainty))
+  Source:               count_5 (FF)
+  Destination:          count_23 (FF)
+  Requirement:          31.250ns
+  Data Path Delay:      3.561ns (Levels of Logic = 6)
+  Clock Path Skew:      -0.015ns (0.285 - 0.300)
+  Source Clock:         CLK_BUFGP rising at 0.000ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.035ns
+
+  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter (TSJ):  0.070ns
+    Total Input Jitter (TIJ):   0.000ns
+    Discrete Jitter (DJ):       0.000ns
+    Phase Error (PE):           0.000ns
+
+  Maximum Data Path at Slow Process Corner: count_5 to count_23
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X13Y39.BQ      Tcko                  0.430   count<7>
+                                                       count_5
+    SLICE_X12Y39.B1      net (fanout=3)        0.807   count<5>
+    SLICE_X12Y39.COUT    Topcyb                0.483   Mcount_count_cy<7>
+                                                       Mcount_count_lut<5>_INV_0
+                                                       Mcount_count_cy<7>
+    SLICE_X12Y40.CIN     net (fanout=1)        0.082   Mcount_count_cy<7>
+    SLICE_X12Y40.COUT    Tbyp                  0.093   Mcount_count_cy<11>
+                                                       Mcount_count_cy<11>
+    SLICE_X12Y41.CIN     net (fanout=1)        0.003   Mcount_count_cy<11>
+    SLICE_X12Y41.COUT    Tbyp                  0.093   Mcount_count_cy<15>
+                                                       Mcount_count_cy<15>
+    SLICE_X12Y42.CIN     net (fanout=1)        0.003   Mcount_count_cy<15>
+    SLICE_X12Y42.COUT    Tbyp                  0.093   Mcount_count_cy<19>
+                                                       Mcount_count_cy<19>
+    SLICE_X12Y43.CIN     net (fanout=1)        0.003   Mcount_count_cy<19>
+    SLICE_X12Y43.DMUX    Tcind                 0.320   Result<23>
+                                                       Mcount_count_xor<23>
+    SLICE_X13Y41.A1      net (fanout=1)        0.778   Result<23>
+    SLICE_X13Y41.CLK     Tas                   0.373   count<23>
+                                                       count_23_rstpot
+                                                       count_23
+    -------------------------------------------------  ---------------------------
+    Total                                      3.561ns (1.885ns logic, 1.676ns route)
+                                                       (52.9% logic, 47.1% route)
+
+--------------------------------------------------------------------------------
+
+Hold Paths: NET "CLK_BUFGP/IBUFG" PERIOD = 31.25 ns HIGH 50%;
+--------------------------------------------------------------------------------
+
+Paths for end point LED1 (SLICE_X14Y41.A6), 1 path
+--------------------------------------------------------------------------------
+Slack (hold path):      0.418ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               LED1 (FF)
+  Destination:          LED1 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.418ns (Levels of Logic = 1)
+  Clock Path Skew:      0.000ns
+  Source Clock:         CLK_BUFGP rising at 31.250ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: LED1 to LED1
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X14Y41.AQ      Tcko                  0.200   LED1_OBUF
+                                                       LED1
+    SLICE_X14Y41.A6      net (fanout=2)        0.028   LED1_OBUF
+    SLICE_X14Y41.CLK     Tah         (-Th)    -0.190   LED1_OBUF
+                                                       LED1_rstpot
+                                                       LED1
+    -------------------------------------------------  ---------------------------
+    Total                                      0.418ns (0.390ns logic, 0.028ns route)
+                                                       (93.3% logic, 6.7% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point count_12 (SLICE_X15Y41.A6), 6 paths
+--------------------------------------------------------------------------------
+Slack (hold path):      0.689ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               count_14 (FF)
+  Destination:          count_12 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.689ns (Levels of Logic = 2)
+  Clock Path Skew:      0.000ns
+  Source Clock:         CLK_BUFGP rising at 31.250ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: count_14 to count_12
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X15Y41.DQ      Tcko                  0.198   count<14>
+                                                       count_14
+    SLICE_X14Y41.C6      net (fanout=3)        0.032   count<14>
+    SLICE_X14Y41.C       Tilo                  0.142   LED1_OBUF
+                                                       count[26]_GND_1_o_equal_2_o<26>1
+    SLICE_X15Y41.A6      net (fanout=13)       0.102   count[26]_GND_1_o_equal_2_o<26>
+    SLICE_X15Y41.CLK     Tah         (-Th)    -0.215   count<14>
+                                                       count_12_rstpot
+                                                       count_12
+    -------------------------------------------------  ---------------------------
+    Total                                      0.689ns (0.555ns logic, 0.134ns route)
+                                                       (80.6% logic, 19.4% route)
+
+--------------------------------------------------------------------------------
+Slack (hold path):      0.829ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               count_17 (FF)
+  Destination:          count_12 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.829ns (Levels of Logic = 2)
+  Clock Path Skew:      0.000ns
+  Source Clock:         CLK_BUFGP rising at 31.250ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: count_17 to count_12
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X15Y42.CQ      Tcko                  0.198   count<18>
+                                                       count_17
+    SLICE_X14Y41.C5      net (fanout=3)        0.172   count<17>
+    SLICE_X14Y41.C       Tilo                  0.142   LED1_OBUF
+                                                       count[26]_GND_1_o_equal_2_o<26>1
+    SLICE_X15Y41.A6      net (fanout=13)       0.102   count[26]_GND_1_o_equal_2_o<26>
+    SLICE_X15Y41.CLK     Tah         (-Th)    -0.215   count<14>
+                                                       count_12_rstpot
+                                                       count_12
+    -------------------------------------------------  ---------------------------
+    Total                                      0.829ns (0.555ns logic, 0.274ns route)
+                                                       (66.9% logic, 33.1% route)
+
+--------------------------------------------------------------------------------
+Slack (hold path):      0.881ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               count_15 (FF)
+  Destination:          count_12 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.881ns (Levels of Logic = 2)
+  Clock Path Skew:      0.000ns
+  Source Clock:         CLK_BUFGP rising at 31.250ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: count_15 to count_12
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X15Y42.AQ      Tcko                  0.198   count<18>
+                                                       count_15
+    SLICE_X14Y41.C4      net (fanout=3)        0.224   count<15>
+    SLICE_X14Y41.C       Tilo                  0.142   LED1_OBUF
+                                                       count[26]_GND_1_o_equal_2_o<26>1
+    SLICE_X15Y41.A6      net (fanout=13)       0.102   count[26]_GND_1_o_equal_2_o<26>
+    SLICE_X15Y41.CLK     Tah         (-Th)    -0.215   count<14>
+                                                       count_12_rstpot
+                                                       count_12
+    -------------------------------------------------  ---------------------------
+    Total                                      0.881ns (0.555ns logic, 0.326ns route)
+                                                       (63.0% logic, 37.0% route)
+
+--------------------------------------------------------------------------------
+
+Paths for end point LED1 (SLICE_X14Y41.A1), 6 paths
+--------------------------------------------------------------------------------
+Slack (hold path):      0.812ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               count_14 (FF)
+  Destination:          LED1 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.814ns (Levels of Logic = 2)
+  Clock Path Skew:      0.002ns (0.033 - 0.031)
+  Source Clock:         CLK_BUFGP rising at 31.250ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: count_14 to LED1
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X15Y41.DQ      Tcko                  0.198   count<14>
+                                                       count_14
+    SLICE_X14Y41.C6      net (fanout=3)        0.032   count<14>
+    SLICE_X14Y41.C       Tilo                  0.142   LED1_OBUF
+                                                       count[26]_GND_1_o_equal_2_o<26>1
+    SLICE_X14Y41.A1      net (fanout=13)       0.252   count[26]_GND_1_o_equal_2_o<26>
+    SLICE_X14Y41.CLK     Tah         (-Th)    -0.190   LED1_OBUF
+                                                       LED1_rstpot
+                                                       LED1
+    -------------------------------------------------  ---------------------------
+    Total                                      0.814ns (0.530ns logic, 0.284ns route)
+                                                       (65.1% logic, 34.9% route)
+
+--------------------------------------------------------------------------------
+Slack (hold path):      0.954ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               count_17 (FF)
+  Destination:          LED1 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      0.954ns (Levels of Logic = 2)
+  Clock Path Skew:      0.000ns
+  Source Clock:         CLK_BUFGP rising at 31.250ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: count_17 to LED1
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X15Y42.CQ      Tcko                  0.198   count<18>
+                                                       count_17
+    SLICE_X14Y41.C5      net (fanout=3)        0.172   count<17>
+    SLICE_X14Y41.C       Tilo                  0.142   LED1_OBUF
+                                                       count[26]_GND_1_o_equal_2_o<26>1
+    SLICE_X14Y41.A1      net (fanout=13)       0.252   count[26]_GND_1_o_equal_2_o<26>
+    SLICE_X14Y41.CLK     Tah         (-Th)    -0.190   LED1_OBUF
+                                                       LED1_rstpot
+                                                       LED1
+    -------------------------------------------------  ---------------------------
+    Total                                      0.954ns (0.530ns logic, 0.424ns route)
+                                                       (55.6% logic, 44.4% route)
+
+--------------------------------------------------------------------------------
+Slack (hold path):      1.006ns (requirement - (clock path skew + uncertainty - data path))
+  Source:               count_15 (FF)
+  Destination:          LED1 (FF)
+  Requirement:          0.000ns
+  Data Path Delay:      1.006ns (Levels of Logic = 2)
+  Clock Path Skew:      0.000ns
+  Source Clock:         CLK_BUFGP rising at 31.250ns
+  Destination Clock:    CLK_BUFGP rising at 31.250ns
+  Clock Uncertainty:    0.000ns
+
+  Minimum Data Path at Fast Process Corner: count_15 to LED1
+    Location             Delay type         Delay(ns)  Physical Resource
+                                                       Logical Resource(s)
+    -------------------------------------------------  -------------------
+    SLICE_X15Y42.AQ      Tcko                  0.198   count<18>
+                                                       count_15
+    SLICE_X14Y41.C4      net (fanout=3)        0.224   count<15>
+    SLICE_X14Y41.C       Tilo                  0.142   LED1_OBUF
+                                                       count[26]_GND_1_o_equal_2_o<26>1
+    SLICE_X14Y41.A1      net (fanout=13)       0.252   count[26]_GND_1_o_equal_2_o<26>
+    SLICE_X14Y41.CLK     Tah         (-Th)    -0.190   LED1_OBUF
+                                                       LED1_rstpot
+                                                       LED1
+    -------------------------------------------------  ---------------------------
+    Total                                      1.006ns (0.530ns logic, 0.476ns route)
+                                                       (52.7% logic, 47.3% route)
+
+--------------------------------------------------------------------------------
+
+Component Switching Limit Checks: NET "CLK_BUFGP/IBUFG" PERIOD = 31.25 ns HIGH 50%;
+--------------------------------------------------------------------------------
+Slack: 28.584ns (period - min period limit)
+  Period: 31.250ns
+  Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
+  Physical resource: CLK_BUFGP/BUFG/I0
+  Logical resource: CLK_BUFGP/BUFG/I0
+  Location pin: BUFGMUX_X2Y2.I0
+  Clock network: CLK_BUFGP/IBUFG
+--------------------------------------------------------------------------------
+Slack: 30.775ns (period - min period limit)
+  Period: 31.250ns
+  Min period limit: 0.475ns (2105.263MHz) (Tcp)
+  Physical resource: LED1_OBUF/CLK
+  Logical resource: LED1/CK
+  Location pin: SLICE_X14Y41.CLK
+  Clock network: CLK_BUFGP
+--------------------------------------------------------------------------------
+Slack: 30.780ns (period - min period limit)
+  Period: 31.250ns
+  Min period limit: 0.470ns (2127.660MHz) (Tcp)
+  Physical resource: count<3>/CLK
+  Logical resource: count_0/CK
+  Location pin: SLICE_X13Y38.CLK
+  Clock network: CLK_BUFGP
+--------------------------------------------------------------------------------
+
+
+All constraints were met.
+
+
+Data Sheet report:
+-----------------
+All values displayed in nanoseconds (ns)
+
+Clock to Setup on destination clock CLK
+---------------+---------+---------+---------+---------+
+               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
+Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
+---------------+---------+---------+---------+---------+
+CLK            |    3.695|         |         |         |
+---------------+---------+---------+---------+---------+
+
+
+Timing summary:
+---------------
+
+Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)
+
+Constraints cover 901 paths, 0 nets, and 211 connections
+
+Design statistics:
+   Minimum period:   3.695ns{1}   (Maximum frequency: 270.636MHz)
+
+
+------------------------------------Footnotes-----------------------------------
+1)  The minimum period statistic assumes all single cycle delays.
+
+Analysis completed Tue Feb 21 22:17:03 2017 
+--------------------------------------------------------------------------------
+
+Trace Settings:
+-------------------------
+Trace Settings 
+
+Peak Memory Usage: 390 MB
+
+
+
diff --git a/led.twx b/led.twx
new file mode 100644
index 0000000..ddcae97
--- /dev/null
+++ b/led.twx
@@ -0,0 +1,346 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE twReport [
+<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
+					twDebug*, twFoot?, twClientInfo?)>
+<!ATTLIST twReport version CDATA "10,4">
+<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
+<!ELEMENT twExecVer (#PCDATA)>
+<!ELEMENT twCopyright (#PCDATA)>
+<!ELEMENT twCmdLine (#PCDATA)>
+<!ELEMENT twDesign (#PCDATA)>
+<!ELEMENT twPCF (#PCDATA)>
+<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
+<!ELEMENT twDevName (#PCDATA)>
+<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
+<!ELEMENT twSpeedGrade (#PCDATA)>
+<!ELEMENT twSpeedVer (#PCDATA)>
+<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
+<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
+<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
+<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
+<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
+<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
+<!ELEMENT twItemLimit (#PCDATA)>
+<!ELEMENT twUnconst EMPTY>
+<!ELEMENT twUnconstLimit (#PCDATA)>
+<!ELEMENT twEnvVar EMPTY>
+<!ATTLIST twEnvVar name CDATA #REQUIRED>
+<!ATTLIST twEnvVar description CDATA #REQUIRED>
+<!ELEMENT twWarn (#PCDATA)>
+<!ELEMENT twInfo (#PCDATA)>
+<!ELEMENT twDebug (#PCDATA)>
+<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
+<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
+<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
+<!ELEMENT twProc (#PCDATA)>
+<!ELEMENT twTemp (#PCDATA)>
+<!ELEMENT twVolt (#PCDATA)>
+<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
+<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
+<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
+<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
+<!ELEMENT twCycles (twSigConn+)>
+<!ATTLIST twCycles twNum CDATA #REQUIRED>
+<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
+<!ELEMENT twSig (#PCDATA)>
+<!ELEMENT twDriver (#PCDATA)>
+<!ELEMENT twLoad (#PCDATA)> 
+<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
+<!ATTLIST twConst twConstType (NET | 
+							   NETDELAY | 
+							   NETSKEW | 
+							   PATH |
+							   DEFPERIOD |
+							   UNCONSTPATH |
+							   DEFPATH | 
+							   PATH2SETUP |
+							   UNCONSTPATH2SETUP | 
+							   PATHCLASS | 
+							   PATHDELAY | 
+							   PERIOD |
+							   FREQUENCY |
+							   PATHBLOCK |
+							   OFFSET |
+							   OFFSETIN |
+							   OFFSETINCLOCK | 
+							   UNCONSTOFFSETINCLOCK |
+							   OFFSETINDELAY |
+							   OFFSETINMOD |
+							   OFFSETOUT |
+							   OFFSETOUTCLOCK |
+							   UNCONSTOFFSETOUTCLOCK | 
+							   OFFSETOUTDELAY |
+							   OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
+<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
+					   twEndPtCnt?,
+					   twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
+<!ELEMENT twConstName (#PCDATA)>
+<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
+<!ATTLIST twConstHead uID CDATA #IMPLIED>
+<!ELEMENT twItemCnt (#PCDATA)>
+<!ELEMENT twErrCnt (#PCDATA)>
+<!ELEMENT twErrCntEndPt (#PCDATA)>
+<!ELEMENT twErrCntSetup (#PCDATA)>
+<!ELEMENT twErrCntHold (#PCDATA)>
+<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
+<!ELEMENT twEndPtCnt (#PCDATA)>
+<!ELEMENT twPathErrCnt (#PCDATA)>
+<!ELEMENT twMinPer (#PCDATA) >
+<!ELEMENT twFootnote EMPTY>
+<!ATTLIST twFootnote number CDATA #REQUIRED>
+<!ELEMENT twMaxDel (#PCDATA)>
+<!ELEMENT twMaxFreq (#PCDATA)>
+<!ELEMENT twMinOff (#PCDATA)>
+<!ELEMENT twMaxOff (#PCDATA)>
+<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
+<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
+<!ELEMENT twTIGName (#PCDATA)>
+<!ELEMENT twInstantiated (#PCDATA)>
+<!ELEMENT twBlocked (#PCDATA)>
+<!ELEMENT twRacePathRpt (twRacePath+)>
+<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
+<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
+<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
+						twSimpleMinPath CDATA #IMPLIED>
+<!ELEMENT twTotDel (#PCDATA)>
+<!ELEMENT twSrc (#PCDATA)>
+<!ATTLIST twSrc BELType CDATA #IMPLIED>
+<!ELEMENT twDest (#PCDATA)>
+<!ATTLIST twDest BELType CDATA #IMPLIED>
+<!ELEMENT twDel (#PCDATA)>
+<!ELEMENT twSUTime (#PCDATA)>
+<!ELEMENT twTotPathDel (#PCDATA)>
+<!ELEMENT twClkSkew (#PCDATA)>
+<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
+<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
+<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
+<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
+<!ELEMENT twSlack (#PCDATA)>
+<!ELEMENT twDelConst (#PCDATA)>
+<!ELEMENT tw2Phase EMPTY>
+<!ELEMENT twClkUncert (#PCDATA)>
+<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
+					  fDCMJit CDATA #IMPLIED
+					  fPhaseErr CDATA #IMPLIED
+					  sEqu CDATA #IMPLIED>
+<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
+<!ELEMENT twPathRptBanner (#PCDATA)>
+<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
+<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
+<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
+<!ELEMENT twOff (#PCDATA)>
+<!ELEMENT twGuaranteed EMPTY>
+<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
+<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
+<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
+<!ELEMENT twClkDel (#PCDATA)>
+<!ELEMENT twClkSrc (#PCDATA)>
+<!ELEMENT twClkDest (#PCDATA)>
+<!ELEMENT twGuarInSetup (#PCDATA)>
+<!ELEMENT twOffSrc (#PCDATA)>
+<!ELEMENT twOffDest (#PCDATA)>
+<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
+<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
+<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
+<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
+<!ELEMENT twDataDel (#PCDATA)>
+<!ELEMENT twDataSrc (#PCDATA)>
+<!ELEMENT twDataDest (#PCDATA)>
+<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
+<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
+<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
+<!ELEMENT twLogLvls (#PCDATA)>
+<!ELEMENT twSrcSite (#PCDATA)>
+<!ELEMENT twSrcClk (#PCDATA)>
+<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
+<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
+<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
+<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
+<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
+<!ELEMENT twDelInfo (#PCDATA)>
+<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
+<!ELEMENT twSite (#PCDATA)>
+<!ELEMENT twDelType (#PCDATA)>
+<!ELEMENT twFanCnt (#PCDATA)>
+<!ELEMENT twComp (#PCDATA)>
+<!ELEMENT twNet (#PCDATA)>
+<!ELEMENT twBEL (#PCDATA)>
+<!ELEMENT twLogDel (#PCDATA)>
+<!ELEMENT twRouteDel (#PCDATA)>
+<!ELEMENT twDestClk (#PCDATA)>
+<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
+<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
+<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
+<!ELEMENT twPctLog (#PCDATA)>
+<!ELEMENT twPctRoute (#PCDATA)>
+<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
+<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
+<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
+<!ELEMENT twTimeConst (#PCDATA)>
+<!ELEMENT twAbsSlack (#PCDATA)>
+<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
+<!ELEMENT twSkew (#PCDATA)>
+<!ELEMENT twDetNet (twNetDel*)>
+<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
+<!ELEMENT twNetDelInfo (#PCDATA)>
+<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
+<!ELEMENT twDetSkewNet (twNetSkew*)>
+<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
+<!ELEMENT twClkSkewLimit  EMPTY>
+<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
+		         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
+<!ELEMENT twConstRollupTable (twConstRollup*)>
+<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
+<!ELEMENT twConstRollup  EMPTY>
+<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
+<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
+<!ELEMENT twConstList (twConstListItem)*>
+<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
+<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
+<!ELEMENT twNotMet EMPTY>
+<!ELEMENT twReqVal (#PCDATA)>
+<!ELEMENT twActVal (#PCDATA)>
+<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
+<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
+<!ELEMENT twConstStats (twConstName)>
+<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
+<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
+<!ATTLIST twConstStats twActual CDATA #IMPLIED>
+<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
+<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
+<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
+<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
+<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
+<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
+<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
+<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
+<!ELEMENT twConstData EMPTY>
+<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
+					  best CDATA #IMPLIED requested CDATA #IMPLIED
+					  errors CDATA #IMPLIED
+					  score CDATA #IMPLIED>
+<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
+<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
+<!ELEMENT twTimeGrpName (#PCDATA)>
+<!ELEMENT twCompList (twCompName+)>
+<!ELEMENT twCompName (#PCDATA)>
+<!ELEMENT twSigList (twSigName+)>
+<!ELEMENT twSigName (#PCDATA)>
+<!ELEMENT twBELList (twBELName+)>
+<!ELEMENT twBELName (#PCDATA)>
+<!ELEMENT twBlockList (twBlockName+)>
+<!ELEMENT twBlockName (#PCDATA)>
+<!ELEMENT twMacList (twMacName+)>
+<!ELEMENT twMacName (#PCDATA)>
+<!ELEMENT twPinList (twPinName+)>
+<!ELEMENT twPinName (#PCDATA)>
+<!ELEMENT twUnmetConstCnt (#PCDATA)>
+<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
+<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
+<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
+<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
+<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
+<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
+<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
+<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
+<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
+<!ELEMENT twSU2ClkTime (#PCDATA)>
+<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twH2ClkTime (#PCDATA)>
+<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
+<!ELEMENT twClk2Pad (twDest, twTime)>
+<!ELEMENT twTime (#PCDATA)>
+<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
+<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
+<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
+<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
+<!ELEMENT twClk2Out EMPTY>
+<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
+<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
+<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
+<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
+<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
+<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
+<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
+<!ELEMENT twRiseRise (#PCDATA)>
+<!ELEMENT twFallRise (#PCDATA)>
+<!ELEMENT twRiseFall (#PCDATA)>
+<!ELEMENT twFallFall (#PCDATA)>
+<!ELEMENT twPad2PadList (twPad2Pad+)>
+<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
+<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
+<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
+<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
+<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
+<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
+<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
+<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
+<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
+<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
+<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
+<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
+<!ELEMENT twOffOutTblRow EMPTY>
+<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
+<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
+<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
+<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
+<!ELEMENT twNonDedClk (#PCDATA)>
+<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
+<!ELEMENT twScore (#PCDATA)>
+<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
+<!ELEMENT twPathCnt (#PCDATA)>
+<!ELEMENT twNetCnt (#PCDATA)>
+<!ELEMENT twConnCnt (#PCDATA)>
+<!ELEMENT twPct (#PCDATA)>
+<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
+<!ELEMENT twMaxCombDel (#PCDATA)>
+<!ELEMENT twMaxFromToDel (#PCDATA)>
+<!ELEMENT twMaxNetDel (#PCDATA)>
+<!ELEMENT twMaxNetSkew (#PCDATA)>
+<!ELEMENT twMaxInAfterClk (#PCDATA)>
+<!ELEMENT twMinInBeforeClk (#PCDATA)>
+<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
+<!ELEMENT twMinOutAfterClk (#PCDATA)>
+<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
+<!ELEMENT twTimestamp (#PCDATA)>
+<!ELEMENT twFootnoteExplanation EMPTY>
+<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
+<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
+<!ELEMENT twClientInfo (twClientName, twAttrList?)>
+<!ELEMENT twClientName (#PCDATA)>
+<!ELEMENT twAttrList (twAttrListItem)*>
+<!ELEMENT twAttrListItem (twName, twValue*)>
+<!ELEMENT twName (#PCDATA)>
+<!ELEMENT twValue (#PCDATA)>
+]>
+<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace  (lin64)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 2 -n
+3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf -ucf
+BPC3011-Papilio_Pro-general.ucf
+
+</twCmdLine><twDesign>led.ncd</twDesign><twDesignPath>led.ncd</twDesignPath><twPCF>led.pcf</twPCF><twPcfPath>led.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="tqg144"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true"  dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="PERIOD=31.25ns;" ScopeName="">NET &quot;CLK_BUFGP/IBUFG&quot; PERIOD = 31.25 ns HIGH 50%;</twConstName><twItemCnt>901</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>125</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>3.695</twMinPer></twConstHead><twPathRptBanner iPaths="6" iCriticalPaths="0" sType="EndPoint">Paths for end point count_1 (SLICE_X13Y38.B1), 6 paths
+</twPathRptBanner><twPathRpt anchorID="6"><twConstPath anchorID="7" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>27.555</twSlack><twSrc BELType="FF">count_9</twSrc><twDest BELType="FF">count_1</twDest><twTotPathDel>3.645</twTotPathDel><twClkSkew dest = "0.285" src = "0.300">0.015</twClkSkew><twDelConst>31.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>count_9</twSrc><twDest BELType='FF'>count_1</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X13Y40.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X13Y40.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>count&lt;11&gt;</twComp><twBEL>count_9</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.B3</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.341</twDelInfo><twComp>count&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y41.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>count[26]_GND_1_o_equal_2_o&lt;26&gt;4</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y38.B1</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising">1.266</twDelInfo><twComp>count[26]_GND_1_o_equal_2_o&lt;26&gt;3</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y38.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>count&lt;3&gt;</twComp><twBEL>count_1_rstpot</twBEL><twBEL>count_1</twBEL></twPathDel><twLogDel>1.038</twLogDel><twRouteDel>2.607</twRouteDel><twTotDel>3.645</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>28.5</twPctLog><twPctRoute>71.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="8"><twConstPath anchorID="9" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>27.760</twSlack><twSrc BELType="FF">count_10</twSrc><twDest BELType="FF">count_1</twDest><twTotPathDel>3.440</twTotPathDel><twClkSkew dest = "0.285" src = "0.300">0.015</twClkSkew><twDelConst>31.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>count_10</twSrc><twDest BELType='FF'>count_1</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X13Y40.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X13Y40.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>count&lt;11&gt;</twComp><twBEL>count_10</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.B1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.136</twDelInfo><twComp>count&lt;10&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y41.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>count[26]_GND_1_o_equal_2_o&lt;26&gt;4</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y38.B1</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising">1.266</twDelInfo><twComp>count[26]_GND_1_o_equal_2_o&lt;26&gt;3</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y38.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>count&lt;3&gt;</twComp><twBEL>count_1_rstpot</twBEL><twBEL>count_1</twBEL></twPathDel><twLogDel>1.038</twLogDel><twRouteDel>2.402</twRouteDel><twTotDel>3.440</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>30.2</twPctLog><twPctRoute>69.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="10"><twConstPath anchorID="11" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>27.948</twSlack><twSrc BELType="FF">count_11</twSrc><twDest BELType="FF">count_1</twDest><twTotPathDel>3.252</twTotPathDel><twClkSkew dest = "0.285" src = "0.300">0.015</twClkSkew><twDelConst>31.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>count_11</twSrc><twDest BELType='FF'>count_1</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X13Y40.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X13Y40.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>count&lt;11&gt;</twComp><twBEL>count_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.B2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.948</twDelInfo><twComp>count&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y41.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>count[26]_GND_1_o_equal_2_o&lt;26&gt;4</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y38.B1</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising">1.266</twDelInfo><twComp>count[26]_GND_1_o_equal_2_o&lt;26&gt;3</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y38.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>count&lt;3&gt;</twComp><twBEL>count_1_rstpot</twBEL><twBEL>count_1</twBEL></twPathDel><twLogDel>1.038</twLogDel><twRouteDel>2.214</twRouteDel><twTotDel>3.252</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>31.9</twPctLog><twPctRoute>68.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="6" iCriticalPaths="0" sType="EndPoint">Paths for end point count_7 (SLICE_X13Y39.D2), 6 paths
+</twPathRptBanner><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>27.560</twSlack><twSrc BELType="FF">count_9</twSrc><twDest BELType="FF">count_7</twDest><twTotPathDel>3.638</twTotPathDel><twClkSkew dest = "0.283" src = "0.300">0.017</twClkSkew><twDelConst>31.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>count_9</twSrc><twDest BELType='FF'>count_7</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X13Y40.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X13Y40.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>count&lt;11&gt;</twComp><twBEL>count_9</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.B3</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.341</twDelInfo><twComp>count&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y41.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>count[26]_GND_1_o_equal_2_o&lt;26&gt;4</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y39.D2</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising">1.259</twDelInfo><twComp>count[26]_GND_1_o_equal_2_o&lt;26&gt;3</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y39.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>count&lt;7&gt;</twComp><twBEL>count_7_rstpot</twBEL><twBEL>count_7</twBEL></twPathDel><twLogDel>1.038</twLogDel><twRouteDel>2.600</twRouteDel><twTotDel>3.638</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>28.5</twPctLog><twPctRoute>71.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="14"><twConstPath anchorID="15" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>27.765</twSlack><twSrc BELType="FF">count_10</twSrc><twDest BELType="FF">count_7</twDest><twTotPathDel>3.433</twTotPathDel><twClkSkew dest = "0.283" src = "0.300">0.017</twClkSkew><twDelConst>31.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>count_10</twSrc><twDest BELType='FF'>count_7</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X13Y40.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X13Y40.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>count&lt;11&gt;</twComp><twBEL>count_10</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.B1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">1.136</twDelInfo><twComp>count&lt;10&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y41.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>count[26]_GND_1_o_equal_2_o&lt;26&gt;4</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y39.D2</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising">1.259</twDelInfo><twComp>count[26]_GND_1_o_equal_2_o&lt;26&gt;3</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y39.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>count&lt;7&gt;</twComp><twBEL>count_7_rstpot</twBEL><twBEL>count_7</twBEL></twPathDel><twLogDel>1.038</twLogDel><twRouteDel>2.395</twRouteDel><twTotDel>3.433</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>30.2</twPctLog><twPctRoute>69.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="16"><twConstPath anchorID="17" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>27.953</twSlack><twSrc BELType="FF">count_11</twSrc><twDest BELType="FF">count_7</twDest><twTotPathDel>3.245</twTotPathDel><twClkSkew dest = "0.283" src = "0.300">0.017</twClkSkew><twDelConst>31.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>count_11</twSrc><twDest BELType='FF'>count_7</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X13Y40.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X13Y40.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>count&lt;11&gt;</twComp><twBEL>count_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.B2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.948</twDelInfo><twComp>count&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y41.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.235</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>count[26]_GND_1_o_equal_2_o&lt;26&gt;4</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y39.D2</twSite><twDelType>net</twDelType><twFanCnt>19</twFanCnt><twDelInfo twEdge="twRising">1.259</twDelInfo><twComp>count[26]_GND_1_o_equal_2_o&lt;26&gt;3</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y39.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>count&lt;7&gt;</twComp><twBEL>count_7_rstpot</twBEL><twBEL>count_7</twBEL></twPathDel><twLogDel>1.038</twLogDel><twRouteDel>2.207</twRouteDel><twTotDel>3.245</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>32.0</twPctLog><twPctRoute>68.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="24" iCriticalPaths="0" sType="EndPoint">Paths for end point count_23 (SLICE_X13Y41.A1), 24 paths
+</twPathRptBanner><twPathRpt anchorID="18"><twConstPath anchorID="19" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>27.618</twSlack><twSrc BELType="FF">count_1</twSrc><twDest BELType="FF">count_23</twDest><twTotPathDel>3.580</twTotPathDel><twClkSkew dest = "0.285" src = "0.302">0.017</twClkSkew><twDelConst>31.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>count_1</twSrc><twDest BELType='FF'>count_23</twDest><twLogLvls>7</twLogLvls><twSrcSite>SLICE_X13Y38.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X13Y38.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>count&lt;3&gt;</twComp><twBEL>count_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y38.B1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.730</twDelInfo><twComp>count&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y38.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>Mcount_count_cy&lt;3&gt;</twComp><twBEL>Mcount_count_lut&lt;1&gt;_INV_0</twBEL><twBEL>Mcount_count_cy&lt;3&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y39.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcount_count_cy&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y39.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcount_count_cy&lt;7&gt;</twComp><twBEL>Mcount_count_cy&lt;7&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y40.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.082</twDelInfo><twComp>Mcount_count_cy&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y40.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcount_count_cy&lt;11&gt;</twComp><twBEL>Mcount_count_cy&lt;11&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y41.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcount_count_cy&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y41.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcount_count_cy&lt;15&gt;</twComp><twBEL>Mcount_count_cy&lt;15&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y42.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcount_count_cy&lt;15&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y42.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcount_count_cy&lt;19&gt;</twComp><twBEL>Mcount_count_cy&lt;19&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y43.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcount_count_cy&lt;19&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y43.DMUX</twSite><twDelType>Tcind</twDelType><twDelInfo twEdge="twRising">0.320</twDelInfo><twComp>Result&lt;23&gt;</twComp><twBEL>Mcount_count_xor&lt;23&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y41.A1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.778</twDelInfo><twComp>Result&lt;23&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y41.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>count&lt;23&gt;</twComp><twBEL>count_23_rstpot</twBEL><twBEL>count_23</twBEL></twPathDel><twLogDel>1.978</twLogDel><twRouteDel>1.602</twRouteDel><twTotDel>3.580</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>55.3</twPctLog><twPctRoute>44.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="20"><twConstPath anchorID="21" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>27.628</twSlack><twSrc BELType="FF">count_0</twSrc><twDest BELType="FF">count_23</twDest><twTotPathDel>3.570</twTotPathDel><twClkSkew dest = "0.285" src = "0.302">0.017</twClkSkew><twDelConst>31.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>count_0</twSrc><twDest BELType='FF'>count_23</twDest><twLogLvls>7</twLogLvls><twSrcSite>SLICE_X13Y38.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X13Y38.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>count&lt;3&gt;</twComp><twBEL>count_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y38.A2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.729</twDelInfo><twComp>count&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y38.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.474</twDelInfo><twComp>Mcount_count_cy&lt;3&gt;</twComp><twBEL>count&lt;0&gt;_rt</twBEL><twBEL>Mcount_count_cy&lt;3&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y39.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcount_count_cy&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y39.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcount_count_cy&lt;7&gt;</twComp><twBEL>Mcount_count_cy&lt;7&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y40.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.082</twDelInfo><twComp>Mcount_count_cy&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y40.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcount_count_cy&lt;11&gt;</twComp><twBEL>Mcount_count_cy&lt;11&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y41.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcount_count_cy&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y41.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcount_count_cy&lt;15&gt;</twComp><twBEL>Mcount_count_cy&lt;15&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y42.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcount_count_cy&lt;15&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y42.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcount_count_cy&lt;19&gt;</twComp><twBEL>Mcount_count_cy&lt;19&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y43.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcount_count_cy&lt;19&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y43.DMUX</twSite><twDelType>Tcind</twDelType><twDelInfo twEdge="twRising">0.320</twDelInfo><twComp>Result&lt;23&gt;</twComp><twBEL>Mcount_count_xor&lt;23&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y41.A1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.778</twDelInfo><twComp>Result&lt;23&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y41.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>count&lt;23&gt;</twComp><twBEL>count_23_rstpot</twBEL><twBEL>count_23</twBEL></twPathDel><twLogDel>1.969</twLogDel><twRouteDel>1.601</twRouteDel><twTotDel>3.570</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>55.2</twPctLog><twPctRoute>44.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="22"><twConstPath anchorID="23" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>27.639</twSlack><twSrc BELType="FF">count_5</twSrc><twDest BELType="FF">count_23</twDest><twTotPathDel>3.561</twTotPathDel><twClkSkew dest = "0.285" src = "0.300">0.015</twClkSkew><twDelConst>31.250</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>count_5</twSrc><twDest BELType='FF'>count_23</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X13Y39.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X13Y39.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.430</twDelInfo><twComp>count&lt;7&gt;</twComp><twBEL>count_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y39.B1</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.807</twDelInfo><twComp>count&lt;5&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y39.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>Mcount_count_cy&lt;7&gt;</twComp><twBEL>Mcount_count_lut&lt;5&gt;_INV_0</twBEL><twBEL>Mcount_count_cy&lt;7&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y40.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.082</twDelInfo><twComp>Mcount_count_cy&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y40.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcount_count_cy&lt;11&gt;</twComp><twBEL>Mcount_count_cy&lt;11&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y41.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcount_count_cy&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y41.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcount_count_cy&lt;15&gt;</twComp><twBEL>Mcount_count_cy&lt;15&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y42.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcount_count_cy&lt;15&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y42.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.093</twDelInfo><twComp>Mcount_count_cy&lt;19&gt;</twComp><twBEL>Mcount_count_cy&lt;19&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y43.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Mcount_count_cy&lt;19&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y43.DMUX</twSite><twDelType>Tcind</twDelType><twDelInfo twEdge="twRising">0.320</twDelInfo><twComp>Result&lt;23&gt;</twComp><twBEL>Mcount_count_xor&lt;23&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y41.A1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.778</twDelInfo><twComp>Result&lt;23&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y41.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>count&lt;23&gt;</twComp><twBEL>count_23_rstpot</twBEL><twBEL>count_23</twBEL></twPathDel><twLogDel>1.885</twLogDel><twRouteDel>1.676</twRouteDel><twTotDel>3.561</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>52.9</twPctLog><twPctRoute>47.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: NET &quot;CLK_BUFGP/IBUFG&quot; PERIOD = 31.25 ns HIGH 50%;
+</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point LED1 (SLICE_X14Y41.A6), 1 path
+</twPathRptBanner><twPathRpt anchorID="24"><twConstPath anchorID="25" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.418</twSlack><twSrc BELType="FF">LED1</twSrc><twDest BELType="FF">LED1</twDest><twTotPathDel>0.418</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>LED1</twSrc><twDest BELType='FF'>LED1</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X14Y41.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X14Y41.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>LED1</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.A6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.028</twDelInfo><twComp>LED1_OBUF</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X14Y41.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>LED1_rstpot</twBEL><twBEL>LED1</twBEL></twPathDel><twLogDel>0.390</twLogDel><twRouteDel>0.028</twRouteDel><twTotDel>0.418</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>93.3</twPctLog><twPctRoute>6.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="6" iCriticalPaths="0" sType="EndPoint">Paths for end point count_12 (SLICE_X15Y41.A6), 6 paths
+</twPathRptBanner><twPathRpt anchorID="26"><twConstPath anchorID="27" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.689</twSlack><twSrc BELType="FF">count_14</twSrc><twDest BELType="FF">count_12</twDest><twTotPathDel>0.689</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>count_14</twSrc><twDest BELType='FF'>count_12</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X15Y41.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X15Y41.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.198</twDelInfo><twComp>count&lt;14&gt;</twComp><twBEL>count_14</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.032</twDelInfo><twComp>count&lt;14&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y41.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.142</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>count[26]_GND_1_o_equal_2_o&lt;26&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y41.A6</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twFalling">0.102</twDelInfo><twComp>count[26]_GND_1_o_equal_2_o&lt;26&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X15Y41.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>count&lt;14&gt;</twComp><twBEL>count_12_rstpot</twBEL><twBEL>count_12</twBEL></twPathDel><twLogDel>0.555</twLogDel><twRouteDel>0.134</twRouteDel><twTotDel>0.689</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>80.6</twPctLog><twPctRoute>19.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="28"><twConstPath anchorID="29" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.829</twSlack><twSrc BELType="FF">count_17</twSrc><twDest BELType="FF">count_12</twDest><twTotPathDel>0.829</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>count_17</twSrc><twDest BELType='FF'>count_12</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X15Y42.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X15Y42.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.198</twDelInfo><twComp>count&lt;18&gt;</twComp><twBEL>count_17</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.C5</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.172</twDelInfo><twComp>count&lt;17&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y41.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.142</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>count[26]_GND_1_o_equal_2_o&lt;26&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y41.A6</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twFalling">0.102</twDelInfo><twComp>count[26]_GND_1_o_equal_2_o&lt;26&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X15Y41.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>count&lt;14&gt;</twComp><twBEL>count_12_rstpot</twBEL><twBEL>count_12</twBEL></twPathDel><twLogDel>0.555</twLogDel><twRouteDel>0.274</twRouteDel><twTotDel>0.829</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>66.9</twPctLog><twPctRoute>33.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="30"><twConstPath anchorID="31" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.881</twSlack><twSrc BELType="FF">count_15</twSrc><twDest BELType="FF">count_12</twDest><twTotPathDel>0.881</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>count_15</twSrc><twDest BELType='FF'>count_12</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X15Y42.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X15Y42.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.198</twDelInfo><twComp>count&lt;18&gt;</twComp><twBEL>count_15</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.C4</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.224</twDelInfo><twComp>count&lt;15&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y41.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.142</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>count[26]_GND_1_o_equal_2_o&lt;26&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y41.A6</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twFalling">0.102</twDelInfo><twComp>count[26]_GND_1_o_equal_2_o&lt;26&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X15Y41.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>count&lt;14&gt;</twComp><twBEL>count_12_rstpot</twBEL><twBEL>count_12</twBEL></twPathDel><twLogDel>0.555</twLogDel><twRouteDel>0.326</twRouteDel><twTotDel>0.881</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>63.0</twPctLog><twPctRoute>37.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="6" iCriticalPaths="0" sType="EndPoint">Paths for end point LED1 (SLICE_X14Y41.A1), 6 paths
+</twPathRptBanner><twPathRpt anchorID="32"><twConstPath anchorID="33" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.812</twSlack><twSrc BELType="FF">count_14</twSrc><twDest BELType="FF">LED1</twDest><twTotPathDel>0.814</twTotPathDel><twClkSkew dest = "0.033" src = "0.031">-0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>count_14</twSrc><twDest BELType='FF'>LED1</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X15Y41.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X15Y41.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.198</twDelInfo><twComp>count&lt;14&gt;</twComp><twBEL>count_14</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.C6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.032</twDelInfo><twComp>count&lt;14&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y41.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.142</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>count[26]_GND_1_o_equal_2_o&lt;26&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.A1</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twFalling">0.252</twDelInfo><twComp>count[26]_GND_1_o_equal_2_o&lt;26&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X14Y41.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>LED1_rstpot</twBEL><twBEL>LED1</twBEL></twPathDel><twLogDel>0.530</twLogDel><twRouteDel>0.284</twRouteDel><twTotDel>0.814</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>65.1</twPctLog><twPctRoute>34.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="34"><twConstPath anchorID="35" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.954</twSlack><twSrc BELType="FF">count_17</twSrc><twDest BELType="FF">LED1</twDest><twTotPathDel>0.954</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>count_17</twSrc><twDest BELType='FF'>LED1</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X15Y42.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X15Y42.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.198</twDelInfo><twComp>count&lt;18&gt;</twComp><twBEL>count_17</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.C5</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.172</twDelInfo><twComp>count&lt;17&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y41.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.142</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>count[26]_GND_1_o_equal_2_o&lt;26&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.A1</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twFalling">0.252</twDelInfo><twComp>count[26]_GND_1_o_equal_2_o&lt;26&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X14Y41.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>LED1_rstpot</twBEL><twBEL>LED1</twBEL></twPathDel><twLogDel>0.530</twLogDel><twRouteDel>0.424</twRouteDel><twTotDel>0.954</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>55.6</twPctLog><twPctRoute>44.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="36"><twConstPath anchorID="37" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>1.006</twSlack><twSrc BELType="FF">count_15</twSrc><twDest BELType="FF">LED1</twDest><twTotPathDel>1.006</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>count_15</twSrc><twDest BELType='FF'>LED1</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X15Y42.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X15Y42.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.198</twDelInfo><twComp>count&lt;18&gt;</twComp><twBEL>count_15</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.C4</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.224</twDelInfo><twComp>count&lt;15&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y41.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twFalling">0.142</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>count[26]_GND_1_o_equal_2_o&lt;26&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y41.A1</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twFalling">0.252</twDelInfo><twComp>count[26]_GND_1_o_equal_2_o&lt;26&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X14Y41.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>LED1_OBUF</twComp><twBEL>LED1_rstpot</twBEL><twBEL>LED1</twBEL></twPathDel><twLogDel>0.530</twLogDel><twRouteDel>0.476</twRouteDel><twTotDel>1.006</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="31.250">CLK_BUFGP</twDestClk><twPctLog>52.7</twPctLog><twPctRoute>47.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="38"><twPinLimitBanner>Component Switching Limit Checks: NET &quot;CLK_BUFGP/IBUFG&quot; PERIOD = 31.25 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="39" type="MINPERIOD" name="Tbcper_I" slack="28.584" period="31.250" constraintValue="31.250" deviceLimit="2.666" freqLimit="375.094" physResource="CLK_BUFGP/BUFG/I0" logResource="CLK_BUFGP/BUFG/I0" locationPin="BUFGMUX_X2Y2.I0" clockNet="CLK_BUFGP/IBUFG"/><twPinLimit anchorID="40" type="MINPERIOD" name="Tcp" slack="30.775" period="31.250" constraintValue="31.250" deviceLimit="0.475" freqLimit="2105.263" physResource="LED1_OBUF/CLK" logResource="LED1/CK" locationPin="SLICE_X14Y41.CLK" clockNet="CLK_BUFGP"/><twPinLimit anchorID="41" type="MINPERIOD" name="Tcp" slack="30.780" period="31.250" constraintValue="31.250" deviceLimit="0.470" freqLimit="2127.660" physResource="count&lt;3&gt;/CLK" logResource="count_0/CK" locationPin="SLICE_X13Y38.CLK" clockNet="CLK_BUFGP"/></twPinLimitRpt></twConst><twUnmetConstCnt anchorID="42">0</twUnmetConstCnt><twDataSheet anchorID="43" twNameLen="15"><twClk2SUList anchorID="44" twDestWidth="3"><twDest>CLK</twDest><twClk2SU><twSrc>CLK</twSrc><twRiseRise>3.695</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="45"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>901</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>211</twConnCnt></twConstCov><twStats anchorID="46"><twMinPer>3.695</twMinPer><twFootnote number="1" /><twMaxFreq>270.636</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Tue Feb 21 22:17:03 2017 </twTimestamp></twFoot><twClientInfo anchorID="47"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
+
+Peak Memory Usage: 390 MB
+</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
diff --git a/led.unroutes b/led.unroutes
new file mode 100644
index 0000000..f9381ee
--- /dev/null
+++ b/led.unroutes
@@ -0,0 +1,9 @@
+Release 14.7 - par P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Tue Feb 21 22:16:59 2017
+
+All signals are completely routed.
+
+
+
diff --git a/led.ut b/led.ut
new file mode 100644
index 0000000..d1824d0
--- /dev/null
+++ b/led.ut
@@ -0,0 +1,30 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
diff --git a/led.v b/led.v
index 28d6363..c7657f2 100644
--- a/led.v
+++ b/led.v
@@ -18,8 +18,27 @@
 // Additional Comments: 
 //
 //////////////////////////////////////////////////////////////////////////////////
-module led(
-    );
-
+module led(CLK, LED1);
 
+   input CLK;
+   output reg LED1;
+   
+   reg [26:0] count;
+   
+   initial begin
+      count = 26'd16000000;
+      LED1 = 1'b0;
+   end
+   
+   always @ (posedge CLK) 
+     begin
+	if(count == 1'b0) 
+	  begin
+	     LED1 <= ~LED1;
+	     count <= 26'd16000000;
+	  end
+	else 
+	  count <= count - 1'b1;
+     end
+   
 endmodule
diff --git a/led.xdl b/led.xdl
new file mode 100644
index 0000000..761d70a
--- /dev/null
+++ b/led.xdl
diff --git a/led.xpi b/led.xpi
new file mode 100644
index 0000000..a50c444
--- /dev/null
+++ b/led.xpi
@@ -0,0 +1,3 @@
+PROGRAM=PAR
+STATE=ROUTED
+TIMESPECS_MET=YES
diff --git a/led.xst b/led.xst
index 0a62f03..0cd81d2 100644
--- a/led.xst
+++ b/led.xst
@@ -2,13 +2,13 @@ set -tmpdir "xst/projnav.tmp"
 set -xsthdpdir "xst"
 run
 -ifn led.prj
--ifmt mixed
 -ofn led
 -ofmt NGC
--p xc3s250e-4-vq100
+-p xc6slx9-2-tqg144
 -top led
 -opt_mode Speed
 -opt_level 1
+-power NO
 -iuc NO
 -keep_hierarchy No
 -netlist_hierarchy As_Optimized
@@ -22,35 +22,31 @@ run
 -case Maintain
 -slice_utilization_ratio 100
 -bram_utilization_ratio 100
--verilog2001 YES
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
 -fsm_extract YES -fsm_encoding Auto
 -safe_implementation No
 -fsm_style LUT
 -ram_extract Yes
 -ram_style Auto
 -rom_extract Yes
--mux_style Auto
--decoder_extract YES
--priority_extract Yes
 -shreg_extract YES
--shift_extract YES
--xor_collapse YES
 -rom_style Auto
 -auto_bram_packing NO
--mux_extract Yes
 -resource_sharing YES
 -async_to_sync NO
--mult_style Auto
+-shreg_min_size 2
+-use_dsp48 Auto
 -iobuf YES
--max_fanout 500
--bufg 24
+-max_fanout 100000
+-bufg 16
 -register_duplication YES
 -register_balancing No
--slice_packing YES
 -optimize_primitives NO
--use_clock_enable Yes
--use_sync_set Yes
--use_sync_reset Yes
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
 -iob Auto
 -equivalent_register_removal YES
 -slice_utilization_ratio_maxmargin 5
diff --git a/led_bitgen.xwbt b/led_bitgen.xwbt
new file mode 100644
index 0000000..e907caf
--- /dev/null
+++ b/led_bitgen.xwbt
@@ -0,0 +1,8 @@
+INTSTYLE=ise
+INFILE=/home/yannherklotz/Github/FPGA-led-lights/led.ncd
+OUTFILE=/home/yannherklotz/Github/FPGA-led-lights/led.bit
+FAMILY=Spartan6
+PART=xc6slx9-2tqg144
+WORKINGDIR=/home/yannherklotz/Github/FPGA-led-lights
+LICENSE=WebPack
+USER_INFO=211291888_0_0_214
diff --git a/led_envsettings.html b/led_envsettings.html
index 215f634..11d7231 100644
--- a/led_envsettings.html
+++ b/led_envsettings.html
@@ -16,44 +16,51 @@
 <tr>
 <td>LD_LIBRARY_PATH</td>
 <td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
 </tr>
 <tr>
 <td>PATH</td>
 <td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/local/sbin:<br>/usr/local/bin:<br>/usr/bin:<br>/usr/lib/jvm/default/bin:<br>/usr/bin/site_perl:<br>/usr/bin/vendor_perl:<br>/usr/bin/core_perl</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/local/sbin:<br>/usr/local/bin:<br>/usr/bin:<br>/usr/lib/jvm/default/bin:<br>/usr/bin/site_perl:<br>/usr/bin/vendor_perl:<br>/usr/bin/core_perl</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/local/sbin:<br>/usr/local/bin:<br>/usr/bin:<br>/usr/lib/jvm/default/bin:<br>/usr/bin/site_perl:<br>/usr/bin/vendor_perl:<br>/usr/bin/core_perl</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/local/sbin:<br>/usr/local/bin:<br>/usr/bin:<br>/usr/lib/jvm/default/bin:<br>/usr/bin/site_perl:<br>/usr/bin/vendor_perl:<br>/usr/bin/core_perl</td>
 </tr>
 <tr>
 <td>XILINX</td>
 <td>/opt/Xilinx/14.7/ISE_DS/ISE/</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE/</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE/</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE/</td>
 </tr>
 <tr>
 <td>XILINX_DSP</td>
 <td>/opt/Xilinx/14.7/ISE_DS/ISE</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE</td>
 </tr>
 <tr>
 <td>XILINX_EDK</td>
 <td>/opt/Xilinx/14.7/ISE_DS/EDK</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td>/opt/Xilinx/14.7/ISE_DS/EDK</td>
+<td>/opt/Xilinx/14.7/ISE_DS/EDK</td>
+<td>/opt/Xilinx/14.7/ISE_DS/EDK</td>
 </tr>
 <tr>
 <td>XILINX_PLANAHEAD</td>
 <td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td>
+<td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td>
+<td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td>
+</tr>
+<tr>
+<td>XIL_MAP_LOCWARN</td>
+<td>1</td>
+<td>1</td>
+<td>1</td>
+<td>1</td>
 </tr>
 </TABLE>
 <A NAME="Synthesis Property Settings"></A>
@@ -74,12 +81,6 @@
 <td>&nbsp;</td>
 </tr>
 <tr>
-<td>-ifmt</td>
-<td>&nbsp;</td>
-<td>mixed</td>
-<td>MIXED</td>
-</tr>
-<tr>
 <td>-ofn</td>
 <td>&nbsp;</td>
 <td>led</td>
@@ -94,7 +95,7 @@
 <tr>
 <td>-p</td>
 <td>&nbsp;</td>
-<td>xc3s250e-4-vq100</td>
+<td>xc6slx9-2-tqg144</td>
 <td>&nbsp;</td>
 </tr>
 <tr>
@@ -107,7 +108,7 @@
 <td>-opt_mode</td>
 <td>Optimization Goal</td>
 <td>Speed</td>
-<td>SPEED</td>
+<td>Speed</td>
 </tr>
 <tr>
 <td>-opt_level</td>
@@ -116,52 +117,58 @@
 <td>1</td>
 </tr>
 <tr>
+<td>-power</td>
+<td>Power Reduction</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
 <td>-iuc</td>
 <td>Use synthesis Constraints File</td>
 <td>NO</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-keep_hierarchy</td>
 <td>Keep Hierarchy</td>
 <td>No</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-netlist_hierarchy</td>
 <td>Netlist Hierarchy</td>
 <td>As_Optimized</td>
-<td>as_optimized</td>
+<td>As_Optimized</td>
 </tr>
 <tr>
 <td>-rtlview</td>
 <td>Generate RTL Schematic</td>
 <td>Yes</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-glob_opt</td>
 <td>Global Optimization Goal</td>
 <td>AllClockNets</td>
-<td>ALLCLOCKNETS</td>
+<td>AllClockNets</td>
 </tr>
 <tr>
 <td>-read_cores</td>
 <td>Read Cores</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-write_timing_constraints</td>
 <td>Write Timing Constraints</td>
 <td>NO</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-cross_clock_analysis</td>
 <td>Cross Clock Analysis</td>
 <td>NO</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-bus_delimiter</td>
@@ -173,37 +180,43 @@
 <td>-slice_utilization_ratio</td>
 <td>Slice Utilization Ratio</td>
 <td>100</td>
-<td>100%</td>
+<td>100</td>
 </tr>
 <tr>
 <td>-bram_utilization_ratio</td>
 <td>BRAM Utilization Ratio</td>
 <td>100</td>
-<td>100%</td>
+<td>100</td>
 </tr>
 <tr>
-<td>-verilog2001</td>
-<td>Verilog 2001</td>
-<td>YES</td>
-<td>YES</td>
+<td>-dsp_utilization_ratio</td>
+<td>DSP Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-reduce_control_sets</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-fsm_extract</td>
 <td>&nbsp;</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-fsm_encoding</td>
 <td>&nbsp;</td>
 <td>Auto</td>
-<td>AUTO</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-safe_implementation</td>
 <td>&nbsp;</td>
 <td>No</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-fsm_style</td>
@@ -215,127 +228,283 @@
 <td>-ram_extract</td>
 <td>&nbsp;</td>
 <td>Yes</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-ram_style</td>
 <td>&nbsp;</td>
 <td>Auto</td>
-<td>AUTO</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-rom_extract</td>
 <td>&nbsp;</td>
 <td>Yes</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-shreg_extract</td>
 <td>&nbsp;</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-rom_style</td>
 <td>&nbsp;</td>
 <td>Auto</td>
-<td>AUTO</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-auto_bram_packing</td>
 <td>&nbsp;</td>
 <td>NO</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-resource_sharing</td>
 <td>&nbsp;</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-async_to_sync</td>
 <td>&nbsp;</td>
 <td>NO</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
-<td>-mult_style</td>
+<td>-use_dsp48</td>
 <td>&nbsp;</td>
 <td>Auto</td>
-<td>AUTO</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-iobuf</td>
 <td>&nbsp;</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-max_fanout</td>
 <td>&nbsp;</td>
-<td>500</td>
-<td>500</td>
+<td>100000</td>
+<td>100000</td>
 </tr>
 <tr>
 <td>-bufg</td>
 <td>&nbsp;</td>
-<td>24</td>
-<td>24</td>
+<td>16</td>
+<td>16</td>
 </tr>
 <tr>
 <td>-register_duplication</td>
 <td>&nbsp;</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-register_balancing</td>
 <td>&nbsp;</td>
 <td>No</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-optimize_primitives</td>
 <td>&nbsp;</td>
 <td>NO</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-use_clock_enable</td>
 <td>&nbsp;</td>
-<td>Yes</td>
-<td>YES</td>
+<td>Auto</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-use_sync_set</td>
 <td>&nbsp;</td>
-<td>Yes</td>
-<td>YES</td>
+<td>Auto</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-use_sync_reset</td>
 <td>&nbsp;</td>
-<td>Yes</td>
-<td>YES</td>
+<td>Auto</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-iob</td>
 <td>&nbsp;</td>
 <td>Auto</td>
-<td>AUTO</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-equivalent_register_removal</td>
 <td>&nbsp;</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-slice_utilization_ratio_maxmargin</td>
 <td>&nbsp;</td>
 <td>5</td>
-<td>0%</td>
+<td>0</td>
+</tr>
+</TABLE>
+<A NAME="Translation Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-aul</td>
+<td>Allow Unmatched LOC Constraints</td>
+<td>true</td>
+<td>false</td>
+</tr>
+<tr>
+<td>-intstyle</td>
+<td>&nbsp;</td>
+<td>ise</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-dd</td>
+<td>&nbsp;</td>
+<td>_ngo</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc6slx9-tqg144-2</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-uc</td>
+<td>&nbsp;</td>
+<td>BPC3011-Papilio_Pro-general.ucf</td>
+<td>None</td>
+</tr>
+</TABLE>
+<A NAME="Map Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-ol</td>
+<td>Place & Route Effort Level (Overall)</td>
+<td>high</td>
+<td>high</td>
+</tr>
+<tr>
+<td>-xt</td>
+<td>Extra Cost Tables</td>
+<td>0</td>
+<td>0</td>
+</tr>
+<tr>
+<td>-ir</td>
+<td>Use RLOC Constraints</td>
+<td>OFF</td>
+<td>OFF</td>
+</tr>
+<tr>
+<td>-t</td>
+<td>Starting Placer Cost Table (1-100) Map</td>
+<td>1</td>
+<td>0</td>
+</tr>
+<tr>
+<td>-r</td>
+<td>Register Ordering</td>
+<td>4</td>
+<td>4</td>
+</tr>
+<tr>
+<td>-intstyle</td>
+<td>&nbsp;</td>
+<td>ise</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-lc</td>
+<td>LUT Combining</td>
+<td>off</td>
+<td>off</td>
+</tr>
+<tr>
+<td>-o</td>
+<td>&nbsp;</td>
+<td>led_map.ncd</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-w</td>
+<td>&nbsp;</td>
+<td>true</td>
+<td>false</td>
+</tr>
+<tr>
+<td>-pr</td>
+<td>Pack I/O Registers/Latches into IOBs</td>
+<td>off</td>
+<td>off</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc6slx9-tqg144-2</td>
+<td>None</td>
+</tr>
+</TABLE>
+<A NAME="Place and Route Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-intstyle</td>
+<td>&nbsp;</td>
+<td>ise</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-mt</td>
+<td>Enable Multi-Threading</td>
+<td>off</td>
+<td>off</td>
+</tr>
+<tr>
+<td>-ol</td>
+<td>Place & Route Effort Level (Overall)</td>
+<td>high</td>
+<td>std</td>
+</tr>
+<tr>
+<td>-w</td>
+<td>&nbsp;</td>
+<td>true</td>
+<td>false</td>
 </tr>
 </TABLE>
 <A NAME="Operating System Information"></A>
@@ -353,30 +522,30 @@
 <tr>
 <td>CPU Architecture/Speed</td>
 <td>Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz/3099.957 MHz</td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td>Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz/3099.957 MHz</td>
+<td>Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz/3100.451 MHz</td>
+<td>Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz/3100.122 MHz</td>
 </tr>
 <tr>
 <td>Host</td>
 <td>yann-arch</td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td>yann-arch</td>
+<td>yann-arch</td>
+<td>yann-arch</td>
 </tr>
 <tr>
 <td>OS Name</td>
 <td>unknown</td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td>unknown</td>
+<td>unknown</td>
+<td>unknown</td>
 </tr>
 <tr>
 <td>OS Release</td>
 <td>unknown</td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
-<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
+<td>unknown</td>
+<td>unknown</td>
+<td>unknown</td>
 </tr>
 </TABLE>
 </BODY> </HTML>
 \ No newline at end of file
diff --git a/led_guide.ncd b/led_guide.ncd
new file mode 100644
index 0000000..bc25375
--- /dev/null
+++ b/led_guide.ncd
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
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+\ No newline at end of file
diff --git a/led_map.map b/led_map.map
new file mode 100644
index 0000000..050a07f
--- /dev/null
+++ b/led_map.map
@@ -0,0 +1,146 @@
+Release 14.7 Map P.20131013 (lin64)
+Xilinx Map Application Log File for Design 'led'
+
+Design Information
+------------------
+Command Line   : map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol
+high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
+-pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+Target Device  : xc6slx9
+Target Package : tqg144
+Target Speed   : -2
+Mapper Version : spartan6 -- $Revision: 1.55 $
+Mapped Date    : Tue Feb 21 22:16:49 2017
+
+Mapping design into LUTs...
+Running directed packing...
+Running delay-based LUT packing...
+Updating timing models...
+INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
+   (.mrp).
+Running timing-driven placement...
+Total REAL time at the beginning of Placer: 3 secs 
+Total CPU  time at the beginning of Placer: 3 secs 
+
+Phase 1.1  Initial Placement Analysis
+Phase 1.1  Initial Placement Analysis (Checksum:184813e3) REAL time: 3 secs 
+
+Phase 2.7  Design Feasibility Check
+Phase 2.7  Design Feasibility Check (Checksum:184813e3) REAL time: 3 secs 
+
+Phase 3.31  Local Placement Optimization
+Phase 3.31  Local Placement Optimization (Checksum:184813e3) REAL time: 3 secs 
+
+Phase 4.2  Initial Placement for Architecture Specific Features
+
+Phase 4.2  Initial Placement for Architecture Specific Features
+(Checksum:e8c062d1) REAL time: 4 secs 
+
+Phase 5.36  Local Placement Optimization
+Phase 5.36  Local Placement Optimization (Checksum:e8c062d1) REAL time: 4 secs 
+
+Phase 6.30  Global Clock Region Assignment
+Phase 6.30  Global Clock Region Assignment (Checksum:e8c062d1) REAL time: 4 secs 
+
+Phase 7.3  Local Placement Optimization
+Phase 7.3  Local Placement Optimization (Checksum:e8c062d1) REAL time: 4 secs 
+
+Phase 8.5  Local Placement Optimization
+Phase 8.5  Local Placement Optimization (Checksum:e8c062d1) REAL time: 4 secs 
+
+Phase 9.8  Global Placement
+..
+..
+Phase 9.8  Global Placement (Checksum:973ccb49) REAL time: 4 secs 
+
+Phase 10.5  Local Placement Optimization
+Phase 10.5  Local Placement Optimization (Checksum:973ccb49) REAL time: 4 secs 
+
+Phase 11.18  Placement Optimization
+Phase 11.18  Placement Optimization (Checksum:ed34dee1) REAL time: 4 secs 
+
+Phase 12.5  Local Placement Optimization
+Phase 12.5  Local Placement Optimization (Checksum:ed34dee1) REAL time: 4 secs 
+
+Phase 13.34  Placement Validation
+Phase 13.34  Placement Validation (Checksum:ed34dee1) REAL time: 4 secs 
+
+Total REAL time to Placer completion: 4 secs 
+Total CPU  time to Placer completion: 4 secs 
+Running post-placement packing...
+Writing output files...
+
+Design Summary
+--------------
+
+Design Summary:
+Number of errors:      0
+Number of warnings:    0
+Slice Logic Utilization:
+  Number of Slice Registers:                    25 out of  11,440    1%
+    Number used as Flip Flops:                  25
+    Number used as Latches:                      0
+    Number used as Latch-thrus:                  0
+    Number used as AND/OR logics:                0
+  Number of Slice LUTs:                         57 out of   5,720    1%
+    Number used as logic:                       57 out of   5,720    1%
+      Number using O6 output only:              34
+      Number using O5 output only:               1
+      Number using O5 and O6:                   22
+      Number used as ROM:                        0
+    Number used as Memory:                       0 out of   1,440    0%
+
+Slice Logic Distribution:
+  Number of occupied Slices:                    15 out of   1,430    1%
+  Number of MUXCYs used:                        24 out of   2,860    1%
+  Number of LUT Flip Flop pairs used:           57
+    Number with an unused Flip Flop:            32 out of      57   56%
+    Number with an unused LUT:                   0 out of      57    0%
+    Number of fully used LUT-FF pairs:          25 out of      57   43%
+    Number of unique control sets:               1
+    Number of slice register sites lost
+      to control set restrictions:               7 out of  11,440    1%
+
+  A LUT Flip Flop pair for this architecture represents one LUT paired with
+  one Flip Flop within a slice.  A control set is a unique combination of
+  clock, reset, set, and enable signals for a registered element.
+  The Slice Logic Distribution report is not meaningful if the design is
+  over-mapped for a non-slice resource or if Placement fails.
+
+IO Utilization:
+  Number of bonded IOBs:                         2 out of     102    1%
+    Number of LOCed IOBs:                        2 out of       2  100%
+
+Specific Feature Utilization:
+  Number of RAMB16BWERs:                         0 out of      32    0%
+  Number of RAMB8BWERs:                          0 out of      64    0%
+  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
+  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
+  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
+    Number used as BUFGs:                        1
+    Number used as BUFGMUX:                      0
+  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
+  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
+  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
+  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
+  Number of BSCANs:                              0 out of       4    0%
+  Number of BUFHs:                               0 out of     128    0%
+  Number of BUFPLLs:                             0 out of       8    0%
+  Number of BUFPLL_MCBs:                         0 out of       4    0%
+  Number of DSP48A1s:                            0 out of      16    0%
+  Number of ICAPs:                               0 out of       1    0%
+  Number of MCBs:                                0 out of       2    0%
+  Number of PCILOGICSEs:                         0 out of       2    0%
+  Number of PLL_ADVs:                            0 out of       2    0%
+  Number of PMVs:                                0 out of       1    0%
+  Number of STARTUPs:                            0 out of       1    0%
+  Number of SUSPEND_SYNCs:                       0 out of       1    0%
+
+Average Fanout of Non-Clock Nets:                3.24
+
+Peak Memory Usage:  654 MB
+Total REAL time to MAP completion:  4 secs 
+Total CPU time to MAP completion:   4 secs 
+
+Mapping completed.
+See MAP report file "led_map.mrp" for details.
diff --git a/led_map.mrp b/led_map.mrp
new file mode 100644
index 0000000..ee48480
--- /dev/null
+++ b/led_map.mrp
@@ -0,0 +1,196 @@
+Release 14.7 Map P.20131013 (lin64)
+Xilinx Mapping Report File for Design 'led'
+
+Design Information
+------------------
+Command Line   : map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol
+high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
+-pr off -lc off -power off -o led_map.ncd led.ngd led.pcf 
+Target Device  : xc6slx9
+Target Package : tqg144
+Target Speed   : -2
+Mapper Version : spartan6 -- $Revision: 1.55 $
+Mapped Date    : Tue Feb 21 22:16:49 2017
+
+Design Summary
+--------------
+Number of errors:      0
+Number of warnings:    0
+Slice Logic Utilization:
+  Number of Slice Registers:                    25 out of  11,440    1%
+    Number used as Flip Flops:                  25
+    Number used as Latches:                      0
+    Number used as Latch-thrus:                  0
+    Number used as AND/OR logics:                0
+  Number of Slice LUTs:                         57 out of   5,720    1%
+    Number used as logic:                       57 out of   5,720    1%
+      Number using O6 output only:              34
+      Number using O5 output only:               1
+      Number using O5 and O6:                   22
+      Number used as ROM:                        0
+    Number used as Memory:                       0 out of   1,440    0%
+
+Slice Logic Distribution:
+  Number of occupied Slices:                    15 out of   1,430    1%
+  Number of MUXCYs used:                        24 out of   2,860    1%
+  Number of LUT Flip Flop pairs used:           57
+    Number with an unused Flip Flop:            32 out of      57   56%
+    Number with an unused LUT:                   0 out of      57    0%
+    Number of fully used LUT-FF pairs:          25 out of      57   43%
+    Number of unique control sets:               1
+    Number of slice register sites lost
+      to control set restrictions:               7 out of  11,440    1%
+
+  A LUT Flip Flop pair for this architecture represents one LUT paired with
+  one Flip Flop within a slice.  A control set is a unique combination of
+  clock, reset, set, and enable signals for a registered element.
+  The Slice Logic Distribution report is not meaningful if the design is
+  over-mapped for a non-slice resource or if Placement fails.
+
+IO Utilization:
+  Number of bonded IOBs:                         2 out of     102    1%
+    Number of LOCed IOBs:                        2 out of       2  100%
+
+Specific Feature Utilization:
+  Number of RAMB16BWERs:                         0 out of      32    0%
+  Number of RAMB8BWERs:                          0 out of      64    0%
+  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
+  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
+  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
+    Number used as BUFGs:                        1
+    Number used as BUFGMUX:                      0
+  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
+  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
+  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
+  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
+  Number of BSCANs:                              0 out of       4    0%
+  Number of BUFHs:                               0 out of     128    0%
+  Number of BUFPLLs:                             0 out of       8    0%
+  Number of BUFPLL_MCBs:                         0 out of       4    0%
+  Number of DSP48A1s:                            0 out of      16    0%
+  Number of ICAPs:                               0 out of       1    0%
+  Number of MCBs:                                0 out of       2    0%
+  Number of PCILOGICSEs:                         0 out of       2    0%
+  Number of PLL_ADVs:                            0 out of       2    0%
+  Number of PMVs:                                0 out of       1    0%
+  Number of STARTUPs:                            0 out of       1    0%
+  Number of SUSPEND_SYNCs:                       0 out of       1    0%
+
+Average Fanout of Non-Clock Nets:                3.24
+
+Peak Memory Usage:  654 MB
+Total REAL time to MAP completion:  4 secs 
+Total CPU time to MAP completion:   4 secs 
+
+Table of Contents
+-----------------
+Section 1 - Errors
+Section 2 - Warnings
+Section 3 - Informational
+Section 4 - Removed Logic Summary
+Section 5 - Removed Logic
+Section 6 - IOB Properties
+Section 7 - RPMs
+Section 8 - Guide Report
+Section 9 - Area Group and Partition Summary
+Section 10 - Timing Report
+Section 11 - Configuration String Information
+Section 12 - Control Set Information
+Section 13 - Utilization by Hierarchy
+
+Section 1 - Errors
+------------------
+
+Section 2 - Warnings
+--------------------
+
+Section 3 - Informational
+-------------------------
+INFO:MapLib:564 - The following environment variables are currently set:
+INFO:MapLib:591 - XIL_MAP_LOCWARN 	Value: 1
+INFO:MapLib:159 - Net Timing constraints on signal CLK are pushed forward
+   through input buffer.
+INFO:LIT:244 - All of the single ended outputs in this design are using slew
+   rate limited output drivers. The delay on speed critical single ended outputs
+   can be dramatically reduced by designating them as fast outputs.
+INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
+   0.000 to 85.000 Celsius)
+INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
+   1.260 Volts)
+INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
+   (.mrp).
+INFO:Pack:1650 - Map created a placed design.
+
+Section 4 - Removed Logic Summary
+---------------------------------
+   2 block(s) optimized away
+
+Section 5 - Removed Logic
+-------------------------
+
+Optimized Block(s):
+TYPE 		BLOCK
+GND 		XST_GND
+VCC 		XST_VCC
+
+To enable printing of redundant blocks removed and signals merged, set the
+detailed map report option and rerun map.
+
+Section 6 - IOB Properties
+--------------------------
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
+|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+| CLK                                | IOB              | INPUT     | LVTTL                |       |          |      |              |          |          |
+| LED1                               | IOB              | OUTPUT    | LVTTL                |       | 8        | SLOW |              |          |          |
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+Section 7 - RPMs
+----------------
+
+Section 8 - Guide Report
+------------------------
+Guide not run on this design.
+
+Section 9 - Area Group and Partition Summary
+--------------------------------------------
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+Area Group Information
+----------------------
+
+  No area groups were found in this design.
+
+----------------------
+
+Section 10 - Timing Report
+--------------------------
+A logic-level (pre-route) timing report can be generated by using Xilinx static
+timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
+mapped NCD and PCF files. Please note that this timing report will be generated
+using estimated delay information. For accurate numbers, please generate a
+timing report with the post Place and Route NCD file.
+
+For more information about the Timing Analyzer, consult the Xilinx Timing
+Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
+Command Line Tools User Guide "TRACE" chapter.
+
+Section 11 - Configuration String Details
+-----------------------------------------
+Use the "-detail" map option to print out Configuration Strings
+
+Section 12 - Control Set Information
+------------------------------------
+Use the "-detail" map option to print out Control Set Information.
+
+Section 13 - Utilization by Hierarchy
+-------------------------------------
+Use the "-detail" map option to print out the Utilization by Hierarchy section.
diff --git a/led_map.ncd b/led_map.ncd
new file mode 100644
index 0000000..c3a8323
--- /dev/null
+++ b/led_map.ncd
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6
+###5660:XlxV32DM    3fff    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diff --git a/led_map.ngm b/led_map.ngm
new file mode 100644
index 0000000..074fadc
--- /dev/null
+++ b/led_map.ngm
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+\ No newline at end of file
diff --git a/led_map.xrpt b/led_map.xrpt
new file mode 100644
index 0000000..3788bef
--- /dev/null
+++ b/led_map.xrpt
@@ -0,0 +1,292 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="lin64" product="ISE" version="14.7">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="Map" timeStamp="Tue Feb 21 22:16:54 2017">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="LD_LIBRARY_PATH"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="XILINX_DSP"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE"/>
+        </row>
+        <row stringID="row" value="2">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/PlanAhead"/>
+        </row>
+        <row stringID="row" value="3">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
+        </row>
+        <row stringID="row" value="4">
+          <item stringID="variable" value="XIL_MAP_LOCWARN"/>
+          <item stringID="value" value="1"/>
+        </row>
+        <row stringID="row" value="5">
+          <item stringID="variable" value="XILINX_EDK"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/EDK"/>
+        </row>
+        <row stringID="row" value="6">
+          <item stringID="variable" value="PATH"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/local/sbin:/usr/local/bin:/usr/bin:/usr/lib/jvm/default/bin:/usr/bin/site_perl:/usr/bin/vendor_perl:/usr/bin/core_perl"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="unknown"/>
+        <item stringID="User_EnvOsrelease" value="unknown"/>
+      </item>
+      <item stringID="User_EnvHost" value="yann-arch"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz"/>
+          <item stringID="speed" value="3100.451 MHz"/>
+        </row>
+      </table>
+    </section>
+    <section stringID="MAP_OPTION_SUMMARY">
+      <item DEFAULT="high" label="-ol" stringID="MAP_EFFORTLEVEL" value="high"/>
+      <item DEFAULT="0" label="-xt" stringID="MAP_EXTRA_COST_TABLE" value="0"/>
+      <item DEFAULT="OFF" label="-ir" stringID="MAP_IGNORERLOCS" value="OFF"/>
+      <item DEFAULT="OFF" stringID="MAP_LUTCOMPRESSIONMODE" value="OFF"/>
+      <item DEFAULT="0" label="-t" stringID="MAP_PLACERCOSTTABLE" value="1"/>
+      <item DEFAULT="4" label="-r" stringID="MAP_REGORDERING" value="4"/>
+      <item DEFAULT="FALSE" stringID="MAP_REPLICATELUTS" value="TRUE"/>
+      <item DEFAULT="None" label="-intstyle" stringID="MAP_INTSTYLE" value="ise"/>
+      <item DEFAULT="off" label="-lc" stringID="MAP_LUT_COMBINING" value="off"/>
+      <item DEFAULT="None" label="-o" stringID="MAP_OUTFILE" value="led_map.ncd"/>
+      <item DEFAULT="false" label="-w" stringID="MAP_OVERWRITE_OUTPUT" value="true"/>
+      <item DEFAULT="off" label="-pr" stringID="MAP_PACK_INTERNAL" value="off"/>
+      <item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx9-tqg144-2"/>
+    </section>
+    <task stringID="MAP_PACK_REPORT">
+      <item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="25">
+        <item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="25"/>
+        <item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
+      </item>
+      <item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="57">
+        <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="1"/>
+        <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="34"/>
+        <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="22"/>
+        <item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
+      </item>
+      <item AVAILABLE="102" dataType="int" stringID="MAP_AGG_BONDED_IO" value="2"/>
+      <item AVAILABLE="98" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
+      <item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
+      <item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
+      <item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
+      <item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
+      <item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
+      <section stringID="MAP_DESIGN_INFORMATION">
+        <item stringID="MAP_PART" value="6slx9tqg144-2"/>
+        <item stringID="MAP_DEVICE" value="xc6slx9"/>
+        <item stringID="MAP_ARCHITECTURE" value="spartan6"/>
+        <item stringID="MAP_PACKAGE" value="tqg144"/>
+        <item stringID="MAP_SPEED" value="-2"/>
+      </section>
+      <section stringID="MAP_DESIGN_SUMMARY">
+        <item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
+        <item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
+        <item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
+        <item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="669832"/>
+        <item stringID="MAP_TOTAL_REAL_TIME" value="4 secs "/>
+        <item stringID="MAP_TOTAL_CPU_TIME" value="4 secs "/>
+      </section>
+      <section stringID="MAP_SLICE_REPORTING">
+        <item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="25">
+          <item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="25"/>
+          <item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
+        </item>
+        <item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="57">
+          <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="1"/>
+          <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="34"/>
+          <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="22"/>
+          <item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
+          <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
+        </item>
+        <item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="15">
+          <item AVAILABLE="355" dataType="int" stringID="MAP_NUM_SLICEL" value="6"/>
+          <item AVAILABLE="360" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
+          <item AVAILABLE="715" dataType="int" stringID="MAP_NUM_SLICEX" value="9"/>
+        </item>
+        <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="57">
+          <item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="32"/>
+          <item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="0"/>
+          <item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="25"/>
+        </item>
+      </section>
+      <section stringID="MAP_IOB_REPORTING">
+        <item AVAILABLE="102" dataType="int" stringID="MAP_AGG_BONDED_IO" value="2"/>
+        <item AVAILABLE="98" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
+        <item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
+        <item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
+        <item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
+        <item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
+        <item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
+      </section>
+      <section stringID="MAP_HARD_IP_REPORTING"/>
+      <section stringID="MAP_RAM_FIFO_DATA">
+        <item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
+        <item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
+      </section>
+      <section stringID="MAP_IP_DATA">
+        <item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
+        <item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
+        <item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
+        <item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
+        <item AVAILABLE="16" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
+        <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
+        <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
+        <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
+      </section>
+      <section stringID="MAP_BUFG_DATA">
+        <item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="1"/>
+        <item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
+        <item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
+      </section>
+      <section stringID="MAP_MACRO_RPM_REPORTING">
+        <item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
+        <item dataType="int" stringID="MAP_RPMS" value="0"/>
+      </section>
+      <section stringID="MAP_IOB_PROPERTIES">
+        <table stringID="MAP_IOB_TABLE">
+          <column label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME"/>
+          <column stringID="Type"/>
+          <column stringID="Direction"/>
+          <column label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD"/>
+          <column label="Diff&#xA;Term" stringID="DIFF_TERM"/>
+          <column label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH"/>
+          <column label="Slew&#xA;Rate" stringID="SLEW_RATE"/>
+          <column label="Reg&#xA;(s)" stringID="REGS"/>
+          <column stringID="Resistor"/>
+          <column label="IOB&#xA;Delay" stringID="IOB_DELAY"/>
+          <row stringID="row" value="1">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="CLK"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="INPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVTTL"/>
+          </row>
+          <row stringID="row" value="2">
+            <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LED1"/>
+            <item stringID="Type" value="IOB"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVTTL"/>
+            <item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="8"/>
+            <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
+          </row>
+        </table>
+      </section>
+      <section stringID="MAP_RPM_MACROS">
+        <section stringID="MAP_SHAPE_SECTION">
+          <item dataType="int" stringID="MAP_NUM_SHAPE" value="1"/>
+        </section>
+      </section>
+      <section stringID="MAP_GUIDE_REPORT"/>
+      <section stringID="MAP_AREA_GROUPS_PARTITIONS"/>
+      <section stringID="MAP_TIMING_REPORT"/>
+      <section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
+      <section stringID="MAP_GENERAL_CONFIG_DATA"/>
+      <section stringID="MAP_CONTROL_SET_INFORMATION">
+        <item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="1"/>
+        <tree stringID="MAP_CONTROL_SET_HIERARCHY">
+          <property stringID="MAP_CLOCK_SIGNAL"/>
+          <property stringID="MAP_RESET_SIGNAL"/>
+          <property stringID="MAP_SET_SIGNAL"/>
+          <property stringID="MAP_ENABLE_SIGNAL"/>
+          <property label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT"/>
+          <property label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT"/>
+        </tree>
+      </section>
+    </task>
+    <section stringID="MAP_RAM_FIFO_DATA">
+      <item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
+      <item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
+    </section>
+    <section stringID="MAP_IP_DATA">
+      <item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
+      <item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
+      <item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
+      <item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
+      <item AVAILABLE="16" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
+      <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
+      <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
+      <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
+      <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
+      <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="0"/>
+      <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
+      <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
+      <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
+    </section>
+    <section stringID="MAP_BUFG_DATA">
+      <item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="1"/>
+      <item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
+      <item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
+      <item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
+      <item dataType="int" stringID="MAP_RPMS" value="0"/>
+    </section>
+  </application>
+
+</document>
diff --git a/led_ngdbuild.xrpt b/led_ngdbuild.xrpt
new file mode 100644
index 0000000..6a2be4e
--- /dev/null
+++ b/led_ngdbuild.xrpt
@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="lin64" product="ISE" version="14.7">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="NgdBuild" timeStamp="Tue Feb 21 22:16:43 2017">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="LD_LIBRARY_PATH"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="XILINX_DSP"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE"/>
+        </row>
+        <row stringID="row" value="2">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/PlanAhead"/>
+        </row>
+        <row stringID="row" value="3">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
+        </row>
+        <row stringID="row" value="4">
+          <item stringID="variable" value="XIL_MAP_LOCWARN"/>
+          <item stringID="value" value="1"/>
+        </row>
+        <row stringID="row" value="5">
+          <item stringID="variable" value="XILINX_EDK"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/EDK"/>
+        </row>
+        <row stringID="row" value="6">
+          <item stringID="variable" value="PATH"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/local/sbin:/usr/local/bin:/usr/bin:/usr/lib/jvm/default/bin:/usr/bin/site_perl:/usr/bin/vendor_perl:/usr/bin/core_perl"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="unknown"/>
+        <item stringID="User_EnvOsrelease" value="unknown"/>
+      </item>
+      <item stringID="User_EnvHost" value="yann-arch"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz"/>
+          <item stringID="speed" value="3099.957 MHz"/>
+        </row>
+      </table>
+    </section>
+    <task stringID="NGDBUILD_OPTION_SUMMARY">
+      <section stringID="NGDBUILD_OPTION_SUMMARY">
+        <item DEFAULT="false" label="-aul" stringID="NGDBUILD_allow_unmatched_locs" value="true"/>
+        <item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
+        <item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
+        <item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc6slx9-tqg144-2"/>
+        <item DEFAULT="None" label="-uc" stringID="NGDBUILD_ucf_file" value="BPC3011-Papilio_Pro-general.ucf"/>
+      </section>
+    </task>
+    <task stringID="NGDBUILD_REPORT">
+      <section stringID="NGDBUILD_DESIGN_SUMMARY">
+        <item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
+        <item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="95"/>
+        <item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="207"/>
+      </section>
+      <section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
+        <item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FD" value="25"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_INV" value="23"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="25"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="8"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="23"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="24"/>
+      </section>
+      <section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
+        <item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_FD" value="25"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_INV" value="23"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="25"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="8"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="23"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
+        <item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="24"/>
+      </section>
+      <section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
+        <section stringID="NGDBUILD_CORE_INSTANCES"/>
+      </section>
+    </task>
+  </application>
+
+</document>
diff --git a/led_pad.csv b/led_pad.csv
new file mode 100644
index 0000000..d406d98
--- /dev/null
+++ b/led_pad.csv
@@ -0,0 +1,175 @@
+#Release 14.7 - par P.20131013 (lin64)
+#Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+#Tue Feb 21 22:16:59 2017
+
+#
+## NOTE: This file is designed to be imported into a spreadsheet program
+# such as Microsoft Excel for viewing, printing and sorting. The |
+# character is used as the data field separator. This file is also designed
+# to support parsing.
+#
+#INPUT FILE:       led_map.ncd
+#OUTPUT FILE:      led_pad.csv
+#PART TYPE:        xc6slx9
+#SPEED GRADE:      -2
+#PACKAGE:          tqg144
+#
+# Pinout by Pin Number:
+# 
+# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
+Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
+P1,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,,
+P2,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,,
+P3,,,GND,,,,,,,,,,,,
+P4,,,VCCO_3,,,3,,,,,any******,,,,
+P5,,IOBS,IO_L52N_3,UNUSED,,3,,,,,,,,,
+P6,,IOBM,IO_L52P_3,UNUSED,,3,,,,,,,,,
+P7,,IOBS,IO_L51N_3,UNUSED,,3,,,,,,,,,
+P8,,IOBM,IO_L51P_3,UNUSED,,3,,,,,,,,,
+P9,,IOBS,IO_L50N_3,UNUSED,,3,,,,,,,,,
+P10,,IOBM,IO_L50P_3,UNUSED,,3,,,,,,,,,
+P11,,IOBS,IO_L49N_3,UNUSED,,3,,,,,,,,,
+P12,,IOBM,IO_L49P_3,UNUSED,,3,,,,,,,,,
+P13,,,GND,,,,,,,,,,,,
+P14,,IOBS,IO_L44N_GCLK20_3,UNUSED,,3,,,,,,,,,
+P15,,IOBM,IO_L44P_GCLK21_3,UNUSED,,3,,,,,,,,,
+P16,,IOBS,IO_L43N_GCLK22_IRDY2_3,UNUSED,,3,,,,,,,,,
+P17,,IOBM,IO_L43P_GCLK23_3,UNUSED,,3,,,,,,,,,
+P18,,,VCCO_3,,,3,,,,,any******,,,,
+P19,,,VCCINT,,,,,,,,1.2,,,,
+P20,,,VCCAUX,,,,,,,,2.5,,,,
+P21,,IOBS,IO_L42N_GCLK24_3,UNUSED,,3,,,,,,,,,
+P22,,IOBM,IO_L42P_GCLK25_TRDY2_3,UNUSED,,3,,,,,,,,,
+P23,,IOBS,IO_L41N_GCLK26_3,UNUSED,,3,,,,,,,,,
+P24,,IOBM,IO_L41P_GCLK27_3,UNUSED,,3,,,,,,,,,
+P25,,,GND,,,,,,,,,,,,
+P26,,IOBS,IO_L37N_3,UNUSED,,3,,,,,,,,,
+P27,,IOBM,IO_L37P_3,UNUSED,,3,,,,,,,,,
+P28,,,VCCINT,,,,,,,,1.2,,,,
+P29,,IOBS,IO_L36N_3,UNUSED,,3,,,,,,,,,
+P30,,IOBM,IO_L36P_3,UNUSED,,3,,,,,,,,,
+P31,,,VCCO_3,,,3,,,,,any******,,,,
+P32,,IOBS,IO_L2N_3,UNUSED,,3,,,,,,,,,
+P33,,IOBM,IO_L2P_3,UNUSED,,3,,,,,,,,,
+P34,,IOBS,IO_L1N_VREF_3,UNUSED,,3,,,,,,,,,
+P35,,IOBM,IO_L1P_3,UNUSED,,3,,,,,,,,,
+P36,,,VCCAUX,,,,,,,,2.5,,,,
+P37,,,PROGRAM_B_2,,,,,,,,,,,,
+P38,,IOBS,IO_L65N_CSO_B_2,UNUSED,,2,,,,,,,,,
+P39,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,,
+P40,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,,
+P41,,IOBM,IO_L64P_D8_2,UNUSED,,2,,,,,,,,,
+P42,,,VCCO_2,,,2,,,,,any******,,,,
+P43,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,,
+P44,,IOBM,IO_L62P_D5_2,UNUSED,,2,,,,,,,,,
+P45,,IOBS,IO_L49N_D4_2,UNUSED,,2,,,,,,,,,
+P46,,IOBM,IO_L49P_D3_2,UNUSED,,2,,,,,,,,,
+P47,,IOBS,IO_L48N_RDWR_B_VREF_2,UNUSED,,2,,,,,,,,,
+P48,,IOBM,IO_L48P_D7_2,UNUSED,,2,,,,,,,,,
+P49,,,GND,,,,,,,,,,,,
+P50,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,,
+P51,,IOBM,IO_L31P_GCLK31_D14_2,UNUSED,,2,,,,,,,,,
+P52,,,VCCINT,,,,,,,,1.2,,,,
+P53,,,VCCAUX,,,,,,,,2.5,,,,
+P54,,,GND,,,,,,,,,,,,
+P55,,IOBS,IO_L30N_GCLK0_USERCCLK_2,UNUSED,,2,,,,,,,,,
+P56,,IOBM,IO_L30P_GCLK1_D13_2,UNUSED,,2,,,,,,,,,
+P57,,IOBS,IO_L14N_D12_2,UNUSED,,2,,,,,,,,,
+P58,,IOBM,IO_L14P_D11_2,UNUSED,,2,,,,,,,,,
+P59,,IOBS,IO_L13N_D10_2,UNUSED,,2,,,,,,,,,
+P60,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,PROHIBITED,,,
+P61,,IOBS,IO_L12N_D2_MISO3_2,UNUSED,,2,,,,,,,,,
+P62,,IOBM,IO_L12P_D1_MISO2_2,UNUSED,,2,,,,,,,,,
+P63,,,VCCO_2,,,2,,,,,any******,,,,
+P64,,IOBS,IO_L3N_MOSI_CSI_B_MISO0_2,UNUSED,,2,,,,,,,,,
+P65,,IOBM,IO_L3P_D0_DIN_MISO_MISO1_2,UNUSED,,2,,,,,,,,,
+P66,,IOBS,IO_L2N_CMPMOSI_2,UNUSED,,2,,,,,,,,,
+P67,,IOBM,IO_L2P_CMPCLK_2,UNUSED,,2,,,,,,,,,
+P68,,,GND,,,,,,,,,,,,
+P69,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,PROHIBITED,,,
+P70,,IOBM,IO_L1P_CCLK_2,UNUSED,,2,,,,,,,,,
+P71,,,DONE_2,,,,,,,,,,,,
+P72,,,CMPCS_B_2,,,,,,,,,,,,
+P73,,,SUSPEND,,,,,,,,,,,,
+P74,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,,
+P75,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,,
+P76,,,VCCO_1,,,1,,,,,any******,,,,
+P77,,,GND,,,,,,,,,,,,
+P78,,IOBS,IO_L47N_1,UNUSED,,1,,,,,,,,,
+P79,,IOBM,IO_L47P_1,UNUSED,,1,,,,,,,,,
+P80,,IOBS,IO_L46N_1,UNUSED,,1,,,,,,,,,
+P81,,IOBM,IO_L46P_1,UNUSED,,1,,,,,,,,,
+P82,,IOBS,IO_L45N_1,UNUSED,,1,,,,,,,,,
+P83,,IOBM,IO_L45P_1,UNUSED,,1,,,,,,,,,
+P84,,IOBS,IO_L43N_GCLK4_1,UNUSED,,1,,,,,,,,,
+P85,,IOBM,IO_L43P_GCLK5_1,UNUSED,,1,,,,,,,,,
+P86,,,VCCO_1,,,1,,,,,any******,,,,
+P87,,IOBS,IO_L42N_GCLK6_TRDY1_1,UNUSED,,1,,,,,,,,,
+P88,,IOBM,IO_L42P_GCLK7_1,UNUSED,,1,,,,,,,,,
+P89,,,VCCINT,,,,,,,,1.2,,,,
+P90,,,VCCAUX,,,,,,,,2.5,,,,
+P91,,,GND,,,,,,,,,,,,
+P92,,IOBS,IO_L41N_GCLK8_1,UNUSED,,1,,,,,,,,,
+P93,,IOBM,IO_L41P_GCLK9_IRDY1_1,UNUSED,,1,,,,,,,,,
+P94,CLK,IOB,IO_L40N_GCLK10_1,INPUT,LVTTL,1,,,,NONE,,LOCATED,NO,NONE,
+P95,,IOBM,IO_L40P_GCLK11_1,UNUSED,,1,,,,,,,,,
+P96,,,GND,,,,,,,,,,,,
+P97,,IOBS,IO_L34N_1,UNUSED,,1,,,,,,,,,
+P98,,IOBM,IO_L34P_1,UNUSED,,1,,,,,,,,,
+P99,,IOBS,IO_L33N_1,UNUSED,,1,,,,,,,,,
+P100,,IOBM,IO_L33P_1,UNUSED,,1,,,,,,,,,
+P101,,IOBS,IO_L32N_1,UNUSED,,1,,,,,,,,,
+P102,,IOBM,IO_L32P_1,UNUSED,,1,,,,,,,,,
+P103,,,VCCO_1,,,1,,,,,any******,,,,
+P104,,IOBS,IO_L1N_VREF_1,UNUSED,,1,,,,,,,,,
+P105,,IOBM,IO_L1P_1,UNUSED,,1,,,,,,,,,
+P106,,,TDO,,,,,,,,,,,,
+P107,,,TMS,,,,,,,,,,,,
+P108,,,GND,,,,,,,,,,,,
+P109,,,TCK,,,,,,,,,,,,
+P110,,,TDI,,,,,,,,,,,,
+P111,,IOBS,IO_L66N_SCP0_0,UNUSED,,0,,,,,,,,,
+P112,LED1,IOB,IO_L66P_SCP1_0,OUTPUT,LVTTL,0,8,SLOW,,,,LOCATED,NO,NONE,
+P113,,,GND,,,,,,,,,,,,
+P114,,IOBS,IO_L65N_SCP2_0,UNUSED,,0,,,,,,,,,
+P115,,IOBM,IO_L65P_SCP3_0,UNUSED,,0,,,,,,,,,
+P116,,IOBS,IO_L64N_SCP4_0,UNUSED,,0,,,,,,,,,
+P117,,IOBM,IO_L64P_SCP5_0,UNUSED,,0,,,,,,,,,
+P118,,IOBS,IO_L63N_SCP6_0,UNUSED,,0,,,,,,,,,
+P119,,IOBM,IO_L63P_SCP7_0,UNUSED,,0,,,,,,,,,
+P120,,IOBS,IO_L62N_VREF_0,UNUSED,,0,,,,,,,,,
+P121,,IOBM,IO_L62P_0,UNUSED,,0,,,,,,,,,
+P122,,,VCCO_0,,,0,,,,,3.30,,,,
+P123,,IOBS,IO_L37N_GCLK12_0,UNUSED,,0,,,,,,,,,
+P124,,IOBM,IO_L37P_GCLK13_0,UNUSED,,0,,,,,,,,,
+P125,,,VCCO_0,,,0,,,,,3.30,,,,
+P126,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,,
+P127,,IOBM,IO_L36P_GCLK15_0,UNUSED,,0,,,,,,,,,
+P128,,,VCCINT,,,,,,,,1.2,,,,
+P129,,,VCCAUX,,,,,,,,2.5,,,,
+P130,,,GND,,,,,,,,,,,,
+P131,,IOBS,IO_L35N_GCLK16_0,UNUSED,,0,,,,,,,,,
+P132,,IOBM,IO_L35P_GCLK17_0,UNUSED,,0,,,,,,,,,
+P133,,IOBS,IO_L34N_GCLK18_0,UNUSED,,0,,,,,,,,,
+P134,,IOBM,IO_L34P_GCLK19_0,UNUSED,,0,,,,,,,,,
+P135,,,VCCO_0,,,0,,,,,3.30,,,,
+P136,,,GND,,,,,,,,,,,,
+P137,,IOBS,IO_L4N_0,UNUSED,,0,,,,,,,,,
+P138,,IOBM,IO_L4P_0,UNUSED,,0,,,,,,,,,
+P139,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,,
+P140,,IOBM,IO_L3P_0,UNUSED,,0,,,,,,,,,
+P141,,IOBS,IO_L2N_0,UNUSED,,0,,,,,,,,,
+P142,,IOBM,IO_L2P_0,UNUSED,,0,,,,,,,,,
+P143,,IOBS,IO_L1N_VREF_0,UNUSED,,0,,,,,,,,,
+P144,,IOBM,IO_L1P_HSWAPEN_0,UNUSED,,0,,,,,,PROHIBITED,,,
+
+# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
+# 
+#* Default value.
+#** This default Pullup/Pulldown value can be overridden in Bitgen. 
+#****** Special VCCO requirements may apply. Please consult the device 
+#       family datasheet for specific guideline on VCCO requirements. 
+#
+#
+#
+\ No newline at end of file
diff --git a/led_pad.txt b/led_pad.txt
new file mode 100644
index 0000000..b8a53a3
--- /dev/null
+++ b/led_pad.txt
@@ -0,0 +1,174 @@
+Release 14.7 - par P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Tue Feb 21 22:16:59 2017
+
+
+INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process.  These formats are:
+1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
+2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
+3. The <design name>.pad file designed for parsing by customers.  It uses the "|" as a data field separator.
+
+INPUT FILE:       led_map.ncd
+OUTPUT FILE:      led_pad.txt
+PART TYPE:        xc6slx9
+SPEED GRADE:      -2
+PACKAGE:          tqg144
+
+Pinout by Pin Number:
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+|Pin Number|Signal Name|Pin Usage|Pin Name                  |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage  |Constraint|IO Register|Signal Integrity|
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+|P1        |           |IOBS     |IO_L83N_VREF_3            |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P2        |           |IOBM     |IO_L83P_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P3        |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P4        |           |         |VCCO_3                    |         |           |3             |          |         |           |         |any******|          |           |                |
+|P5        |           |IOBS     |IO_L52N_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P6        |           |IOBM     |IO_L52P_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P7        |           |IOBS     |IO_L51N_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P8        |           |IOBM     |IO_L51P_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P9        |           |IOBS     |IO_L50N_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P10       |           |IOBM     |IO_L50P_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P11       |           |IOBS     |IO_L49N_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P12       |           |IOBM     |IO_L49P_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P13       |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P14       |           |IOBS     |IO_L44N_GCLK20_3          |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P15       |           |IOBM     |IO_L44P_GCLK21_3          |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P16       |           |IOBS     |IO_L43N_GCLK22_IRDY2_3    |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P17       |           |IOBM     |IO_L43P_GCLK23_3          |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P18       |           |         |VCCO_3                    |         |           |3             |          |         |           |         |any******|          |           |                |
+|P19       |           |         |VCCINT                    |         |           |              |          |         |           |         |1.2      |          |           |                |
+|P20       |           |         |VCCAUX                    |         |           |              |          |         |           |         |2.5      |          |           |                |
+|P21       |           |IOBS     |IO_L42N_GCLK24_3          |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P22       |           |IOBM     |IO_L42P_GCLK25_TRDY2_3    |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P23       |           |IOBS     |IO_L41N_GCLK26_3          |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P24       |           |IOBM     |IO_L41P_GCLK27_3          |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P25       |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P26       |           |IOBS     |IO_L37N_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P27       |           |IOBM     |IO_L37P_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P28       |           |         |VCCINT                    |         |           |              |          |         |           |         |1.2      |          |           |                |
+|P29       |           |IOBS     |IO_L36N_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P30       |           |IOBM     |IO_L36P_3                 |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P31       |           |         |VCCO_3                    |         |           |3             |          |         |           |         |any******|          |           |                |
+|P32       |           |IOBS     |IO_L2N_3                  |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P33       |           |IOBM     |IO_L2P_3                  |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P34       |           |IOBS     |IO_L1N_VREF_3             |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P35       |           |IOBM     |IO_L1P_3                  |UNUSED   |           |3             |          |         |           |         |         |          |           |                |
+|P36       |           |         |VCCAUX                    |         |           |              |          |         |           |         |2.5      |          |           |                |
+|P37       |           |         |PROGRAM_B_2               |         |           |              |          |         |           |         |         |          |           |                |
+|P38       |           |IOBS     |IO_L65N_CSO_B_2           |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P39       |           |IOBM     |IO_L65P_INIT_B_2          |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P40       |           |IOBS     |IO_L64N_D9_2              |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P41       |           |IOBM     |IO_L64P_D8_2              |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P42       |           |         |VCCO_2                    |         |           |2             |          |         |           |         |any******|          |           |                |
+|P43       |           |IOBS     |IO_L62N_D6_2              |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P44       |           |IOBM     |IO_L62P_D5_2              |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P45       |           |IOBS     |IO_L49N_D4_2              |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P46       |           |IOBM     |IO_L49P_D3_2              |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P47       |           |IOBS     |IO_L48N_RDWR_B_VREF_2     |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P48       |           |IOBM     |IO_L48P_D7_2              |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P49       |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P50       |           |IOBS     |IO_L31N_GCLK30_D15_2      |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P51       |           |IOBM     |IO_L31P_GCLK31_D14_2      |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P52       |           |         |VCCINT                    |         |           |              |          |         |           |         |1.2      |          |           |                |
+|P53       |           |         |VCCAUX                    |         |           |              |          |         |           |         |2.5      |          |           |                |
+|P54       |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P55       |           |IOBS     |IO_L30N_GCLK0_USERCCLK_2  |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P56       |           |IOBM     |IO_L30P_GCLK1_D13_2       |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P57       |           |IOBS     |IO_L14N_D12_2             |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P58       |           |IOBM     |IO_L14P_D11_2             |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P59       |           |IOBS     |IO_L13N_D10_2             |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P60       |           |IOBM     |IO_L13P_M1_2              |UNUSED   |           |2             |          |         |           |         |         |PROHIBITED|           |                |
+|P61       |           |IOBS     |IO_L12N_D2_MISO3_2        |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P62       |           |IOBM     |IO_L12P_D1_MISO2_2        |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P63       |           |         |VCCO_2                    |         |           |2             |          |         |           |         |any******|          |           |                |
+|P64       |           |IOBS     |IO_L3N_MOSI_CSI_B_MISO0_2 |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P65       |           |IOBM     |IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P66       |           |IOBS     |IO_L2N_CMPMOSI_2          |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P67       |           |IOBM     |IO_L2P_CMPCLK_2           |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P68       |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P69       |           |IOBS     |IO_L1N_M0_CMPMISO_2       |UNUSED   |           |2             |          |         |           |         |         |PROHIBITED|           |                |
+|P70       |           |IOBM     |IO_L1P_CCLK_2             |UNUSED   |           |2             |          |         |           |         |         |          |           |                |
+|P71       |           |         |DONE_2                    |         |           |              |          |         |           |         |         |          |           |                |
+|P72       |           |         |CMPCS_B_2                 |         |           |              |          |         |           |         |         |          |           |                |
+|P73       |           |         |SUSPEND                   |         |           |              |          |         |           |         |         |          |           |                |
+|P74       |           |IOBS     |IO_L74N_DOUT_BUSY_1       |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P75       |           |IOBM     |IO_L74P_AWAKE_1           |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P76       |           |         |VCCO_1                    |         |           |1             |          |         |           |         |any******|          |           |                |
+|P77       |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P78       |           |IOBS     |IO_L47N_1                 |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P79       |           |IOBM     |IO_L47P_1                 |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P80       |           |IOBS     |IO_L46N_1                 |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P81       |           |IOBM     |IO_L46P_1                 |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P82       |           |IOBS     |IO_L45N_1                 |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P83       |           |IOBM     |IO_L45P_1                 |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P84       |           |IOBS     |IO_L43N_GCLK4_1           |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P85       |           |IOBM     |IO_L43P_GCLK5_1           |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P86       |           |         |VCCO_1                    |         |           |1             |          |         |           |         |any******|          |           |                |
+|P87       |           |IOBS     |IO_L42N_GCLK6_TRDY1_1     |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P88       |           |IOBM     |IO_L42P_GCLK7_1           |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P89       |           |         |VCCINT                    |         |           |              |          |         |           |         |1.2      |          |           |                |
+|P90       |           |         |VCCAUX                    |         |           |              |          |         |           |         |2.5      |          |           |                |
+|P91       |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P92       |           |IOBS     |IO_L41N_GCLK8_1           |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P93       |           |IOBM     |IO_L41P_GCLK9_IRDY1_1     |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P94       |CLK        |IOB      |IO_L40N_GCLK10_1          |INPUT    |LVTTL      |1             |          |         |           |NONE     |         |LOCATED   |NO         |NONE            |
+|P95       |           |IOBM     |IO_L40P_GCLK11_1          |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P96       |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P97       |           |IOBS     |IO_L34N_1                 |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P98       |           |IOBM     |IO_L34P_1                 |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P99       |           |IOBS     |IO_L33N_1                 |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P100      |           |IOBM     |IO_L33P_1                 |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P101      |           |IOBS     |IO_L32N_1                 |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P102      |           |IOBM     |IO_L32P_1                 |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P103      |           |         |VCCO_1                    |         |           |1             |          |         |           |         |any******|          |           |                |
+|P104      |           |IOBS     |IO_L1N_VREF_1             |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P105      |           |IOBM     |IO_L1P_1                  |UNUSED   |           |1             |          |         |           |         |         |          |           |                |
+|P106      |           |         |TDO                       |         |           |              |          |         |           |         |         |          |           |                |
+|P107      |           |         |TMS                       |         |           |              |          |         |           |         |         |          |           |                |
+|P108      |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P109      |           |         |TCK                       |         |           |              |          |         |           |         |         |          |           |                |
+|P110      |           |         |TDI                       |         |           |              |          |         |           |         |         |          |           |                |
+|P111      |           |IOBS     |IO_L66N_SCP0_0            |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P112      |LED1       |IOB      |IO_L66P_SCP1_0            |OUTPUT   |LVTTL      |0             |8         |SLOW     |           |         |         |LOCATED   |NO         |NONE            |
+|P113      |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P114      |           |IOBS     |IO_L65N_SCP2_0            |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P115      |           |IOBM     |IO_L65P_SCP3_0            |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P116      |           |IOBS     |IO_L64N_SCP4_0            |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P117      |           |IOBM     |IO_L64P_SCP5_0            |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P118      |           |IOBS     |IO_L63N_SCP6_0            |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P119      |           |IOBM     |IO_L63P_SCP7_0            |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P120      |           |IOBS     |IO_L62N_VREF_0            |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P121      |           |IOBM     |IO_L62P_0                 |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P122      |           |         |VCCO_0                    |         |           |0             |          |         |           |         |3.30     |          |           |                |
+|P123      |           |IOBS     |IO_L37N_GCLK12_0          |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P124      |           |IOBM     |IO_L37P_GCLK13_0          |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P125      |           |         |VCCO_0                    |         |           |0             |          |         |           |         |3.30     |          |           |                |
+|P126      |           |IOBS     |IO_L36N_GCLK14_0          |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P127      |           |IOBM     |IO_L36P_GCLK15_0          |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P128      |           |         |VCCINT                    |         |           |              |          |         |           |         |1.2      |          |           |                |
+|P129      |           |         |VCCAUX                    |         |           |              |          |         |           |         |2.5      |          |           |                |
+|P130      |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P131      |           |IOBS     |IO_L35N_GCLK16_0          |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P132      |           |IOBM     |IO_L35P_GCLK17_0          |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P133      |           |IOBS     |IO_L34N_GCLK18_0          |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P134      |           |IOBM     |IO_L34P_GCLK19_0          |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P135      |           |         |VCCO_0                    |         |           |0             |          |         |           |         |3.30     |          |           |                |
+|P136      |           |         |GND                       |         |           |              |          |         |           |         |         |          |           |                |
+|P137      |           |IOBS     |IO_L4N_0                  |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P138      |           |IOBM     |IO_L4P_0                  |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P139      |           |IOBS     |IO_L3N_0                  |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P140      |           |IOBM     |IO_L3P_0                  |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P141      |           |IOBS     |IO_L2N_0                  |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P142      |           |IOBM     |IO_L2P_0                  |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P143      |           |IOBS     |IO_L1N_VREF_0             |UNUSED   |           |0             |          |         |           |         |         |          |           |                |
+|P144      |           |IOBM     |IO_L1P_HSWAPEN_0          |UNUSED   |           |0             |          |         |           |         |         |PROHIBITED|           |                |
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+* Default value.
+** This default Pullup/Pulldown value can be overridden in Bitgen. 
+****** Special VCCO requirements may apply. Please consult the device 
+       family datasheet for specific guideline on VCCO requirements. 
+
+
diff --git a/led_par.xrpt b/led_par.xrpt
new file mode 100644
index 0000000..76e44d4
--- /dev/null
+++ b/led_par.xrpt
@@ -0,0 +1,1191 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="lin64" product="ISE" version="14.7">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="par" timeStamp="Tue Feb 21 22:16:58 2017">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="LD_LIBRARY_PATH"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="XILINX_DSP"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE"/>
+        </row>
+        <row stringID="row" value="2">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/PlanAhead"/>
+        </row>
+        <row stringID="row" value="3">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
+        </row>
+        <row stringID="row" value="4">
+          <item stringID="variable" value="XIL_MAP_LOCWARN"/>
+          <item stringID="value" value="1"/>
+        </row>
+        <row stringID="row" value="5">
+          <item stringID="variable" value="XILINX_EDK"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/EDK"/>
+        </row>
+        <row stringID="row" value="6">
+          <item stringID="variable" value="PATH"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/local/sbin:/usr/local/bin:/usr/bin:/usr/lib/jvm/default/bin:/usr/bin/site_perl:/usr/bin/vendor_perl:/usr/bin/core_perl"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="unknown"/>
+        <item stringID="User_EnvOsrelease" value="unknown"/>
+      </item>
+      <item stringID="User_EnvHost" value="yann-arch"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz"/>
+          <item stringID="speed" value="3099.957 MHz"/>
+        </row>
+      </table>
+    </section>
+    <task stringID="PAR_OPTION_SUMMARY">
+      <section stringID="PAR_OPTION_SUMMARY">
+        <item DEFAULT="" label="-intstyle" stringID="PAR_INTSTYLE" value="ise"/>
+        <item DEFAULT="off" label="-mt" stringID="PAR_MULTI_THREADING" value="off"/>
+        <item DEFAULT="std" label="-ol" stringID="PAR_OVERALL_EFFORTLEVEL" value="high"/>
+        <item DEFAULT="false" label="-w" stringID="PAR_OVERWRITE_OUTPUT" value="true"/>
+      </section>
+    </task>
+    <task stringID="PAR_PAR">
+      <section stringID="PAR_DESIGN_SUMMARY">
+        <item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="3 secs "/>
+        <item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="3 secs "/>
+        <item dataType="int" stringID="PAR_UNROUTES" value="0"/>
+        <item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
+        <item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="3 secs "/>
+        <item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="3 secs "/>
+      </section>
+    </task>
+    <task stringID="PAR_par">
+      <section stringID="PAR_DLY_CLK_REPORT"/>
+      <section stringID="PAR_CLOCK_REPORT">
+        <table stringID="PAR_CLOCK_TABLE">
+          <column label="Clock Net" stringID="CLOCK_NET"/>
+          <column label="Routed" stringID="ROUTED"/>
+          <column label="Resource" stringID="RESOURCE"/>
+          <column label="Locked" stringID="LOCKED"/>
+          <column label="Fanout" stringID="FANOUT"/>
+          <column label="Net Skew(ns)" stringID="NET_SKEW"/>
+          <column label="Max Delay(ns)" stringID="MAX_DELAY"/>
+          <row stringID="row" value="1">
+            <item label="Clock Net" stringID="CLOCK_NET" value="CLK_BUFGP"/>
+            <item label="Routed" stringID="ROUTED" value="ROUTED"/>
+            <item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y2"/>
+            <item label="Locked" stringID="LOCKED" value="No"/>
+            <item dataType="float" label="Fanout" stringID="FANOUT" value="8.000000"/>
+            <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.005000"/>
+            <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.395000"/>
+          </row>
+        </table>
+      </section>
+      <section stringID="PAR_PAD_PIN_REPORT">
+        <table stringID="PAR_PINOUT_BY_PIN_NUMBER">
+          <column label="Pin&#xA;Number" sort="smart" stringID="Pin_Number"/>
+          <column label="Signal&#xA;Name" stringID="Signal_Name"/>
+          <column label="Pin&#xA;Usage" stringID="Pin_Usage"/>
+          <column label="Pin&#xA;Name" sort="smart" stringID="Pin_Name"/>
+          <column stringID="Direction"/>
+          <column label="IO&#xA;Standard" sort="smart" stringID="IO_Standard"/>
+          <column label="IO Bank&#xA;Number" stringID="IO_Bank_Number"/>
+          <column label="Drive&#xA;(mA)" stringID="Drive"/>
+          <column label="Slew&#xA;Rate" stringID="Slew_Rate"/>
+          <column label="Termination" stringID="Termination"/>
+          <column label="IOB&#xA;Delay" stringID="IOB_Delay"/>
+          <column label="Voltage" stringID="Voltage"/>
+          <column label="Constraint" stringID="Constraint"/>
+          <column label="IO&#xA;Register" stringID="IO_Register"/>
+          <column label="Signal&#xA;Integrity" stringID="Signal_Integrity"/>
+          <row stringID="row" value="1">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P1"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L83N_VREF_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="2">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P2"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L83P_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="3">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P3"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="4">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P4"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Voltage" stringID="Voltage" value="any******"/>
+          </row>
+          <row stringID="row" value="5">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P5"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L52N_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="6">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P6"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L52P_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="7">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P7"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L51N_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="8">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P8"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L51P_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="9">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P9"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L50N_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="10">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P10"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L50P_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="11">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P11"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L49N_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="12">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P12"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L49P_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="13">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P13"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="14">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P14"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L44N_GCLK20_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="15">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P15"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L44P_GCLK21_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="16">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P16"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L43N_GCLK22_IRDY2_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="17">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P17"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L43P_GCLK23_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="18">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P18"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Voltage" stringID="Voltage" value="any******"/>
+          </row>
+          <row stringID="row" value="19">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P19"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
+            <item label="Voltage" stringID="Voltage" value="1.2"/>
+          </row>
+          <row stringID="row" value="20">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P20"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
+            <item label="Voltage" stringID="Voltage" value="2.5"/>
+          </row>
+          <row stringID="row" value="21">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P21"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L42N_GCLK24_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="22">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P22"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L42P_GCLK25_TRDY2_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="23">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P23"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L41N_GCLK26_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="24">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P24"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L41P_GCLK27_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="25">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P25"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="26">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P26"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L37N_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="27">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P27"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L37P_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="28">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P28"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
+            <item label="Voltage" stringID="Voltage" value="1.2"/>
+          </row>
+          <row stringID="row" value="29">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P29"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L36N_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="30">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P30"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L36P_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="31">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P31"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_3"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+            <item label="Voltage" stringID="Voltage" value="any******"/>
+          </row>
+          <row stringID="row" value="32">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P32"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L2N_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="33">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P33"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L2P_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="34">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P34"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1N_VREF_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="35">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P35"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1P_3"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
+          </row>
+          <row stringID="row" value="36">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P36"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
+            <item label="Voltage" stringID="Voltage" value="2.5"/>
+          </row>
+          <row stringID="row" value="37">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P37"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="PROGRAM_B_2"/>
+          </row>
+          <row stringID="row" value="38">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P38"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L65N_CSO_B_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="39">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P39"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L65P_INIT_B_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="40">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P40"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L64N_D9_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="41">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P41"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L64P_D8_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="42">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P42"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_2"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+            <item label="Voltage" stringID="Voltage" value="any******"/>
+          </row>
+          <row stringID="row" value="43">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P43"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L62N_D6_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="44">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P44"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L62P_D5_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="45">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P45"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L49N_D4_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="46">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P46"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L49P_D3_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="47">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P47"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L48N_RDWR_B_VREF_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="48">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P48"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L48P_D7_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="49">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P49"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="50">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P50"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L31N_GCLK30_D15_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="51">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P51"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L31P_GCLK31_D14_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="52">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P52"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
+            <item label="Voltage" stringID="Voltage" value="1.2"/>
+          </row>
+          <row stringID="row" value="53">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P53"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
+            <item label="Voltage" stringID="Voltage" value="2.5"/>
+          </row>
+          <row stringID="row" value="54">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P54"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="55">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P55"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L30N_GCLK0_USERCCLK_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="56">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P56"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L30P_GCLK1_D13_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="57">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P57"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L14N_D12_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="58">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P58"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L14P_D11_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="59">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P59"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L13N_D10_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="60">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P60"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L13P_M1_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+            <item label="Constraint" stringID="Constraint" value="PROHIBITED"/>
+          </row>
+          <row stringID="row" value="61">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P61"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L12N_D2_MISO3_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="62">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P62"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L12P_D1_MISO2_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="63">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P63"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_2"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+            <item label="Voltage" stringID="Voltage" value="any******"/>
+          </row>
+          <row stringID="row" value="64">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P64"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L3N_MOSI_CSI_B_MISO0_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="65">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P65"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L3P_D0_DIN_MISO_MISO1_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="66">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P66"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L2N_CMPMOSI_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="67">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P67"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L2P_CMPCLK_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="68">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P68"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="69">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P69"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1N_M0_CMPMISO_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+            <item label="Constraint" stringID="Constraint" value="PROHIBITED"/>
+          </row>
+          <row stringID="row" value="70">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P70"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1P_CCLK_2"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="2"/>
+          </row>
+          <row stringID="row" value="71">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P71"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="DONE_2"/>
+          </row>
+          <row stringID="row" value="72">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P72"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="CMPCS_B_2"/>
+          </row>
+          <row stringID="row" value="73">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P73"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="SUSPEND"/>
+          </row>
+          <row stringID="row" value="74">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P74"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L74N_DOUT_BUSY_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="75">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P75"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L74P_AWAKE_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="76">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P76"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_1"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+            <item label="Voltage" stringID="Voltage" value="any******"/>
+          </row>
+          <row stringID="row" value="77">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P77"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="78">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P78"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L47N_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="79">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P79"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L47P_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="80">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P80"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L46N_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="81">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P81"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L46P_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="82">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P82"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L45N_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="83">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P83"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L45P_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="84">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P84"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L43N_GCLK4_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="85">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P85"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L43P_GCLK5_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="86">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P86"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_1"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+            <item label="Voltage" stringID="Voltage" value="any******"/>
+          </row>
+          <row stringID="row" value="87">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P87"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L42N_GCLK6_TRDY1_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="88">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P88"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L42P_GCLK7_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="89">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P89"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
+            <item label="Voltage" stringID="Voltage" value="1.2"/>
+          </row>
+          <row stringID="row" value="90">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P90"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
+            <item label="Voltage" stringID="Voltage" value="2.5"/>
+          </row>
+          <row stringID="row" value="91">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P91"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="92">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P92"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L41N_GCLK8_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="93">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P93"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L41P_GCLK9_IRDY1_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="94">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P94"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="CLK"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L40N_GCLK10_1"/>
+            <item stringID="Direction" value="INPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVTTL"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+            <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="95">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P95"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L40P_GCLK11_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="96">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P96"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="97">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P97"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L34N_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="98">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P98"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L34P_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="99">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P99"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L33N_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="100">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P100"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L33P_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="101">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P101"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L32N_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="102">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P102"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L32P_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="103">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P103"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_1"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+            <item label="Voltage" stringID="Voltage" value="any******"/>
+          </row>
+          <row stringID="row" value="104">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P104"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1N_VREF_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="105">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P105"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1P_1"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
+          </row>
+          <row stringID="row" value="106">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P106"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="TDO"/>
+          </row>
+          <row stringID="row" value="107">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P107"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="TMS"/>
+          </row>
+          <row stringID="row" value="108">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P108"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="109">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P109"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="TCK"/>
+          </row>
+          <row stringID="row" value="110">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P110"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="TDI"/>
+          </row>
+          <row stringID="row" value="111">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P111"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L66N_SCP0_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="112">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P112"/>
+            <item label="Signal&#xA;Name" stringID="Signal_Name" value="LED1"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L66P_SCP1_0"/>
+            <item stringID="Direction" value="OUTPUT"/>
+            <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVTTL"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Drive&#xA;(mA)" stringID="Drive" value="8"/>
+            <item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
+            <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+            <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+            <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
+          </row>
+          <row stringID="row" value="113">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P113"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="114">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P114"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L65N_SCP2_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="115">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P115"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L65P_SCP3_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="116">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P116"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L64N_SCP4_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="117">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P117"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L64P_SCP5_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="118">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P118"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L63N_SCP6_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="119">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P119"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L63P_SCP7_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="120">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P120"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L62N_VREF_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="121">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P121"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L62P_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="122">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P122"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_0"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Voltage" stringID="Voltage" value="3.30"/>
+          </row>
+          <row stringID="row" value="123">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P123"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L37N_GCLK12_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="124">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P124"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L37P_GCLK13_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="125">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P125"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_0"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Voltage" stringID="Voltage" value="3.30"/>
+          </row>
+          <row stringID="row" value="126">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P126"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L36N_GCLK14_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="127">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P127"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L36P_GCLK15_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="128">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P128"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
+            <item label="Voltage" stringID="Voltage" value="1.2"/>
+          </row>
+          <row stringID="row" value="129">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P129"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
+            <item label="Voltage" stringID="Voltage" value="2.5"/>
+          </row>
+          <row stringID="row" value="130">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P130"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="131">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P131"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L35N_GCLK16_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="132">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P132"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L35P_GCLK17_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="133">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P133"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L34N_GCLK18_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="134">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P134"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L34P_GCLK19_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="135">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P135"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="VCCO_0"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Voltage" stringID="Voltage" value="3.30"/>
+          </row>
+          <row stringID="row" value="136">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P136"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="GND"/>
+          </row>
+          <row stringID="row" value="137">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P137"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L4N_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="138">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P138"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L4P_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="139">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P139"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L3N_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="140">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P140"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L3P_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="141">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P141"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L2N_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="142">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P142"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L2P_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="143">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P143"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1N_VREF_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+          </row>
+          <row stringID="row" value="144">
+            <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="P144"/>
+            <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
+            <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1P_HSWAPEN_0"/>
+            <item stringID="Direction" value="UNUSED"/>
+            <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+            <item label="Constraint" stringID="Constraint" value="PROHIBITED"/>
+          </row>
+        </table>
+        <table stringID="PAR_PSEUDO_LOGIC">
+          <column label="Signal&#xA;Name" stringID="Signal_Name"/>
+          <column stringID="Type"/>
+          <column stringID="Site"/>
+        </table>
+      </section>
+      <section stringID="PAR_UNROUTES_REPORT">
+        <item dataType="int" stringID="PAR_UNROUTED_NETS" value="0"/>
+        <item dataType="int" stringID="PAR_TOTAL_SOURCELESS_NETS" value="0"/>
+        <item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="0"/>
+      </section>
+    </task>
+  </application>
+
+  <application stringID="Par" timeStamp="Tue Feb 21 22:16:58 2017">
+    <section stringID="User_Env">
+      <table stringID="User_EnvVar">
+        <column stringID="variable"/>
+        <column stringID="value"/>
+        <row stringID="row" value="0">
+          <item stringID="variable" value="LD_LIBRARY_PATH"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
+        </row>
+        <row stringID="row" value="1">
+          <item stringID="variable" value="XILINX_DSP"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE"/>
+        </row>
+        <row stringID="row" value="2">
+          <item stringID="variable" value="XILINX_PLANAHEAD"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/PlanAhead"/>
+        </row>
+        <row stringID="row" value="3">
+          <item stringID="variable" value="XILINX"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
+        </row>
+        <row stringID="row" value="4">
+          <item stringID="variable" value="XIL_MAP_LOCWARN"/>
+          <item stringID="value" value="1"/>
+        </row>
+        <row stringID="row" value="5">
+          <item stringID="variable" value="XILINX_EDK"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/EDK"/>
+        </row>
+        <row stringID="row" value="6">
+          <item stringID="variable" value="PATH"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/local/sbin:/usr/local/bin:/usr/bin:/usr/lib/jvm/default/bin:/usr/bin/site_perl:/usr/bin/vendor_perl:/usr/bin/core_perl"/>
+        </row>
+      </table>
+      <item stringID="User_EnvOs" value="OS Information">
+        <item stringID="User_EnvOsname" value="unknown"/>
+        <item stringID="User_EnvOsrelease" value="unknown"/>
+      </item>
+      <item stringID="User_EnvHost" value="yann-arch"/>
+      <table stringID="User_EnvCpu">
+        <column stringID="arch"/>
+        <column stringID="speed"/>
+        <row stringID="row" value="0">
+          <item stringID="arch" value="Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz"/>
+          <item stringID="speed" value="3100.122 MHz"/>
+        </row>
+      </table>
+    </section>
+    <task label="Device Utilization Summary" stringID="PAR_DEVICE_UTLIZATION">
+      <section stringID="PAR_SLICE_REPORTING">
+        <item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="25">
+          <item dataType="int" stringID="PAR_NUM_SLICE_FF" value="25"/>
+          <item dataType="int" stringID="PAR_NUM_SLICE_LATCH" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
+        </item>
+        <item AVAILABLE="5720" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="57">
+          <item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="1"/>
+          <item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="34"/>
+          <item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="22"/>
+          <item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_DPRAM_O5ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_DPRAM_O6ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_DPRAM_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SPRAM_O5ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SPRAM_O6ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SPRAM_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SRL_O5ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SRL_O6ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_SRL_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_LUT_RT_O5ANDO6" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
+          <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
+        </item>
+        <item AVAILABLE="1430" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="15">
+          <item AVAILABLE="355" dataType="int" stringID="PAR_NUM_SLICEL" value="6"/>
+          <item AVAILABLE="360" dataType="int" stringID="PAR_NUM_SLICEM" value="0"/>
+          <item AVAILABLE="715" dataType="int" stringID="PAR_NUM_SLICEX" value="9"/>
+        </item>
+        <item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="57">
+          <item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="32"/>
+          <item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="0"/>
+          <item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="25"/>
+        </item>
+      </section>
+      <section stringID="PAR_IOB_REPORTING">
+        <item AVAILABLE="102" dataType="int" stringID="PAR_AGG_BONDED_IO" value="2"/>
+        <item AVAILABLE="98" dataType="int" stringID="PAR_AGG_UNBONDED_IO" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_FF" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_LATCH" value="0"/>
+        <item AVAILABLE="49" dataType="int" stringID="PAR_NUM_IOBM" value="0"/>
+        <item AVAILABLE="51" dataType="int" stringID="PAR_NUM_BONDED_IOBM" value="0"/>
+        <item AVAILABLE="49" dataType="int" stringID="PAR_NUM_IOBS" value="0"/>
+        <item AVAILABLE="51" dataType="int" stringID="PAR_NUM_BONDED_IOBS" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IPAD" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_BONDED_IPAD" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_BONDED_OPAD" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_OPAD" value="0"/>
+      </section>
+      <section stringID="PAR_HARD_IP_REPORTING"/>
+      <section stringID="PAR_RAM_FIFO_DATA">
+        <item AVAILABLE="32" dataType="int" stringID="PAR_NUM_RAMB16BWER" value="0"/>
+        <item AVAILABLE="64" dataType="int" stringID="PAR_NUM_RAMB8BWER" value="0"/>
+      </section>
+      <section stringID="PAR_IP_DATA">
+        <item AVAILABLE="4" dataType="int" stringID="PAR_NUM_BSCAN" value="0"/>
+        <item AVAILABLE="128" dataType="int" stringID="PAR_NUM_BUFH" value="0"/>
+        <item AVAILABLE="8" dataType="int" stringID="PAR_NUM_BUFPLL" value="0"/>
+        <item AVAILABLE="4" dataType="int" stringID="PAR_NUM_BUFPLL_MCB" value="0"/>
+        <item AVAILABLE="16" dataType="int" stringID="PAR_NUM_DSP48A1" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_GTPA1_DUAL" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="PAR_NUM_ICAP" value="0"/>
+        <item AVAILABLE="2" dataType="int" stringID="PAR_NUM_MCB" value="0"/>
+        <item AVAILABLE="0" dataType="int" stringID="PAR_NUM_PCIE_A1" value="0"/>
+        <item AVAILABLE="2" dataType="int" stringID="PAR_NUM_PCILOGICSE" value="0"/>
+        <item AVAILABLE="2" dataType="int" stringID="PAR_NUM_PLL_ADV" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="PAR_NUM_PMV" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="PAR_NUM_STARTUP" value="0"/>
+        <item AVAILABLE="1" dataType="int" stringID="PAR_NUM_SUSPEND_SYNC" value="0"/>
+      </section>
+      <section stringID="PAR_BUFG_DATA">
+        <item dataType="int" stringID="PAR_NUM_BUFG" value="1"/>
+        <item dataType="int" stringID="PAR_NUM_BUFGMUX" value="0"/>
+        <item dataType="int" stringID="PAR_AVAILABLE" value="16"/>
+      </section>
+    </task>
+  </application>
+
+</document>
diff --git a/led_summary.html b/led_summary.html
index 5387a17..7839b75 100644
--- a/led_summary.html
+++ b/led_summary.html
@@ -2,7 +2,7 @@
 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
 <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>led Project Status</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>led Project Status (02/21/2017 - 22:10:44)</B></TD></TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
 <TD>FPGA-led-lights.xise</TD>
@@ -13,33 +13,33 @@
 <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
 <TD>led</TD>
 <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
-<TD>Synthesized</TD>
+<TD>Programming File Generated</TD>
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
-<TD>xc3s250e-4vq100</TD>
+<TD>xc6slx9-2tqg144</TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
 <TD>
-<font color="red"; face="Arial"><b>X </b></font>
-<A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/_xmsgs/*.xmsgs?&DataKey=Error'>1 Error (1 new)</A></TD>
+No Errors</TD>
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
-<TD ALIGN=LEFT>No Warnings</TD>
+<TD ALIGN=LEFT><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/_xmsgs/*.xmsgs?&DataKey=Warning'>98 Warnings (2 new)</A></TD>
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
 <TD>Balanced</TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
 <TD>
-&nbsp;</TD>
+<A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led.unroutes'>All Signals Completely Routed</A></TD>
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
 <TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
+<TD>
+<A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
@@ -48,17 +48,318 @@
 System Settings</A>
 </TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
-<TD>&nbsp;&nbsp;</TD>
+<TD>0 &nbsp;<A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
 </TR>
 </TABLE>
 
 
 
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
+<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
+<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
+<TD ALIGN=RIGHT>25</TD>
+<TD ALIGN=RIGHT>11,440</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
+<TD ALIGN=RIGHT>25</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
+<TD ALIGN=RIGHT>57</TD>
+<TD ALIGN=RIGHT>5,720</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
+<TD ALIGN=RIGHT>57</TD>
+<TD ALIGN=RIGHT>5,720</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
+<TD ALIGN=RIGHT>34</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
+<TD ALIGN=RIGHT>22</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1,440</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
+<TD ALIGN=RIGHT>15</TD>
+<TD ALIGN=RIGHT>1,430</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
+<TD ALIGN=RIGHT>24</TD>
+<TD ALIGN=RIGHT>2,860</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
+<TD ALIGN=RIGHT>57</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
+<TD ALIGN=RIGHT>32</TD>
+<TD ALIGN=RIGHT>57</TD>
+<TD ALIGN=RIGHT>56%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>57</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
+<TD ALIGN=RIGHT>25</TD>
+<TD ALIGN=RIGHT>57</TD>
+<TD ALIGN=RIGHT>43%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
+<TD ALIGN=RIGHT>7</TD>
+<TD ALIGN=RIGHT>11,440</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>102</TD>
+<TD ALIGN=RIGHT>1%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>100%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>32</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>64</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>32</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>32</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>16</TD>
+<TD ALIGN=RIGHT>6%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>200</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>200</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>200</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>128</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>8</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>4</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>16</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>2</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>1</TD>
+<TD ALIGN=RIGHT>0%</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
+<TD ALIGN=RIGHT>3.24</TD>
+<TD>&nbsp;</TD>
+<TD>&nbsp;</TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TR>
+</TABLE>
 
 
 
-
-
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
+<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
+<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
+<TD COLSPAN='2'><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
+<A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led.unroutes'>All Signals Completely Routed</A></TD>
+<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
+<TD COLSPAN='2'><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
+<TD>
+<A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
+<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
+<TD COLSPAN='2'>&nbsp;</TD>
+</TABLE>
 
 
 
@@ -66,19 +367,21 @@ System Settings</A>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
 <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sun Feb 19 23:15:32 2017</TD><TD ALIGN=LEFT><font color="red"; face="Arial"><b>X </b></font><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/_xmsgs/xst.xmsgs?&DataKey=Error'>1 Error (1 new)</A></TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Tue Feb 21 22:10:17 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue Feb 21 22:16:44 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>95 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>207 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Tue Feb 21 22:16:54 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/_xmsgs/map.xmsgs?&DataKey=Info'>8 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Tue Feb 21 22:16:59 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
 <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Tue Feb 21 22:17:03 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/led.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Tue Feb 21 22:17:08 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
 </TABLE>
 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Tue Feb 21 22:17:09 2017</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/yannherklotz/Github/FPGA-led-lights/webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Tue Feb 21 22:17:10 2017</TD></TR>
 </TABLE>
 
 
-<br><center><b>Date Generated:</b> 02/20/2017 - 16:00:35</center>
+<br><center><b>Date Generated:</b> 02/21/2017 - 23:44:54</center>
 </BODY></HTML>
 \ No newline at end of file
diff --git a/led_summary.xml b/led_summary.xml
new file mode 100644
index 0000000..d46d958
--- /dev/null
+++ b/led_summary.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<DesignSummary rev="37">
+<CmdHistory>
+</CmdHistory>
+</DesignSummary>
diff --git a/led_usage.xml b/led_usage.xml
new file mode 100644
index 0000000..83b1dce
--- /dev/null
+++ b/led_usage.xml
@@ -0,0 +1,612 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<DeviceUsageSummary rev="37">
+<DesignStatistics TimeStamp="Tue Feb 21 22:17:08 2017"><group name="NetStatistics">
+<item name="NumNets_Active" rev="37">
+<attrib name="value" value="66"/></item>
+<item name="NumNets_Vcc" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="37">
+<attrib name="value" value="2"/></item>
+<item name="NumNodesOfType_Active_BOUNCEIN" rev="37">
+<attrib name="value" value="7"/></item>
+<item name="NumNodesOfType_Active_BUFGOUT" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Active_CLKPIN" rev="37">
+<attrib name="value" value="8"/></item>
+<item name="NumNodesOfType_Active_CLKPINFEED" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Active_DOUBLE" rev="37">
+<attrib name="value" value="41"/></item>
+<item name="NumNodesOfType_Active_GENERIC" rev="37">
+<attrib name="value" value="2"/></item>
+<item name="NumNodesOfType_Active_GLOBAL" rev="37">
+<attrib name="value" value="10"/></item>
+<item name="NumNodesOfType_Active_INPUT" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="NumNodesOfType_Active_IOBIN2OUT" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Active_IOBOUTPUT" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Active_LUTINPUT" rev="37">
+<attrib name="value" value="197"/></item>
+<item name="NumNodesOfType_Active_OUTBOUND" rev="37">
+<attrib name="value" value="60"/></item>
+<item name="NumNodesOfType_Active_OUTPUT" rev="37">
+<attrib name="value" value="66"/></item>
+<item name="NumNodesOfType_Active_PADINPUT" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Active_PADOUTPUT" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="NumNodesOfType_Active_PINBOUNCE" rev="37">
+<attrib name="value" value="17"/></item>
+<item name="NumNodesOfType_Active_PINFEED" rev="37">
+<attrib name="value" value="207"/></item>
+<item name="NumNodesOfType_Active_QUAD" rev="37">
+<attrib name="value" value="7"/></item>
+<item name="NumNodesOfType_Active_SINGLE" rev="37">
+<attrib name="value" value="76"/></item>
+<item name="NumNodesOfType_Vcc_HVCCOUT" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="NumNodesOfType_Vcc_LUTINPUT" rev="37">
+<attrib name="value" value="23"/></item>
+<item name="NumNodesOfType_Vcc_PINFEED" rev="37">
+<attrib name="value" value="23"/></item>
+</group>
+<group name="SiteStatistics">
+<item name="BUFG-BUFGMUX" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="IOB-IOBM" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="IOB-IOBS" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="SLICEL-SLICEM" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="SLICEX-SLICEL" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="SLICEX-SLICEM" rev="37">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="MiscellaneousStatistics">
+<item name="AGG_BONDED_IO" rev="36">
+<attrib name="value" value="2"/></item>
+<item name="AGG_IO" rev="36">
+<attrib name="value" value="2"/></item>
+<item name="AGG_LOCED_IO" rev="36">
+<attrib name="value" value="2"/></item>
+<item name="AGG_SLICE" rev="36">
+<attrib name="value" value="15"/></item>
+<item name="NUM_BONDED_IOB" rev="36">
+<attrib name="value" value="2"/></item>
+<item name="NUM_BSFULL" rev="36">
+<attrib name="value" value="25"/></item>
+<item name="NUM_BSLUTONLY" rev="36">
+<attrib name="value" value="32"/></item>
+<item name="NUM_BSUSED" rev="36">
+<attrib name="value" value="57"/></item>
+<item name="NUM_BUFG" rev="36">
+<attrib name="value" value="1"/></item>
+<item name="NUM_LOCED_IOB" rev="36">
+<attrib name="value" value="2"/></item>
+<item name="NUM_LOGIC_O5ANDO6" rev="36">
+<attrib name="value" value="22"/></item>
+<item name="NUM_LOGIC_O5ONLY" rev="36">
+<attrib name="value" value="1"/></item>
+<item name="NUM_LOGIC_O6ONLY" rev="36">
+<attrib name="value" value="34"/></item>
+<item name="NUM_LUT_RT_O6" rev="36">
+<attrib name="value" value="1"/></item>
+<item name="NUM_SLICEL" rev="36">
+<attrib name="value" value="6"/></item>
+<item name="NUM_SLICEX" rev="36">
+<attrib name="value" value="9"/></item>
+<item name="NUM_SLICE_CARRY4" rev="36">
+<attrib name="value" value="6"/></item>
+<item name="NUM_SLICE_CONTROLSET" rev="36">
+<attrib name="value" value="1"/></item>
+<item name="NUM_SLICE_CYINIT" rev="36">
+<attrib name="value" value="81"/></item>
+<item name="NUM_SLICE_FF" rev="36">
+<attrib name="value" value="25"/></item>
+<item name="NUM_SLICE_UNUSEDCTRL" rev="36">
+<attrib name="value" value="7"/></item>
+<item name="NUM_UNUSABLE_FF_BELS" rev="36">
+<attrib name="value" value="7"/></item>
+</group>
+</DesignStatistics>
+<DeviceUsage TimeStamp="Tue Feb 21 22:17:08 2017"><group name="SiteSummary">
+<item name="BUFG" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
+<item name="BUFG_BUFG" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
+<item name="CARRY4" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
+<item name="HARD1" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
+<item name="IOB" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
+<item name="IOB_IMUX" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
+<item name="IOB_INBUF" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
+<item name="IOB_OUTBUF" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
+<item name="LUT5" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="23"/></item>
+<item name="LUT6" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="57"/></item>
+<item name="PAD" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
+<item name="REG_SR" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="25"/></item>
+<item name="SLICEL" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
+<item name="SLICEX" rev="37">
+<attrib name="total" value="1000000"/><attrib name="used" value="9"/></item>
+</group>
+</DeviceUsage>
+<ReportConfigData TimeStamp="Tue Feb 21 22:17:08 2017"><group name="SLICEL_CYMUXF">
+<item name="0" rev="9">
+<attrib name="0" value="8"/><attrib name="0_INV" value="0"/></item>
+<item name="1" rev="9">
+<attrib name="1_INV" value="0"/><attrib name="1" value="8"/></item>
+</group>
+<group name="SLICEL_CYMUXG">
+<item name="0" rev="9">
+<attrib name="0" value="7"/><attrib name="0_INV" value="0"/></item>
+</group>
+<group name="REG_SR">
+<item name="CK" rev="37">
+<attrib name="CK" value="25"/><attrib name="CK_INV" value="0"/></item>
+<item name="LATCH_OR_FF" rev="37">
+<attrib name="FF" value="25"/></item>
+<item name="SRINIT" rev="37">
+<attrib name="SRINIT0" value="18"/><attrib name="SRINIT1" value="7"/></item>
+<item name="SYNC_ATTR" rev="37">
+<attrib name="ASYNC" value="25"/></item>
+</group>
+<group name="IBUF_PAD">
+<item name="IOATTRBOX" rev="9">
+<attrib name="LVTTL" value="1"/></item>
+</group>
+<group name="SLICEL">
+<item name="BX" rev="9">
+<attrib name="BX_INV" value="0"/><attrib name="BX" value="1"/></item>
+<item name="BY" rev="9">
+<attrib name="BY" value="0"/><attrib name="BY_INV" value="1"/></item>
+<item name="CE" rev="9">
+<attrib name="CE" value="1"/><attrib name="CE_INV" value="0"/></item>
+<item name="CIN" rev="9">
+<attrib name="CIN_INV" value="0"/><attrib name="CIN" value="7"/></item>
+<item name="CLK" rev="9">
+<attrib name="CLK" value="9"/><attrib name="CLK_INV" value="0"/></item>
+<item name="SR" rev="9">
+<attrib name="SR" value="8"/><attrib name="SR_INV" value="0"/></item>
+</group>
+<group name="IOB_OUTBUF">
+<item name="DRIVEATTRBOX" rev="37">
+<attrib name="8" value="1"/></item>
+<item name="SLEW" rev="37">
+<attrib name="SLOW" value="1"/></item>
+<item name="SUSPEND" rev="37">
+<attrib name="3STATE" value="1"/></item>
+</group>
+<group name="SLICEX">
+<item name="CLK" rev="37">
+<attrib name="CLK" value="8"/><attrib name="CLK_INV" value="0"/></item>
+</group>
+<group name="SLICEL_FFX">
+<item name="CK" rev="9">
+<attrib name="CK" value="8"/><attrib name="CK_INV" value="0"/></item>
+<item name="D" rev="9">
+<attrib name="D" value="8"/><attrib name="D_INV" value="0"/></item>
+<item name="FFX_INIT_ATTR" rev="9">
+<attrib name="INIT0" value="3"/><attrib name="INIT1" value="5"/></item>
+<item name="FFX_SR_ATTR" rev="9">
+<attrib name="SRLOW" value="3"/><attrib name="SRHIGH" value="5"/></item>
+<item name="LATCH_OR_FF" rev="9">
+<attrib name="FF" value="8"/></item>
+<item name="SR" rev="9">
+<attrib name="SR" value="8"/><attrib name="SR_INV" value="0"/></item>
+<item name="SYNC_ATTR" rev="9">
+<attrib name="SYNC" value="8"/></item>
+</group>
+<group name="SLICEL_XORF">
+<item name="1" rev="9">
+<attrib name="1_INV" value="0"/><attrib name="1" value="8"/></item>
+</group>
+<group name="SLICEL_FFY">
+<item name="CE" rev="9">
+<attrib name="CE" value="1"/><attrib name="CE_INV" value="0"/></item>
+<item name="CK" rev="9">
+<attrib name="CK" value="9"/><attrib name="CK_INV" value="0"/></item>
+<item name="D" rev="9">
+<attrib name="D" value="8"/><attrib name="D_INV" value="1"/></item>
+<item name="FFY_INIT_ATTR" rev="9">
+<attrib name="INIT0" value="5"/><attrib name="INIT1" value="4"/></item>
+<item name="FFY_SR_ATTR" rev="9">
+<attrib name="SRLOW" value="5"/><attrib name="SRHIGH" value="4"/></item>
+<item name="LATCH_OR_FF" rev="9">
+<attrib name="FF" value="9"/></item>
+<item name="SR" rev="9">
+<attrib name="SR" value="8"/><attrib name="SR_INV" value="0"/></item>
+<item name="SYNC_ATTR" rev="9">
+<attrib name="ASYNC" value="1"/><attrib name="SYNC" value="8"/></item>
+</group>
+<group name="BUFGMUX_GCLKMUX">
+<item name="DISABLE_ATTR" rev="9">
+<attrib name="LOW" value="1"/></item>
+<item name="S" rev="9">
+<attrib name="S_INV" value="1"/><attrib name="S" value="0"/></item>
+</group>
+<group name="IOB_PAD">
+<item name="DRIVEATTRBOX" rev="9">
+<attrib name="8" value="1"/></item>
+<item name="IOATTRBOX" rev="9">
+<attrib name="LVTTL" value="1"/></item>
+<item name="SLEW" rev="9">
+<attrib name="SLOW" value="1"/></item>
+</group>
+<group name="IOB">
+<item name="O1" rev="9">
+<attrib name="O1_INV" value="0"/><attrib name="O1" value="1"/></item>
+</group>
+<group name="BUFGMUX">
+<item name="S" rev="9">
+<attrib name="S_INV" value="1"/><attrib name="S" value="0"/></item>
+</group>
+</ReportConfigData>
+<ReportPinData TimeStamp="Tue Feb 21 22:17:08 2017"><group name="SLICEL_CYMUXF">
+<item name="0" rev="9">
+<attrib name="value" value="8"/></item>
+<item name="1" rev="9">
+<attrib name="value" value="8"/></item>
+<item name="OUT" rev="9">
+<attrib name="value" value="8"/></item>
+<item name="S0" rev="9">
+<attrib name="value" value="8"/></item>
+</group>
+<group name="SLICEL_CYMUXG">
+<item name="0" rev="9">
+<attrib name="value" value="7"/></item>
+<item name="1" rev="9">
+<attrib name="value" value="7"/></item>
+<item name="OUT" rev="9">
+<attrib name="value" value="7"/></item>
+<item name="S0" rev="9">
+<attrib name="value" value="7"/></item>
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+<group name="REG_SR">
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+<attrib name="value" value="25"/></item>
+<item name="D" rev="37">
+<attrib name="value" value="25"/></item>
+<item name="Q" rev="37">
+<attrib name="value" value="25"/></item>
+</group>
+<group name="IBUF_PAD">
+<item name="PAD" rev="9">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="IBUF_INBUF">
+<item name="IN" rev="9">
+<attrib name="value" value="1"/></item>
+<item name="OUT" rev="9">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="BUFGMUX_GCLK_BUFFER">
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+<item name="OUT" rev="9">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="SLICEL">
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+<attrib name="value" value="6"/></item>
+<item name="A6" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="AMUX" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="B5" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="B6" rev="37">
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+<item name="C6" rev="37">
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+<item name="D6" rev="37">
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+<item name="DMUX" rev="37">
+<attrib name="value" value="6"/></item>
+</group>
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+<item name="D6" rev="37">
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+<item name="DQ" rev="37">
+<attrib name="value" value="6"/></item>
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+<group name="BUFG_BUFG">
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+<attrib name="value" value="1"/></item>
+<item name="O" rev="37">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="IBUF">
+<item name="I" rev="9">
+<attrib name="value" value="1"/></item>
+<item name="PAD" rev="9">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="PAD">
+<item name="PAD" rev="37">
+<attrib name="value" value="2"/></item>
+</group>
+<group name="IOB_INBUF">
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+<attrib name="value" value="1"/></item>
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+<item name="1" rev="9">
+<attrib name="value" value="7"/></item>
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+<item name="D" rev="9">
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+<item name="Q" rev="9">
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+<item name="SR" rev="9">
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+</group>
+<group name="SLICEL_FFY">
+<item name="CE" rev="9">
+<attrib name="value" value="1"/></item>
+<item name="CK" rev="9">
+<attrib name="value" value="9"/></item>
+<item name="D" rev="9">
+<attrib name="value" value="9"/></item>
+<item name="Q" rev="9">
+<attrib name="value" value="9"/></item>
+<item name="SR" rev="9">
+<attrib name="value" value="8"/></item>
+</group>
+<group name="SLICEL_XORG">
+<item name="0" rev="9">
+<attrib name="value" value="8"/></item>
+<item name="1" rev="9">
+<attrib name="value" value="8"/></item>
+<item name="O" rev="9">
+<attrib name="value" value="8"/></item>
+</group>
+<group name="BUFGMUX_GCLKMUX">
+<item name="I0" rev="9">
+<attrib name="value" value="1"/></item>
+<item name="OUT" rev="9">
+<attrib name="value" value="1"/></item>
+<item name="S" rev="9">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="CARRY4">
+<item name="CIN" rev="37">
+<attrib name="value" value="5"/></item>
+<item name="CO3" rev="37">
+<attrib name="value" value="5"/></item>
+<item name="CYINIT" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="DI0" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="DI1" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="DI2" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="DI3" rev="37">
+<attrib name="value" value="5"/></item>
+<item name="O0" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="O1" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="O2" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="O3" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="S0" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="S1" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="S2" rev="37">
+<attrib name="value" value="6"/></item>
+<item name="S3" rev="37">
+<attrib name="value" value="6"/></item>
+</group>
+<group name="LUT5">
+<item name="O5" rev="37">
+<attrib name="value" value="23"/></item>
+</group>
+<group name="LUT6">
+<item name="A1" rev="37">
+<attrib name="value" value="8"/></item>
+<item name="A2" rev="37">
+<attrib name="value" value="33"/></item>
+<item name="A3" rev="37">
+<attrib name="value" value="33"/></item>
+<item name="A4" rev="37">
+<attrib name="value" value="33"/></item>
+<item name="A5" rev="37">
+<attrib name="value" value="56"/></item>
+<item name="A6" rev="37">
+<attrib name="value" value="57"/></item>
+<item name="O6" rev="37">
+<attrib name="value" value="57"/></item>
+</group>
+<group name="IOB_PAD">
+<item name="PAD" rev="9">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="IOB_IMUX">
+<item name="I" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="OUT" rev="37">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="IOB">
+<item name="I" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="O" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="PAD" rev="37">
+<attrib name="value" value="2"/></item>
+</group>
+<group name="SLICEL_C1VDD">
+<item name="1" rev="9">
+<attrib name="value" value="7"/></item>
+</group>
+<group name="BUFGMUX">
+<item name="I0" rev="9">
+<attrib name="value" value="1"/></item>
+<item name="O" rev="9">
+<attrib name="value" value="1"/></item>
+<item name="S" rev="9">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="HARD1">
+<item name="1" rev="37">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="BUFG">
+<item name="I0" rev="37">
+<attrib name="value" value="1"/></item>
+<item name="O" rev="37">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="SLICEL_F">
+<item name="A1" rev="9">
+<attrib name="value" value="12"/></item>
+<item name="A2" rev="9">
+<attrib name="value" value="4"/></item>
+<item name="A3" rev="9">
+<attrib name="value" value="4"/></item>
+<item name="A4" rev="9">
+<attrib name="value" value="4"/></item>
+<item name="D" rev="9">
+<attrib name="value" value="12"/></item>
+</group>
+<group name="SLICEL_G">
+<item name="A1" rev="9">
+<attrib name="value" value="9"/></item>
+<item name="A2" rev="9">
+<attrib name="value" value="1"/></item>
+<item name="A3" rev="9">
+<attrib name="value" value="1"/></item>
+<item name="A4" rev="9">
+<attrib name="value" value="1"/></item>
+<item name="D" rev="9">
+<attrib name="value" value="9"/></item>
+</group>
+<group name="SLICEL_GNDF">
+<item name="0" rev="9">
+<attrib name="value" value="1"/></item>
+</group>
+<group name="SLICEL_GNDG">
+<item name="0" rev="7">
+<attrib name="value" value="7"/></item>
+</group>
+</ReportPinData>
+<CmdHistory>
+</CmdHistory>
+</DeviceUsageSummary>
diff --git a/led_xst.xrpt b/led_xst.xrpt
index 799a43f..dedbc1c 100644
--- a/led_xst.xrpt
+++ b/led_xst.xrpt
@@ -5,7 +5,7 @@
     The structure and the elements are likely to change over the next few releases.
     This means code written to parse this file will need to be revisited each subsequent release.-->
 
-  <application stringID="Xst" timeStamp="Sun Feb 19 23:15:31 2017">
+  <application stringID="Xst" timeStamp="Tue Feb 21 22:10:13 2017">
     <section stringID="User_Env">
       <table stringID="User_EnvVar">
         <column stringID="variable"/>
@@ -27,10 +27,14 @@
           <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
         </row>
         <row stringID="row" value="4">
+          <item stringID="variable" value="XIL_MAP_LOCWARN"/>
+          <item stringID="value" value="1"/>
+        </row>
+        <row stringID="row" value="5">
           <item stringID="variable" value="XILINX_EDK"/>
           <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/EDK"/>
         </row>
-        <row stringID="row" value="5">
+        <row stringID="row" value="6">
           <item stringID="variable" value="PATH"/>
           <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/local/sbin:/usr/local/bin:/usr/bin:/usr/lib/jvm/default/bin:/usr/bin/site_perl:/usr/bin/vendor_perl:/usr/bin/core_perl"/>
         </row>
@@ -51,63 +55,124 @@
     </section>
     <section stringID="XST_OPTION_SUMMARY">
       <item DEFAULT="" label="-ifn" stringID="XST_IFN" value="led.prj"/>
-      <item DEFAULT="MIXED" label="-ifmt" stringID="XST_IFMT" value="mixed"/>
       <item DEFAULT="" label="-ofn" stringID="XST_OFN" value="led"/>
       <item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
-      <item DEFAULT="" label="-p" stringID="XST_P" value="xc3s250e-4-vq100"/>
+      <item DEFAULT="" label="-p" stringID="XST_P" value="xc6slx9-2-tqg144"/>
       <item DEFAULT="" label="-top" stringID="XST_TOP" value="led"/>
-      <item DEFAULT="SPEED" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
+      <item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
       <item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
-      <item DEFAULT="NO" label="-iuc" stringID="XST_IUC" value="NO"/>
-      <item DEFAULT="NO" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
-      <item DEFAULT="as_optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
-      <item DEFAULT="NO" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
-      <item DEFAULT="ALLCLOCKNETS" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
-      <item DEFAULT="YES" label="-read_cores" stringID="XST_READCORES" value="YES"/>
-      <item DEFAULT="NO" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
-      <item DEFAULT="NO" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
+      <item DEFAULT="No" label="-power" stringID="XST_POWER" value="NO"/>
+      <item DEFAULT="No" label="-iuc" stringID="XST_IUC" value="NO"/>
+      <item DEFAULT="No" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
+      <item DEFAULT="As_Optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
+      <item DEFAULT="No" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
+      <item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
+      <item DEFAULT="Yes" label="-read_cores" stringID="XST_READCORES" value="YES"/>
+      <item DEFAULT="No" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
+      <item DEFAULT="No" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
       <item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
       <item DEFAULT="&lt;>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="&lt;>"/>
-      <item DEFAULT="MAINTAIN" stringID="XST_CASE" value="Maintain"/>
-      <item DEFAULT="100%" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
-      <item DEFAULT="100%" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
-      <item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/>
-      <item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
-      <item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
-      <item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
+      <item DEFAULT="Maintain" stringID="XST_CASE" value="Maintain"/>
+      <item DEFAULT="100" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
+      <item DEFAULT="100" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
+      <item DEFAULT="100" label="-dsp_utilization_ratio" stringID="XST_DSPUTILIZATIONRATIO" value="100"/>
+      <item DEFAULT="Auto" stringID="XST_LC" value="Auto"/>
+      <item DEFAULT="Auto" label="-reduce_control_sets" stringID="XST_REDUCECONTROLSETS" value="Auto"/>
+      <item DEFAULT="Yes" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
+      <item DEFAULT="Auto" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
+      <item DEFAULT="No" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
       <item DEFAULT="LUT" label="-fsm_style" stringID="XST_FSMSTYLE" value="LUT"/>
-      <item DEFAULT="YES" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
-      <item DEFAULT="AUTO" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
-      <item DEFAULT="YES" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
-      <item DEFAULT="AUTO" stringID="XST_MUXSTYLE" value="Auto"/>
-      <item DEFAULT="NO" stringID="XST_DECODEREXTRACT" value="YES"/>
-      <item DEFAULT="NO" stringID="XST_PRIORITYEXTRACT" value="Yes"/>
-      <item DEFAULT="YES" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
-      <item DEFAULT="YES" stringID="XST_SHIFTEXTRACT" value="YES"/>
-      <item DEFAULT="YES" stringID="XST_XORCOLLAPSE" value="YES"/>
-      <item DEFAULT="AUTO" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
-      <item DEFAULT="NO" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
-      <item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/>
-      <item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
-      <item DEFAULT="NO" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
-      <item DEFAULT="AUTO" label="-mult_style" stringID="XST_MULTSTYLE" value="Auto"/>
-      <item DEFAULT="YES" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
-      <item DEFAULT="500" label="-max_fanout" stringID="XST_MAXFANOUT" value="500"/>
-      <item DEFAULT="24" label="-bufg" stringID="XST_BUFG" value="24"/>
-      <item DEFAULT="YES" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
-      <item DEFAULT="NO" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
-      <item DEFAULT="YES" stringID="XST_SLICEPACKING" value="YES"/>
-      <item DEFAULT="NO" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
-      <item DEFAULT="YES" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Yes"/>
-      <item DEFAULT="YES" label="-use_sync_set" stringID="XST_USESYNCSET" value="Yes"/>
-      <item DEFAULT="YES" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Yes"/>
-      <item DEFAULT="AUTO" label="-iob" stringID="XST_IOB" value="Auto"/>
-      <item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
-      <item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
+      <item DEFAULT="Yes" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
+      <item DEFAULT="Auto" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
+      <item DEFAULT="Yes" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
+      <item DEFAULT="Yes" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
+      <item DEFAULT="Auto" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
+      <item DEFAULT="No" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
+      <item DEFAULT="Yes" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
+      <item DEFAULT="No" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
+      <item DEFAULT="2" stringID="XST_SHREGMINSIZE" value="2"/>
+      <item DEFAULT="Auto" label="-use_dsp48" stringID="XST_USEDSP48" value="Auto"/>
+      <item DEFAULT="Yes" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
+      <item DEFAULT="100000" label="-max_fanout" stringID="XST_MAXFANOUT" value="100000"/>
+      <item DEFAULT="16" label="-bufg" stringID="XST_BUFG" value="16"/>
+      <item DEFAULT="Yes" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
+      <item DEFAULT="No" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
+      <item DEFAULT="No" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
+      <item DEFAULT="Auto" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Auto"/>
+      <item DEFAULT="Auto" label="-use_sync_set" stringID="XST_USESYNCSET" value="Auto"/>
+      <item DEFAULT="Auto" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Auto"/>
+      <item DEFAULT="Auto" label="-iob" stringID="XST_IOB" value="Auto"/>
+      <item DEFAULT="Yes" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
+      <item DEFAULT="0" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
+    </section>
+    <section stringID="XST_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="1"></item>
+      <item dataType="int" stringID="XST_REGISTERS" value="2">
+        <item dataType="int" stringID="XST_1BIT_REGISTER" value="1"/>
+      </item>
+    </section>
+    <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_COUNTERS" value="1"></item>
+      <item dataType="int" stringID="XST_REGISTERS" value="1">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="1"/>
+      </item>
+    </section>
+    <section stringID="XST_FINAL_REGISTER_REPORT">
+      <item dataType="int" stringID="XST_REGISTERS" value="25">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="25"/>
+      </item>
+    </section>
+    <section stringID="XST_PARTITION_REPORT">
+      <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+        <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+      </section>
+    </section>
+    <section stringID="XST_DESIGN_SUMMARY">
+      <section stringID="XST_">
+        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="led.ngc"/>
+      </section>
+      <section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
+        <item dataType="int" stringID="XST_BELS" value="106">
+          <item dataType="int" stringID="XST_GND" value="1"/>
+          <item dataType="int" stringID="XST_INV" value="23"/>
+          <item dataType="int" stringID="XST_LUT1" value="1"/>
+          <item dataType="int" stringID="XST_LUT5" value="25"/>
+          <item dataType="int" stringID="XST_LUT6" value="8"/>
+          <item dataType="int" stringID="XST_MUXCY" value="23"/>
+          <item dataType="int" stringID="XST_VCC" value="1"/>
+          <item dataType="int" stringID="XST_XORCY" value="24"/>
+        </item>
+        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="25">
+          <item dataType="int" stringID="XST_FD" value="25"/>
+        </item>
+        <item dataType="int" stringID="XST_CLOCK_BUFFERS" value="1">
+          <item dataType="int" stringID="XST_BUFGP" value="1"/>
+        </item>
+        <item dataType="int" stringID="XST_IO_BUFFERS" value="1">
+          <item dataType="int" stringID="XST_OBUF" value="1"/>
+        </item>
+      </section>
+    </section>
+    <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
+      <item stringID="XST_SELECTED_DEVICE" value="6slx9tqg144-2"/>
+      <item AVAILABLE="11440" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="25"/>
+      <item AVAILABLE="5720" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="57"/>
+      <item AVAILABLE="5720" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="57"/>
+      <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="57"/>
+      <item AVAILABLE="57" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="32"/>
+      <item AVAILABLE="57" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="0"/>
+      <item AVAILABLE="57" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="25"/>
+      <item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="1"/>
+      <item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="2"/>
+      <item AVAILABLE="102" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="2"/>
+      <item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="1"/>
+    </section>
+    <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
+      <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
     </section>
     <section stringID="XST_ERRORS_STATISTICS">
-      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="1"/>
-      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="3"/>
       <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
     </section>
   </application>
diff --git a/pa.fromHdl.tcl b/pa.fromHdl.tcl
new file mode 100644
index 0000000..3ee492f
--- /dev/null
+++ b/pa.fromHdl.tcl
@@ -0,0 +1,13 @@
+
+# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator
+
+create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2" -part xc3s250evq100-4
+set_param project.pinAheadLayout yes
+set srcset [get_property srcset [current_run -impl]]
+set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+set hdlfile [add_files [list {led.v}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set_property top led $srcset
+add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+open_rtl_design -part xc3s250evq100-4
diff --git a/pa.fromNcd.tcl b/pa.fromNcd.tcl
new file mode 100644
index 0000000..f862f3a
--- /dev/null
+++ b/pa.fromNcd.tcl
@@ -0,0 +1,15 @@
+
+# PlanAhead Launch Script for Post PAR Floorplanning, created by Project Navigator
+
+create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4" -part xc6slx9tqg144-2
+set srcset [get_property srcset [current_run -impl]]
+set_property design_mode GateLvl $srcset
+set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ]
+add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} }
+set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+link_design
+read_xdl -file "/home/yannherklotz/Github/FPGA-led-lights/led.ncd"
+if {[catch {read_twx -name results_1 -file "/home/yannherklotz/Github/FPGA-led-lights/led.twx"} eInfo]} {
+   puts "WARNING: there was a problem importing \"/home/yannherklotz/Github/FPGA-led-lights/led.twx\": $eInfo"
+}
diff --git a/pa.fromNetlist.tcl b/pa.fromNetlist.tcl
new file mode 100644
index 0000000..1d59b15
--- /dev/null
+++ b/pa.fromNetlist.tcl
@@ -0,0 +1,11 @@
+
+# PlanAhead Launch Script for Post-Synthesis pin planning, created by Project Navigator
+
+create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_3" -part xc6slx9tqg144-2
+set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ]
+add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} }
+set_param project.pinAheadLayout  yes
+set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+link_design
diff --git a/par_usage_statistics.html b/par_usage_statistics.html
new file mode 100644
index 0000000..8378d6c
--- /dev/null
+++ b/par_usage_statistics.html
@@ -0,0 +1,32 @@
+<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="ParStatistics">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>64</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>212</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>212</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>211</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>2.9 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>3.0 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>3.1 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>3.3 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>3.4 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>3.4 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>3.4 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>3.4 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>3.4 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>3.4 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>13.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>1.3</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.2</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>0.5</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0237</xtag-par-property-value></TD></TR>
+</xtag-section>
+</TABLE>
diff --git a/planAhead.ngc2edif.log b/planAhead.ngc2edif.log
new file mode 100644
index 0000000..8f1603c
--- /dev/null
+++ b/planAhead.ngc2edif.log
@@ -0,0 +1,33 @@
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design led.ngc ...
+WARNING:NetListWriters:298 - No output is written to led.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file led.edif ...
+ngc2edif: Total memory usage is 103520 kilobytes
+
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design led.ngc ...
+WARNING:NetListWriters:298 - No output is written to led.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file led.edif ...
+ngc2edif: Total memory usage is 103532 kilobytes
+
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design led.ngc ...
+WARNING:NetListWriters:298 - No output is written to led.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file led.edif ...
+ngc2edif: Total memory usage is 103540 kilobytes
+
diff --git a/planAhead_pid24048.debug b/planAhead_pid24048.debug
new file mode 100644
index 0000000..ad75ce3
--- /dev/null
+++ b/planAhead_pid24048.debug
@@ -0,0 +1,90 @@
+#-------------------------------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Current time: 2/21/17 9:46:53 PM
+# Process ID: 24048
+# Platform: Unix
+#
+# This file is an indication that an internal application error occurred.
+# This information is useful for debugging. Please open a case with Xilinx
+# Technical Support with this file and a testcase attached.
+#-------------------------------------------------------------------------------
+2/21/17 9:46:53 PM
+ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+
+	at ui.h.e.CF(SourceFile:217)
+	at ui.h.I.CF(SourceFile:702)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:368)
+	at ui.frmwork.HTclEventBroker.bb(SourceFile:354)
+	at ui.project.a.een(SourceFile:759)
+	at ui.project.a.cleanup(SourceFile:608)
+	at ui.project.r.cleanup(SourceFile:631)
+	at ui.PlanAhead.aJj(SourceFile:335)
+	at ui.PlanAhead.a(SourceFile:1192)
+	at ui.frmwork.a.i.c(SourceFile:35)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:233)
+	at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325)
+	at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method)
+	at ui.e.gY(SourceFile:195)
+	at ui.bl.run(SourceFile:882)
+	at ui.cd.run(SourceFile:1821)
+	at ui.views.F.aw.a(SourceFile:341)
+	at ui.cd.b(SourceFile:1809)
+	at ui.cd.a(SourceFile:1784)
+	at ui.PlanAhead.a(SourceFile:778)
+	at ui.aL.c(SourceFile:885)
+	at ui.aL.aHs(SourceFile:824)
+	at ui.bk.windowClosing(SourceFile:503)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.Window.processWindowEvent(Window.java:2051)
+	at javax.swing.JFrame.processWindowEvent(JFrame.java:296)
+	at java.awt.Window.processEvent(Window.java:2009)
+	at ui.aL.processEvent(SourceFile:1214)
+	at java.awt.Component.dispatchEventImpl(Component.java:4861)
+	at java.awt.Container.dispatchEventImpl(Container.java:2287)
+	at java.awt.Window.dispatchEventImpl(Window.java:2719)
+	at java.awt.Component.dispatchEvent(Component.java:4687)
+	at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729)
+	at java.awt.EventQueue.access$200(EventQueue.java:103)
+	at java.awt.EventQueue$3.run(EventQueue.java:688)
+	at java.awt.EventQueue$3.run(EventQueue.java:686)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87)
+	at java.awt.EventQueue$4.run(EventQueue.java:702)
+	at java.awt.EventQueue$4.run(EventQueue.java:700)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.awt.EventQueue.dispatchEvent(EventQueue.java:699)
+	at ui.frmwork.a.e.dispatchEvent(SourceFile:73)
+	at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242)
+	at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161)
+	at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138)
+	at java.awt.EventDispatchThread.run(EventDispatchThread.java:91)
+
diff --git a/planAhead_pid24218.debug b/planAhead_pid24218.debug
new file mode 100644
index 0000000..b1ca267
--- /dev/null
+++ b/planAhead_pid24218.debug
@@ -0,0 +1,91 @@
+#-------------------------------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Current time: 2/21/17 9:53:14 PM
+# Process ID: 24218
+# Platform: Unix
+#
+# This file is an indication that an internal application error occurred.
+# This information is useful for debugging. Please open a case with Xilinx
+# Technical Support with this file and a testcase attached.
+#-------------------------------------------------------------------------------
+2/21/17 9:53:14 PM
+ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+
+	at ui.h.e.CF(SourceFile:217)
+	at ui.h.I.CF(SourceFile:702)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:368)
+	at ui.frmwork.HTclEventBroker.bb(SourceFile:354)
+	at ui.project.a.een(SourceFile:759)
+	at ui.project.a.cleanup(SourceFile:608)
+	at ui.project.r.cleanup(SourceFile:631)
+	at ui.PlanAhead.aJj(SourceFile:335)
+	at ui.PlanAhead.a(SourceFile:1192)
+	at ui.frmwork.a.i.c(SourceFile:35)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:233)
+	at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325)
+	at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method)
+	at ui.e.gY(SourceFile:195)
+	at ui.bl.run(SourceFile:882)
+	at ui.cd.run(SourceFile:1821)
+	at ui.views.F.aw.a(SourceFile:341)
+	at ui.cd.b(SourceFile:1809)
+	at ui.cd.a(SourceFile:1784)
+	at ui.PlanAhead.a(SourceFile:778)
+	at ui.aL.c(SourceFile:885)
+	at ui.aL.aHs(SourceFile:824)
+	at ui.bk.windowClosing(SourceFile:503)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.Window.processWindowEvent(Window.java:2051)
+	at javax.swing.JFrame.processWindowEvent(JFrame.java:296)
+	at java.awt.Window.processEvent(Window.java:2009)
+	at ui.aL.processEvent(SourceFile:1214)
+	at java.awt.Component.dispatchEventImpl(Component.java:4861)
+	at java.awt.Container.dispatchEventImpl(Container.java:2287)
+	at java.awt.Window.dispatchEventImpl(Window.java:2719)
+	at java.awt.Component.dispatchEvent(Component.java:4687)
+	at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729)
+	at java.awt.EventQueue.access$200(EventQueue.java:103)
+	at java.awt.EventQueue$3.run(EventQueue.java:688)
+	at java.awt.EventQueue$3.run(EventQueue.java:686)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87)
+	at java.awt.EventQueue$4.run(EventQueue.java:702)
+	at java.awt.EventQueue$4.run(EventQueue.java:700)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.awt.EventQueue.dispatchEvent(EventQueue.java:699)
+	at ui.frmwork.a.e.dispatchEvent(SourceFile:73)
+	at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242)
+	at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161)
+	at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138)
+	at java.awt.EventDispatchThread.run(EventDispatchThread.java:91)
+
diff --git a/planAhead_pid7603.debug b/planAhead_pid7603.debug
new file mode 100644
index 0000000..2e8492f
--- /dev/null
+++ b/planAhead_pid7603.debug
@@ -0,0 +1,90 @@
+#-------------------------------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Current time: 2/21/17 8:21:03 PM
+# Process ID: 7603
+# Platform: Unix
+#
+# This file is an indication that an internal application error occurred.
+# This information is useful for debugging. Please open a case with Xilinx
+# Technical Support with this file and a testcase attached.
+#-------------------------------------------------------------------------------
+2/21/17 8:21:03 PM
+ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+
+	at ui.h.e.CF(SourceFile:217)
+	at ui.h.I.CF(SourceFile:702)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:368)
+	at ui.frmwork.HTclEventBroker.bb(SourceFile:354)
+	at ui.project.a.een(SourceFile:759)
+	at ui.project.a.cleanup(SourceFile:608)
+	at ui.project.r.cleanup(SourceFile:631)
+	at ui.PlanAhead.aJj(SourceFile:335)
+	at ui.PlanAhead.a(SourceFile:1192)
+	at ui.frmwork.a.i.c(SourceFile:35)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:233)
+	at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325)
+	at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method)
+	at ui.e.gY(SourceFile:195)
+	at ui.bl.run(SourceFile:882)
+	at ui.cd.run(SourceFile:1821)
+	at ui.views.F.aw.a(SourceFile:341)
+	at ui.cd.b(SourceFile:1809)
+	at ui.cd.a(SourceFile:1784)
+	at ui.PlanAhead.a(SourceFile:778)
+	at ui.aL.c(SourceFile:885)
+	at ui.aL.aHs(SourceFile:824)
+	at ui.bk.windowClosing(SourceFile:503)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.Window.processWindowEvent(Window.java:2051)
+	at javax.swing.JFrame.processWindowEvent(JFrame.java:296)
+	at java.awt.Window.processEvent(Window.java:2009)
+	at ui.aL.processEvent(SourceFile:1214)
+	at java.awt.Component.dispatchEventImpl(Component.java:4861)
+	at java.awt.Container.dispatchEventImpl(Container.java:2287)
+	at java.awt.Window.dispatchEventImpl(Window.java:2719)
+	at java.awt.Component.dispatchEvent(Component.java:4687)
+	at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729)
+	at java.awt.EventQueue.access$200(EventQueue.java:103)
+	at java.awt.EventQueue$3.run(EventQueue.java:688)
+	at java.awt.EventQueue$3.run(EventQueue.java:686)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87)
+	at java.awt.EventQueue$4.run(EventQueue.java:702)
+	at java.awt.EventQueue$4.run(EventQueue.java:700)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.awt.EventQueue.dispatchEvent(EventQueue.java:699)
+	at ui.frmwork.a.e.dispatchEvent(SourceFile:73)
+	at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242)
+	at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161)
+	at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138)
+	at java.awt.EventDispatchThread.run(EventDispatchThread.java:91)
+
diff --git a/planAhead_pid7744.debug b/planAhead_pid7744.debug
new file mode 100644
index 0000000..6b26846
--- /dev/null
+++ b/planAhead_pid7744.debug
@@ -0,0 +1,90 @@
+#-------------------------------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Current time: 2/21/17 8:24:50 PM
+# Process ID: 7744
+# Platform: Unix
+#
+# This file is an indication that an internal application error occurred.
+# This information is useful for debugging. Please open a case with Xilinx
+# Technical Support with this file and a testcase attached.
+#-------------------------------------------------------------------------------
+2/21/17 8:24:50 PM
+ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+
+	at ui.h.e.CF(SourceFile:217)
+	at ui.h.I.CF(SourceFile:702)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:368)
+	at ui.frmwork.HTclEventBroker.bb(SourceFile:354)
+	at ui.project.a.een(SourceFile:759)
+	at ui.project.a.cleanup(SourceFile:608)
+	at ui.project.r.cleanup(SourceFile:631)
+	at ui.PlanAhead.aJj(SourceFile:335)
+	at ui.PlanAhead.a(SourceFile:1192)
+	at ui.frmwork.a.i.c(SourceFile:35)
+	at ui.frmwork.HTclEventBroker.a(SourceFile:233)
+	at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325)
+	at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method)
+	at ui.e.gY(SourceFile:195)
+	at ui.bl.run(SourceFile:882)
+	at ui.cd.run(SourceFile:1821)
+	at ui.views.F.aw.a(SourceFile:341)
+	at ui.cd.b(SourceFile:1809)
+	at ui.cd.a(SourceFile:1784)
+	at ui.PlanAhead.a(SourceFile:778)
+	at ui.aL.c(SourceFile:885)
+	at ui.aL.aHs(SourceFile:824)
+	at ui.bk.windowClosing(SourceFile:503)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
+	at java.awt.Window.processWindowEvent(Window.java:2051)
+	at javax.swing.JFrame.processWindowEvent(JFrame.java:296)
+	at java.awt.Window.processEvent(Window.java:2009)
+	at ui.aL.processEvent(SourceFile:1214)
+	at java.awt.Component.dispatchEventImpl(Component.java:4861)
+	at java.awt.Container.dispatchEventImpl(Container.java:2287)
+	at java.awt.Window.dispatchEventImpl(Window.java:2719)
+	at java.awt.Component.dispatchEvent(Component.java:4687)
+	at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729)
+	at java.awt.EventQueue.access$200(EventQueue.java:103)
+	at java.awt.EventQueue$3.run(EventQueue.java:688)
+	at java.awt.EventQueue$3.run(EventQueue.java:686)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87)
+	at java.awt.EventQueue$4.run(EventQueue.java:702)
+	at java.awt.EventQueue$4.run(EventQueue.java:700)
+	at java.security.AccessController.doPrivileged(Native Method)
+	at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
+	at java.awt.EventQueue.dispatchEvent(EventQueue.java:699)
+	at ui.frmwork.a.e.dispatchEvent(SourceFile:73)
+	at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242)
+	at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161)
+	at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146)
+	at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138)
+	at java.awt.EventDispatchThread.run(EventDispatchThread.java:91)
+
diff --git a/planAhead_run_1/FPGA-led-lights.data/constrs_1/fileset.xml b/planAhead_run_1/FPGA-led-lights.data/constrs_1/fileset.xml
new file mode 100644
index 0000000..27cbdc8
--- /dev/null
+++ b/planAhead_run_1/FPGA-led-lights.data/constrs_1/fileset.xml
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../../../Downloads/BPC3011-Papilio_Pro-general.ucf">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PPRDIR/../../../Downloads/BPC3011-Papilio_Pro-general.ucf"/>
+      <Option Name="ConstrsType" Val="UCF"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_1/FPGA-led-lights.data/sim_1/fileset.xml b/planAhead_run_1/FPGA-led-lights.data/sim_1/fileset.xml
new file mode 100644
index 0000000..ec597fc
--- /dev/null
+++ b/planAhead_run_1/FPGA-led-lights.data/sim_1/fileset.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="led"/>
+      <Option Name="TopLib" Val="work"/>
+      <Option Name="TopRTLFile" Val="$PPRDIR/../led.v"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+      <Option Name="SrcSet" Val="sources_1"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_1/FPGA-led-lights.data/sources_1/fileset.xml b/planAhead_run_1/FPGA-led-lights.data/sources_1/fileset.xml
new file mode 100644
index 0000000..40e913b
--- /dev/null
+++ b/planAhead_run_1/FPGA-led-lights.data/sources_1/fileset.xml
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PPRDIR/../led.v">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+        <Attr Name="UsedInSimulation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="led"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_1/FPGA-led-lights.data/wt/project.wpc b/planAhead_run_1/FPGA-led-lights.data/wt/project.wpc
new file mode 100644
index 0000000..5fed558
--- /dev/null
+++ b/planAhead_run_1/FPGA-led-lights.data/wt/project.wpc
@@ -0,0 +1,4 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+6d6f64655f636f756e7465727c4953454d6f6465:1
+eof:
diff --git a/planAhead_run_1/FPGA-led-lights.data/wt/webtalk_pa.xml b/planAhead_run_1/FPGA-led-lights.data/wt/webtalk_pa.xml
new file mode 100644
index 0000000..828cdf0
--- /dev/null
+++ b/planAhead_run_1/FPGA-led-lights.data/wt/webtalk_pa.xml
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Tue Feb 21 20:21:00 2017">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="5162b49b77234a039edc109f3f038375" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="PlanAhead Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="0" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
+<property name="ISEMode" value="1" type="ISEMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/planAhead_run_1/FPGA-led-lights.ppr b/planAhead_run_1/FPGA-led-lights.ppr
new file mode 100644
index 0000000..31d6ba7
--- /dev/null
+++ b/planAhead_run_1/FPGA-led-lights.ppr
@@ -0,0 +1,27 @@
+<?xml version="1.0"?>
+<!--Product Version: PlanAhead v14.7 (64-bit)-->
+<Project Version="4" Minor="36">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<FileSet Dir="sim_1" File="fileset.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Id" Val="26f160cfb2d947038c3a341ff51c7e3c"/>
+		<Option Name="Part" Val="xc3s250evq100-4"/>
+		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+		<Option Name="TargetLanguage" Val="Verilog"/>
+		<Option Name="TargetSimulator" Val="ISim"/>
+		<Option Name="Board" Val=""/>
+		<Option Name="SourceMgmtMode" Val="All"/>
+		<Option Name="ActiveSimSet" Val="sim_1"/>
+		<Option Name="CxlOverwriteLibs" Val="1"/>
+		<Option Name="CxlFuncsim" Val="1"/>
+		<Option Name="CxlTimesim" Val="1"/>
+		<Option Name="CxlCore" Val="1"/>
+		<Option Name="CxlEdk" Val="0"/>
+		<Option Name="CxlExcludeCores" Val="1"/>
+		<Option Name="CxlExcludeSubLibs" Val="0"/>
+	</Config>
+</Project>
+
diff --git a/planAhead_run_1/planAhead.jou b/planAhead_run_1/planAhead.jou
new file mode 100644
index 0000000..1826b7c
--- /dev/null
+++ b/planAhead_run_1/planAhead.jou
@@ -0,0 +1,11 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Start of session at: Tue Feb 21 20:20:00 2017
+# Process ID: 7603
+# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_1/planAhead.log
+# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_1/planAhead.jou
+#-----------------------------------------------------------
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromHdl.tcl
+update_compile_order -fileset sim_1
diff --git a/planAhead_run_1/planAhead.log b/planAhead_run_1/planAhead.log
new file mode 100644
index 0000000..fce3fae
--- /dev/null
+++ b/planAhead_run_1/planAhead.log
@@ -0,0 +1,160 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Start of session at: Tue Feb 21 20:20:00 2017
+# Process ID: 7603
+# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_1/planAhead.log
+# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_1/planAhead.jou
+#-----------------------------------------------------------
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromHdl.tcl
+# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_1" -part xc3s250evq100-4
+# set_param project.pinAheadLayout yes
+# set srcset [get_property srcset [current_run -impl]]
+# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1'
+# set hdlfile [add_files [list {led.v}]]
+# set_property file_type Verilog $hdlfile
+# set_property library work $hdlfile
+# set_property top led $srcset
+# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+# open_rtl_design -part xc3s250evq100-4
+Using Verific elaboration
+Parsing VHDL file "/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify
+Analyzing Verilog file "/home/yannherklotz/Github/FPGA-led-lights/led.v" into library work
+INFO: [Designutils 20-910] Reading macro library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn
+Parsing EDIF File [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn]
+Finished Parsing EDIF File [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn]
+Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/ClockRegion.xml
+Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/ClockBuffers.xml
+Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/vq100/Package.xml
+Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/IOStandards.xml
+INFO: [Device 21-19] Loading pkg sso from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/vq100/SSORules.xml
+Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/drc.xml
+INFO: [Timing 38-77] Reading timing library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib.
+INFO: [Timing 38-34] Done reading timing library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib.
+Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P144 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:25]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P101 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:30]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P51 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:33]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P56 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:34]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P75 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:39]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P81 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:41]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P93 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:45]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P100 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:47]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:48]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:48]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P97 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:49]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:50]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:50]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P87 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:51]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:52]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:52]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P82 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:53]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P80 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:54]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:55]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:55]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P74 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:56]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:57]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:57]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:58]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:58]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P59 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:59]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:60]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:60]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P55 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:61]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:62]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:62]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(15)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:63]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(15)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:63]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P114 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:64]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P115 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:65]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P116 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:66]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P117 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:67]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P118 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:68]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P119 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:69]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P120 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:70]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P121 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:71]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P123 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:72]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P124 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:73]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P126 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:74]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P127 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:75]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P131 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:76]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P132 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:77]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P133 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:78]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P134 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:79]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P140 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:80]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P139 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:81]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P138 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:82]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P137 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:83]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P46 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:84]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P45 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:85]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:86]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:86]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:87]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:87]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:88]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:88]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:89]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:89]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P141 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:90]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:91]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:91]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:92]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:92]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:93]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:93]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(1)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:94]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(1)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:94]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:95]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:95]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(3)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:96]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(3)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:96]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P14 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:97]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(5)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:98]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(5)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:98]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:99]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:99]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P8 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:100]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P21 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:101]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:102]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:102]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:103]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:103]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:104]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:104]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:105]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:105]
+INFO: [Common 17-14] Message 'Constraints 18-11' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings.
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P29 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:107]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P7 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:109]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P143 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:111]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P142 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:112]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P6 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:113]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P1 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:116]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P112 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:119]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P107 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:120]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P109 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:121]
+INFO: [Common 17-14] Message 'Designutils 20-30' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings.
+Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+INFO: [Designutils 20-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Phase 0 | Netlist Checksum: a999cfc1
+update_compile_order -fileset sim_1
+exit
+ERROR: [#UNDEF] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+ (See /home/yannherklotz/Github/FPGA-led-lights/planAhead_pid7603.debug)
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 20:21:04 2017...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/planAhead_run_1/planAhead_run.log b/planAhead_run_1/planAhead_run.log
new file mode 100644
index 0000000..cfddfda
--- /dev/null
+++ b/planAhead_run_1/planAhead_run.log
@@ -0,0 +1,189 @@
+
+****** PlanAhead v14.7 (64-bit)
+  **** Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromHdl.tcl
+# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_1" -part xc3s250evq100-4
+# set_param project.pinAheadLayout yes
+# set srcset [get_property srcset [current_run -impl]]
+# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1'
+# set hdlfile [add_files [list {led.v}]]
+# set_property file_type Verilog $hdlfile
+# set_property library work $hdlfile
+# set_property top led $srcset
+# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+# open_rtl_design -part xc3s250evq100-4
+Using Verific elaboration
+Parsing VHDL file "/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify
+Analyzing Verilog file "/home/yannherklotz/Github/FPGA-led-lights/led.v" into library work
+INFO: [Designutils 20-910] Reading macro library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn
+Parsing EDIF File [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn]
+Finished Parsing EDIF File [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn]
+Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/ClockRegion.xml
+Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/ClockBuffers.xml
+Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/vq100/Package.xml
+Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/IOStandards.xml
+INFO: [Device 21-19] Loading pkg sso from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/vq100/SSORules.xml
+Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/drc.xml
+INFO: [Timing 38-77] Reading timing library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib.
+INFO: [Timing 38-34] Done reading timing library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib.
+Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P144 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:25]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P101 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:30]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P51 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:33]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P56 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:34]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P75 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:39]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P81 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:41]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P93 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:45]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P100 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:47]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:48]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:48]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P97 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:49]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:50]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:50]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P87 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:51]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:52]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:52]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P82 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:53]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P80 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:54]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:55]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:55]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P74 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:56]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:57]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:57]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:58]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:58]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P59 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:59]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:60]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:60]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P55 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:61]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:62]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:62]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(15)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:63]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(15)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:63]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P114 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:64]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P115 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:65]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P116 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:66]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P117 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:67]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P118 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:68]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P119 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:69]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P120 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:70]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P121 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:71]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P123 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:72]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P124 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:73]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P126 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:74]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P127 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:75]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P131 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:76]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P132 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:77]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P133 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:78]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P134 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:79]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P140 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:80]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P139 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:81]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P138 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:82]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P137 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:83]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P46 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:84]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P45 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:85]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:86]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:86]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:87]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:87]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:88]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:88]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:89]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:89]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P141 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:90]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:91]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:91]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:92]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:92]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:93]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:93]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(1)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:94]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(1)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:94]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:95]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:95]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(3)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:96]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(3)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:96]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P14 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:97]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(5)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:98]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(5)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:98]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:99]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:99]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P8 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:100]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P21 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:101]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:102]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:102]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:103]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:103]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:104]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:104]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:105]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_DATA(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:105]
+INFO: [Common 17-14] Message 'Constraints 18-11' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings.
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P29 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:107]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P7 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:109]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P143 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:111]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P142 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:112]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P6 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:113]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P1 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:116]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P112 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:119]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P107 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:120]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P109 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:121]
+INFO: [Common 17-14] Message 'Designutils 20-30' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings.
+Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+INFO: [Designutils 20-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Phase 0 | Netlist Checksum: a999cfc1
+update_compile_order -fileset sim_1
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+exit
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 20:21:04 2017...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif b/planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif
new file mode 100644
index 0000000..ad5dec0
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif
@@ -0,0 +1,1149 @@
+(edif led
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2017 2 21 20 23 20)
+      (program "Xilinx ngc2edif" (version "P.20131013"))
+      (author "Xilinx. Inc ")
+      (comment "This EDIF netlist is to be used within supported synthesis tools")
+      (comment "for determining resource/timing estimates of the design component")
+      (comment "represented by this netlist.")
+      (comment "Command line: -mdp2sp -w -secure led.ngc led.edif ")))
+  (external UNISIMS
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell GND
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port G
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell VCC
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port P
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDE
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port CE
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDS
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FDR
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port R
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell MUXCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port DI
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell XORCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port LI
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT4
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell OBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT1
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell BUFGP
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell INV
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT4_L
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port LO
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+  )
+
+  (library led_lib
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell led
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CLK
+              (direction INPUT)
+            )
+            (port A0
+              (direction OUTPUT)
+            )
+            (designator "xc3s250e-4-vq100")
+            (property TYPE (string "led") (owner "Xilinx"))
+            (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_ALIAS (string "led_led") (owner "Xilinx"))
+          )
+          (contents
+            (instance XST_GND
+              (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance XST_VCC
+              (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename A0_renamed_0 "A0")
+              (viewRef view_1 (cellRef FDE (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance count_1
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance count_0
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance count_2
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance count_3
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance count_4
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance count_5
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance count_6
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance count_7
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance count_8
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance count_9
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance count_10
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance count_11
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance count_12
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance count_13
+              (viewRef view_1 (cellRef FDR (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance count_14
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance count_15
+              (viewRef view_1 (cellRef FDS (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_0___renamed_1 "Mcount_count_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_0__ "Mcount_count_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_1___renamed_2 "Mcount_count_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_1__ "Mcount_count_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_2___renamed_3 "Mcount_count_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_2__ "Mcount_count_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_3___renamed_4 "Mcount_count_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_3__ "Mcount_count_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_4___renamed_5 "Mcount_count_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_4__ "Mcount_count_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_5___renamed_6 "Mcount_count_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_5__ "Mcount_count_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_6___renamed_7 "Mcount_count_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_6__ "Mcount_count_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_7___renamed_8 "Mcount_count_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_7__ "Mcount_count_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_8___renamed_9 "Mcount_count_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_8__ "Mcount_count_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_9___renamed_10 "Mcount_count_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_9__ "Mcount_count_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_10___renamed_11 "Mcount_count_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_10__ "Mcount_count_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_11___renamed_12 "Mcount_count_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_11__ "Mcount_count_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_12___renamed_13 "Mcount_count_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_12__ "Mcount_count_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_13___renamed_14 "Mcount_count_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_13__ "Mcount_count_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_14___renamed_15 "Mcount_count_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_14__ "Mcount_count_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_15__ "Mcount_count_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename A0_cmp_eq000025_renamed_16 "A0_cmp_eq000025")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0001") (owner "Xilinx"))
+            )
+            (instance (rename A0_cmp_eq000049_renamed_17 "A0_cmp_eq000049")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0001") (owner "Xilinx"))
+            )
+            (instance (rename A0_cmp_eq000062_renamed_18 "A0_cmp_eq000062")
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0001") (owner "Xilinx"))
+            )
+            (instance A0_cmp_eq000076
+              (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "8000") (owner "Xilinx"))
+            )
+            (instance (rename A0_OBUF_renamed_19 "A0_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_1__rt_renamed_20 "Mcount_count_cy<1>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_2__rt_renamed_21 "Mcount_count_cy<2>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_3__rt_renamed_22 "Mcount_count_cy<3>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_4__rt_renamed_23 "Mcount_count_cy<4>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_5__rt_renamed_24 "Mcount_count_cy<5>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_6__rt_renamed_25 "Mcount_count_cy<6>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_7__rt_renamed_26 "Mcount_count_cy<7>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_8__rt_renamed_27 "Mcount_count_cy<8>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_9__rt_renamed_28 "Mcount_count_cy<9>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_10__rt_renamed_29 "Mcount_count_cy<10>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_11__rt_renamed_30 "Mcount_count_cy<11>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_12__rt_renamed_31 "Mcount_count_cy<12>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_13__rt_renamed_32 "Mcount_count_cy<13>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_14__rt_renamed_33 "Mcount_count_cy<14>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_15__rt_renamed_34 "Mcount_count_xor<15>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename CLK_BUFGP_renamed_35 "CLK_BUFGP")
+              (viewRef view_1 (cellRef BUFGP (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_0__INV_0 "Mcount_count_lut<0>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance A0_not00031_INV_0
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename A0_cmp_eq000012_renamed_36 "A0_cmp_eq000012")
+              (viewRef view_1 (cellRef LUT4_L (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0001") (owner "Xilinx"))
+            )
+            (net A0
+              (joined
+                (portRef A0)
+                (portRef O (instanceRef A0_OBUF_renamed_19))
+              )
+            )
+            (net A0_OBUF
+              (joined
+                (portRef Q (instanceRef A0_renamed_0))
+                (portRef I (instanceRef A0_OBUF_renamed_19))
+                (portRef I (instanceRef A0_not00031_INV_0))
+              )
+            )
+            (net A0_cmp_eq000012
+              (joined
+                (portRef I0 (instanceRef A0_cmp_eq000076))
+                (portRef LO (instanceRef A0_cmp_eq000012_renamed_36))
+              )
+            )
+            (net A0_cmp_eq000025
+              (joined
+                (portRef O (instanceRef A0_cmp_eq000025_renamed_16))
+                (portRef I1 (instanceRef A0_cmp_eq000076))
+              )
+            )
+            (net A0_cmp_eq000049
+              (joined
+                (portRef O (instanceRef A0_cmp_eq000049_renamed_17))
+                (portRef I2 (instanceRef A0_cmp_eq000076))
+              )
+            )
+            (net A0_cmp_eq000062
+              (joined
+                (portRef O (instanceRef A0_cmp_eq000062_renamed_18))
+                (portRef I3 (instanceRef A0_cmp_eq000076))
+              )
+            )
+            (net A0_not0002_inv
+              (joined
+                (portRef CE (instanceRef A0_renamed_0))
+                (portRef S (instanceRef count_1))
+                (portRef S (instanceRef count_0))
+                (portRef S (instanceRef count_2))
+                (portRef S (instanceRef count_3))
+                (portRef R (instanceRef count_4))
+                (portRef R (instanceRef count_5))
+                (portRef S (instanceRef count_6))
+                (portRef R (instanceRef count_7))
+                (portRef S (instanceRef count_8))
+                (portRef S (instanceRef count_9))
+                (portRef R (instanceRef count_10))
+                (portRef R (instanceRef count_11))
+                (portRef R (instanceRef count_12))
+                (portRef R (instanceRef count_13))
+                (portRef S (instanceRef count_14))
+                (portRef S (instanceRef count_15))
+                (portRef O (instanceRef A0_cmp_eq000076))
+              )
+            )
+            (net A0_not0003
+              (joined
+                (portRef D (instanceRef A0_renamed_0))
+                (portRef O (instanceRef A0_not00031_INV_0))
+              )
+            )
+            (net CLK
+              (joined
+                (portRef CLK)
+                (portRef I (instanceRef CLK_BUFGP_renamed_35))
+              )
+            )
+            (net CLK_BUFGP
+              (joined
+                (portRef C (instanceRef A0_renamed_0))
+                (portRef C (instanceRef count_1))
+                (portRef C (instanceRef count_0))
+                (portRef C (instanceRef count_2))
+                (portRef C (instanceRef count_3))
+                (portRef C (instanceRef count_4))
+                (portRef C (instanceRef count_5))
+                (portRef C (instanceRef count_6))
+                (portRef C (instanceRef count_7))
+                (portRef C (instanceRef count_8))
+                (portRef C (instanceRef count_9))
+                (portRef C (instanceRef count_10))
+                (portRef C (instanceRef count_11))
+                (portRef C (instanceRef count_12))
+                (portRef C (instanceRef count_13))
+                (portRef C (instanceRef count_14))
+                (portRef C (instanceRef count_15))
+                (portRef O (instanceRef CLK_BUFGP_renamed_35))
+              )
+            )
+            (net (rename Mcount_count_cy_0__ "Mcount_count_cy<0>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_0___renamed_1))
+                (portRef CI (instanceRef Mcount_count_cy_1___renamed_2))
+                (portRef CI (instanceRef Mcount_count_xor_1__))
+              )
+            )
+            (net (rename Mcount_count_cy_10__ "Mcount_count_cy<10>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_10___renamed_11))
+                (portRef CI (instanceRef Mcount_count_cy_11___renamed_12))
+                (portRef CI (instanceRef Mcount_count_xor_11__))
+              )
+            )
+            (net (rename Mcount_count_cy_10__rt "Mcount_count_cy<10>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_10__rt_renamed_29))
+                (portRef S (instanceRef Mcount_count_cy_10___renamed_11))
+                (portRef LI (instanceRef Mcount_count_xor_10__))
+              )
+            )
+            (net (rename Mcount_count_cy_11__ "Mcount_count_cy<11>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_11___renamed_12))
+                (portRef CI (instanceRef Mcount_count_cy_12___renamed_13))
+                (portRef CI (instanceRef Mcount_count_xor_12__))
+              )
+            )
+            (net (rename Mcount_count_cy_11__rt "Mcount_count_cy<11>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_11__rt_renamed_30))
+                (portRef S (instanceRef Mcount_count_cy_11___renamed_12))
+                (portRef LI (instanceRef Mcount_count_xor_11__))
+              )
+            )
+            (net (rename Mcount_count_cy_12__ "Mcount_count_cy<12>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_12___renamed_13))
+                (portRef CI (instanceRef Mcount_count_cy_13___renamed_14))
+                (portRef CI (instanceRef Mcount_count_xor_13__))
+              )
+            )
+            (net (rename Mcount_count_cy_12__rt "Mcount_count_cy<12>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_12__rt_renamed_31))
+                (portRef S (instanceRef Mcount_count_cy_12___renamed_13))
+                (portRef LI (instanceRef Mcount_count_xor_12__))
+              )
+            )
+            (net (rename Mcount_count_cy_13__ "Mcount_count_cy<13>")
+              (joined
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+                (portRef CI (instanceRef Mcount_count_cy_14___renamed_15))
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+              )
+            )
+            (net (rename Mcount_count_cy_13__rt "Mcount_count_cy<13>_rt")
+              (joined
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+              )
+            )
+            (net (rename Mcount_count_cy_14__ "Mcount_count_cy<14>")
+              (joined
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+                (portRef CI (instanceRef Mcount_count_xor_15__))
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+            (net (rename Mcount_count_cy_1__ "Mcount_count_cy<1>")
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+                (portRef CI (instanceRef Mcount_count_cy_2___renamed_3))
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+            )
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+              )
+            )
+            (net (rename Mcount_count_cy_2__ "Mcount_count_cy<2>")
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+                (portRef CI (instanceRef Mcount_count_cy_3___renamed_4))
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+              )
+            )
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+              (joined
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+              )
+            )
+            (net (rename Mcount_count_cy_3__ "Mcount_count_cy<3>")
+              (joined
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+                (portRef CI (instanceRef Mcount_count_cy_4___renamed_5))
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+            )
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+            (net (rename Mcount_count_cy_4__ "Mcount_count_cy<4>")
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+            )
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+            (net (rename Mcount_count_cy_6__ "Mcount_count_cy<6>")
+              (joined
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+              )
+            )
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+              (joined
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+                (portRef S (instanceRef Mcount_count_cy_6___renamed_7))
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+              )
+            )
+            (net (rename Mcount_count_cy_7__ "Mcount_count_cy<7>")
+              (joined
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+                (portRef CI (instanceRef Mcount_count_cy_8___renamed_9))
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+              )
+            )
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+                (portRef S (instanceRef Mcount_count_cy_7___renamed_8))
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+              )
+            )
+            (net (rename Mcount_count_cy_8__ "Mcount_count_cy<8>")
+              (joined
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+                (portRef CI (instanceRef Mcount_count_cy_9___renamed_10))
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+              )
+            )
+            (net (rename Mcount_count_cy_8__rt "Mcount_count_cy<8>_rt")
+              (joined
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+                (portRef S (instanceRef Mcount_count_cy_8___renamed_9))
+                (portRef LI (instanceRef Mcount_count_xor_8__))
+              )
+            )
+            (net (rename Mcount_count_cy_9__ "Mcount_count_cy<9>")
+              (joined
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+                (portRef CI (instanceRef Mcount_count_cy_10___renamed_11))
+                (portRef CI (instanceRef Mcount_count_xor_10__))
+              )
+            )
+            (net (rename Mcount_count_cy_9__rt "Mcount_count_cy<9>_rt")
+              (joined
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+                (portRef S (instanceRef Mcount_count_cy_9___renamed_10))
+                (portRef LI (instanceRef Mcount_count_xor_9__))
+              )
+            )
+            (net (rename Mcount_count_lut_0__ "Mcount_count_lut<0>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_0___renamed_1))
+                (portRef LI (instanceRef Mcount_count_xor_0__))
+                (portRef O (instanceRef Mcount_count_lut_0__INV_0))
+              )
+            )
+            (net (rename Mcount_count_xor_15__rt "Mcount_count_xor<15>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_15__rt_renamed_34))
+                (portRef LI (instanceRef Mcount_count_xor_15__))
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+            )
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+              (joined
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+                (portRef CI (instanceRef Mcount_count_cy_0___renamed_1))
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+                (portRef DI (instanceRef Mcount_count_cy_2___renamed_3))
+                (portRef DI (instanceRef Mcount_count_cy_3___renamed_4))
+                (portRef DI (instanceRef Mcount_count_cy_4___renamed_5))
+                (portRef DI (instanceRef Mcount_count_cy_5___renamed_6))
+                (portRef DI (instanceRef Mcount_count_cy_6___renamed_7))
+                (portRef DI (instanceRef Mcount_count_cy_7___renamed_8))
+                (portRef DI (instanceRef Mcount_count_cy_8___renamed_9))
+                (portRef DI (instanceRef Mcount_count_cy_9___renamed_10))
+                (portRef DI (instanceRef Mcount_count_cy_10___renamed_11))
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+                (portRef DI (instanceRef Mcount_count_cy_13___renamed_14))
+                (portRef DI (instanceRef Mcount_count_cy_14___renamed_15))
+              )
+            )
+            (net N1
+              (joined
+                (portRef P (instanceRef XST_VCC))
+                (portRef DI (instanceRef Mcount_count_cy_0___renamed_1))
+              )
+            )
+            (net (rename Result_0__ "Result<0>")
+              (joined
+                (portRef D (instanceRef count_0))
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+              )
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+              (joined
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+                (portRef O (instanceRef Mcount_count_xor_10__))
+              )
+            )
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+              (joined
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+                (portRef O (instanceRef Mcount_count_xor_11__))
+              )
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+              (joined
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+              )
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+              (joined
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+              )
+            )
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+              (joined
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+              )
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+              (joined
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+              )
+            )
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+              (joined
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+              )
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+              (joined
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+              )
+            )
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+              (joined
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+              (joined
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+              )
+            )
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+              (joined
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+              )
+            )
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+              (joined
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+              )
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+              (joined
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+              )
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+              (joined
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+              )
+            )
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+              (joined
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+                (portRef O (instanceRef Mcount_count_xor_9__))
+              )
+            )
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+                (portRef I0 (instanceRef A0_cmp_eq000012_renamed_36))
+              )
+            )
+            (net (rename count_1__ "count<1>")
+              (joined
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+                (portRef I0 (instanceRef Mcount_count_cy_1__rt_renamed_20))
+                (portRef I1 (instanceRef A0_cmp_eq000012_renamed_36))
+              )
+            )
+            (net (rename count_10__ "count<10>")
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+                (portRef I0 (instanceRef Mcount_count_cy_10__rt_renamed_29))
+              )
+            )
+            (net (rename count_11__ "count<11>")
+              (joined
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+                (portRef I3 (instanceRef A0_cmp_eq000049_renamed_17))
+                (portRef I0 (instanceRef Mcount_count_cy_11__rt_renamed_30))
+              )
+            )
+            (net (rename count_12__ "count<12>")
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+                (portRef I0 (instanceRef Mcount_count_cy_12__rt_renamed_31))
+              )
+            )
+            (net (rename count_13__ "count<13>")
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+              )
+            )
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+                (portRef I0 (instanceRef Mcount_count_cy_14__rt_renamed_33))
+              )
+            )
+            (net (rename count_15__ "count<15>")
+              (joined
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+                (portRef I3 (instanceRef A0_cmp_eq000062_renamed_18))
+                (portRef I0 (instanceRef Mcount_count_xor_15__rt_renamed_34))
+              )
+            )
+            (net (rename count_2__ "count<2>")
+              (joined
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+                (portRef I0 (instanceRef Mcount_count_cy_2__rt_renamed_21))
+                (portRef I2 (instanceRef A0_cmp_eq000012_renamed_36))
+              )
+            )
+            (net (rename count_3__ "count<3>")
+              (joined
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+                (portRef I0 (instanceRef Mcount_count_cy_3__rt_renamed_22))
+                (portRef I3 (instanceRef A0_cmp_eq000012_renamed_36))
+              )
+            )
+            (net (rename count_4__ "count<4>")
+              (joined
+                (portRef Q (instanceRef count_4))
+                (portRef I0 (instanceRef A0_cmp_eq000025_renamed_16))
+                (portRef I0 (instanceRef Mcount_count_cy_4__rt_renamed_23))
+              )
+            )
+            (net (rename count_5__ "count<5>")
+              (joined
+                (portRef Q (instanceRef count_5))
+                (portRef I1 (instanceRef A0_cmp_eq000025_renamed_16))
+                (portRef I0 (instanceRef Mcount_count_cy_5__rt_renamed_24))
+              )
+            )
+            (net (rename count_6__ "count<6>")
+              (joined
+                (portRef Q (instanceRef count_6))
+                (portRef I2 (instanceRef A0_cmp_eq000025_renamed_16))
+                (portRef I0 (instanceRef Mcount_count_cy_6__rt_renamed_25))
+              )
+            )
+            (net (rename count_7__ "count<7>")
+              (joined
+                (portRef Q (instanceRef count_7))
+                (portRef I3 (instanceRef A0_cmp_eq000025_renamed_16))
+                (portRef I0 (instanceRef Mcount_count_cy_7__rt_renamed_26))
+              )
+            )
+            (net (rename count_8__ "count<8>")
+              (joined
+                (portRef Q (instanceRef count_8))
+                (portRef I0 (instanceRef A0_cmp_eq000049_renamed_17))
+                (portRef I0 (instanceRef Mcount_count_cy_8__rt_renamed_27))
+              )
+            )
+            (net (rename count_9__ "count<9>")
+              (joined
+                (portRef Q (instanceRef count_9))
+                (portRef I1 (instanceRef A0_cmp_eq000049_renamed_17))
+                (portRef I0 (instanceRef Mcount_count_cy_9__rt_renamed_28))
+              )
+            )
+          )
+      )
+    )
+  )
+
+  (design led
+    (cellRef led
+      (libraryRef led_lib)
+    )
+    (property PART (string "xc3s250e-4-vq100") (owner "Xilinx"))
+  )
+)
+
diff --git a/planAhead_run_2/FPGA-led-lights.data/constrs_1/designprops.xml b/planAhead_run_2/FPGA-led-lights.data/constrs_1/designprops.xml
new file mode 100644
index 0000000..cbe1094
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/constrs_1/designprops.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0"?>
+<Compat Version="1" Minor="4">
+	<CompatParts>
+	</CompatParts>
+	<ConfigModes>
+	</ConfigModes>
+	<PortProps>
+	</PortProps>
+</Compat>
+
diff --git a/planAhead_run_2/FPGA-led-lights.data/constrs_1/fileset.xml b/planAhead_run_2/FPGA-led-lights.data/constrs_1/fileset.xml
new file mode 100644
index 0000000..993cb20
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/constrs_1/fileset.xml
@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../../../Downloads/BPC3011-Papilio_Pro-general.ucf">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PDATADIR/constrs_1/designprops.xml">
+      <FileInfo SFType="CompatPartsDb"/>
+    </File>
+    <File Path="$PDATADIR/constrs_1/usercols.xml">
+      <FileInfo SFType="UserColsDb"/>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PPRDIR/../../../Downloads/BPC3011-Papilio_Pro-general.ucf"/>
+      <Option Name="ConstrsType" Val="UCF"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_2/FPGA-led-lights.data/constrs_1/usercols.xml b/planAhead_run_2/FPGA-led-lights.data/constrs_1/usercols.xml
new file mode 100644
index 0000000..eb20735
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/constrs_1/usercols.xml
@@ -0,0 +1,4 @@
+<?xml version="1.0"?>
+<UserColInfo Version="1" Minor="0">
+</UserColInfo>
+
diff --git a/planAhead_run_2/FPGA-led-lights.data/runs/impl_1.psg b/planAhead_run_2/FPGA-led-lights.data/runs/impl_1.psg
new file mode 100644
index 0000000..147f3a9
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/runs/impl_1.psg
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+	<StratHandle Name="ISE Defaults" Flow="ISE14">
+		<Desc>ISE Defaults, including packing registers in IOs off</Desc>
+	</StratHandle>
+	<Step Id="ngdbuild">
+	</Step>
+	<Step Id="map">
+		<Option Id="FFPackEnum">3</Option>
+	</Step>
+	<Step Id="par">
+	</Step>
+	<Step Id="trce">
+	</Step>
+	<Step Id="xdl">
+	</Step>
+	<Step Id="bitgen">
+	</Step>
+</Strategy>
+
diff --git a/planAhead_run_2/FPGA-led-lights.data/runs/runs.xml b/planAhead_run_2/FPGA-led-lights.data/runs/runs.xml
new file mode 100644
index 0000000..fe0b8b1
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/runs/runs.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="8">
+	<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc3s250evq100-4" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/>
+</Runs>
+
diff --git a/planAhead_run_2/FPGA-led-lights.data/sim_1/fileset.xml b/planAhead_run_2/FPGA-led-lights.data/sim_1/fileset.xml
new file mode 100644
index 0000000..65babe3
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/sim_1/fileset.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+      <Option Name="SrcSet" Val="sources_1"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_2/FPGA-led-lights.data/sources_1/chipscope.xml b/planAhead_run_2/FPGA-led-lights.data/sources_1/chipscope.xml
new file mode 100644
index 0000000..3fd9702
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/sources_1/chipscope.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<ChipScope Version="1" Minor="3">
+	<UnassignedNets>
+	</UnassignedNets>
+</ChipScope>
+
diff --git a/planAhead_run_2/FPGA-led-lights.data/sources_1/fileset.xml b/planAhead_run_2/FPGA-led-lights.data/sources_1/fileset.xml
new file mode 100644
index 0000000..9fa644d
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/sources_1/fileset.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="EDIFSrcs"/>
+    <File Path="$PPRDIR/../led.ngc">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <File Path="$PDATADIR/sources_1/ports.xml">
+      <FileInfo SFType="PortsDb"/>
+    </File>
+    <File Path="$PDATADIR/sources_1/chipscope.xml">
+      <FileInfo SFType="ChipscopeDb"/>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="GateLvl"/>
+      <Option Name="GateLvlMode" Val="EDIF"/>
+      <Option Name="TopFile" Val="$PPRDIR/../led.ngc"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_2/FPGA-led-lights.data/sources_1/ports.xml b/planAhead_run_2/FPGA-led-lights.data/sources_1/ports.xml
new file mode 100644
index 0000000..6edcb86
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/sources_1/ports.xml
@@ -0,0 +1,8 @@
+<?xml version="1.0"?>
+<Interface Version="1" Minor="1">
+	<Ifc Id="ROOT" Top="1">
+		<Port Id="CLK" Dir="IN"/>
+		<Port Id="A0" Dir="OUT"/>
+	</Ifc>
+</Interface>
+
diff --git a/planAhead_run_2/FPGA-led-lights.data/wt/java_command_handlers.wdf b/planAhead_run_2/FPGA-led-lights.data/wt/java_command_handlers.wdf
new file mode 100644
index 0000000..9880428
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/wt/java_command_handlers.wdf
@@ -0,0 +1,3 @@
+version:1
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766564657369676e:31:00:00
+eof:3611541694
diff --git a/planAhead_run_2/FPGA-led-lights.data/wt/project.wpc b/planAhead_run_2/FPGA-led-lights.data/wt/project.wpc
new file mode 100644
index 0000000..5fed558
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/wt/project.wpc
@@ -0,0 +1,4 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+6d6f64655f636f756e7465727c4953454d6f6465:1
+eof:
diff --git a/planAhead_run_2/FPGA-led-lights.data/wt/webtalk_pa.xml b/planAhead_run_2/FPGA-led-lights.data/wt/webtalk_pa.xml
new file mode 100644
index 0000000..8f356a2
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/wt/webtalk_pa.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Tue Feb 21 20:24:50 2017">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="a3587ea880e14b0e9bda22648980fcfc" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="GateLvl" type="DesignMode"/>
+<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="SaveDesign" value="1" type="JavaHandler"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="0" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
+<property name="ISEMode" value="3" type="ISEMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/planAhead_run_2/FPGA-led-lights.ppr b/planAhead_run_2/FPGA-led-lights.ppr
new file mode 100644
index 0000000..96f3b15
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.ppr
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<!--Product Version: PlanAhead v14.7 (64-bit)-->
+<Project Version="4" Minor="36">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<FileSet Dir="sim_1" File="fileset.xml"/>
+	<RunSet Dir="runs" File="runs.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Id" Val="78311367463f4d3c9b887dc98454a31b"/>
+		<Option Name="Part" Val="xc3s250evq100-4"/>
+		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+		<Option Name="TargetLanguage" Val="Verilog"/>
+		<Option Name="TargetSimulator" Val="ISim"/>
+		<Option Name="Board" Val=""/>
+		<Option Name="SourceMgmtMode" Val="All"/>
+		<Option Name="ActiveSimSet" Val="sim_1"/>
+		<Option Name="CxlOverwriteLibs" Val="1"/>
+		<Option Name="CxlFuncsim" Val="1"/>
+		<Option Name="CxlTimesim" Val="1"/>
+		<Option Name="CxlCore" Val="1"/>
+		<Option Name="CxlEdk" Val="0"/>
+		<Option Name="CxlExcludeCores" Val="1"/>
+		<Option Name="CxlExcludeSubLibs" Val="0"/>
+	</Config>
+</Project>
+
diff --git a/planAhead_run_2/planAhead.jou b/planAhead_run_2/planAhead.jou
new file mode 100644
index 0000000..2c63572
--- /dev/null
+++ b/planAhead_run_2/planAhead.jou
@@ -0,0 +1,17 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Start of session at: Tue Feb 21 20:23:09 2017
+# Process ID: 7744
+# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2/planAhead.log
+# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2/planAhead.jou
+#-----------------------------------------------------------
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNetlist.tcl
+startgroup
+set_property package_pin P48 [get_ports A0]
+endgroup
+set_property is_loc_fixed false [get_ports [list  A0]]
+set_property is_loc_fixed true [get_ports [list  A0]]
+set_property iostandard LVTTL [get_ports [list A0]]
+save_constraints
diff --git a/planAhead_run_2/planAhead.log b/planAhead_run_2/planAhead.log
new file mode 100644
index 0000000..cc59684
--- /dev/null
+++ b/planAhead_run_2/planAhead.log
@@ -0,0 +1,182 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Start of session at: Tue Feb 21 20:23:09 2017
+# Process ID: 7744
+# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2/planAhead.log
+# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2/planAhead.jou
+#-----------------------------------------------------------
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNetlist.tcl
+# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2" -part xc3s250evq100-4
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} }
+# set_param project.pinAheadLayout  yes
+# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1'
+# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+# link_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to project part: xc3s250evq100-4
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design led.ngc ...
+WARNING:NetListWriters:298 - No output is written to led.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file led.edif ...
+ngc2edif: Total memory usage is 103520 kilobytes
+
+Parsing EDIF File [./planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+Finished Parsing EDIF File [./planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+INFO: [Designutils 20-910] Reading macro library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn
+Parsing EDIF File [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn]
+Finished Parsing EDIF File [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn]
+Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/ClockRegion.xml
+Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/ClockBuffers.xml
+Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/vq100/Package.xml
+Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/IOStandards.xml
+INFO: [Device 21-19] Loading pkg sso from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/vq100/SSORules.xml
+Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/drc.xml
+INFO: [Timing 38-77] Reading timing library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib.
+INFO: [Timing 38-34] Done reading timing library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib.
+Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P144 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:25]
+WARNING: [Constraints 18-7] Clock terminal CLK is located on a non-clock IO location P94 this can produce sub-optimal results [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:29]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P101 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:30]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:32]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:32]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P51 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:33]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P56 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:34]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(3)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:35]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(3)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:35]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:36]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:36]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(5)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:37]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(5)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:37]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:38]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:38]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P75 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:39]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:40]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:40]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P81 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:41]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:42]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:42]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:43]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:43]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:44]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:44]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P93 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:45]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:46]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:46]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P100 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:47]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:48]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:48]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P97 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:49]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:50]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:50]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P87 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:51]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:52]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:52]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P82 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:53]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P80 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:54]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:55]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:55]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P74 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:56]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:57]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:57]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:58]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:58]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P59 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:59]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:60]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:60]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P55 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:61]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:62]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:62]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(15)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:63]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(15)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:63]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P114 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:64]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P115 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:65]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P116 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:66]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P117 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:67]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P118 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:68]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P119 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:69]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P120 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:70]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P121 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:71]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P123 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:72]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P124 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:73]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P126 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:74]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P127 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:75]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P131 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:76]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P132 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:77]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P133 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:78]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P134 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:79]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P140 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:80]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P139 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:81]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P138 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:82]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P137 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:83]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P46 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:84]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P45 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:85]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:86]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:86]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:87]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:87]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:88]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:88]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:89]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:89]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P141 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:90]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:91]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:91]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:92]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:92]
+INFO: [Common 17-14] Message 'Constraints 18-11' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings.
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P14 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:97]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P8 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:100]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P21 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:101]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P29 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:107]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P7 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:109]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P143 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:111]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P142 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:112]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P6 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:113]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P1 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:116]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P112 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:119]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P107 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:120]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P109 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:121]
+INFO: [Common 17-14] Message 'Designutils 20-30' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings.
+Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+INFO: [Designutils 20-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Phase 0 | Netlist Checksum: 790793e2
+link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:06 . Memory (MB): peak = 2818.992 ; gain = 132.293
+startgroup
+set_property package_pin P48 [get_ports A0]
+endgroup
+set_property is_loc_fixed false [get_ports [list  A0]]
+set_property is_loc_fixed true [get_ports [list  A0]]
+set_property iostandard LVTTL [get_ports [list A0]]
+save_constraints
+exit
+ERROR: [#UNDEF] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+ (See /home/yannherklotz/Github/FPGA-led-lights/planAhead_pid7744.debug)
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 20:24:51 2017...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/planAhead_run_2/planAhead_run.log b/planAhead_run_2/planAhead_run.log
new file mode 100644
index 0000000..319ae82
--- /dev/null
+++ b/planAhead_run_2/planAhead_run.log
@@ -0,0 +1,179 @@
+
+****** PlanAhead v14.7 (64-bit)
+  **** Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNetlist.tcl
+# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_2" -part xc3s250evq100-4
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} }
+# set_param project.pinAheadLayout  yes
+# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1'
+# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+# link_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to project part: xc3s250evq100-4
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design led.ngc ...
+WARNING:NetListWriters:298 - No output is written to led.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file led.edif ...
+ngc2edif: Total memory usage is 103520 kilobytes
+
+Parsing EDIF File [./planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+Finished Parsing EDIF File [./planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+INFO: [Designutils 20-910] Reading macro library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn
+Parsing EDIF File [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn]
+Finished Parsing EDIF File [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/hd_int_macros.edn]
+Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/ClockRegion.xml
+Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/ClockBuffers.xml
+Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/vq100/Package.xml
+Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/IOStandards.xml
+INFO: [Device 21-19] Loading pkg sso from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/xc3s250e/vq100/SSORules.xml
+Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan3e/spartan3e/drc.xml
+INFO: [Timing 38-77] Reading timing library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib.
+INFO: [Timing 38-34] Done reading timing library /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan3e/spartan3e/spartan3e-4.lib.
+Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P144 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:25]
+WARNING: [Constraints 18-7] Clock terminal CLK is located on a non-clock IO location P94 this can produce sub-optimal results [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:29]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P101 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:30]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:32]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:32]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P51 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:33]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P56 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:34]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(3)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:35]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(3)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:35]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:36]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:36]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(5)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:37]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(5)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:37]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:38]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:38]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P75 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:39]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:40]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:40]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P81 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:41]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:42]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:42]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:43]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:43]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:44]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:44]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P93 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:45]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:46]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'A(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:46]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P100 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:47]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:48]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(0)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:48]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P97 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:49]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:50]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(2)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:50]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P87 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:51]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:52]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(4)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:52]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P82 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:53]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P80 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:54]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:55]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:55]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P74 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:56]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:57]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:57]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:58]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(10)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:58]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P59 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:59]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:60]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:60]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P55 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:61]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:62]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(14)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:62]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(15)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:63]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'B(15)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:63]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P114 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:64]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P115 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:65]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P116 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:66]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P117 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:67]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P118 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:68]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P119 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:69]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P120 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:70]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P121 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:71]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P123 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:72]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P124 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:73]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P126 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:74]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P127 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:75]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P131 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:76]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P132 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:77]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P133 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:78]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P134 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:79]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P140 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:80]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P139 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:81]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P138 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:82]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P137 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:83]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P46 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:84]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P45 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:85]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:86]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(6)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:86]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:87]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(7)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:87]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:88]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(8)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:88]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:89]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(9)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:89]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P141 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:90]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:91]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(11)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:91]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:92]
+CRITICAL WARNING: [Constraints 18-11] Could not find net or pin 'SDRAM_ADDR(12)' [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:92]
+INFO: [Common 17-14] Message 'Constraints 18-11' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings.
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P14 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:97]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P8 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:100]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P21 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:101]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P29 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:107]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P7 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:109]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P143 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:111]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P142 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:112]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P6 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:113]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P1 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:116]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P112 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:119]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P107 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:120]
+CRITICAL WARNING: [Designutils 20-30] Unrecognized site P109 [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf:121]
+INFO: [Common 17-14] Message 'Designutils 20-30' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings.
+Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+INFO: [Designutils 20-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Phase 0 | Netlist Checksum: 790793e2
+link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:06 . Memory (MB): peak = 2818.992 ; gain = 132.293
+startgroup
+set_property package_pin P48 [get_ports A0]
+endgroup
+set_property is_loc_fixed false [get_ports [list  A0]]
+set_property is_loc_fixed true [get_ports [list  A0]]
+set_property iostandard LVTTL [get_ports [list A0]]
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+save_constraints
+exit
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 20:24:51 2017...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/planAhead_run_3/FPGA-led-lights.data/cache/led_ngc_cb841106.edif b/planAhead_run_3/FPGA-led-lights.data/cache/led_ngc_cb841106.edif
new file mode 100644
index 0000000..0aaccc0
--- /dev/null
+++ b/planAhead_run_3/FPGA-led-lights.data/cache/led_ngc_cb841106.edif
@@ -0,0 +1,1286 @@
+(edif led
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2017 2 21 21 46 16)
+      (program "Xilinx ngc2edif" (version "P.20131013"))
+      (author "Xilinx. Inc ")
+      (comment "This EDIF netlist is to be used within supported synthesis tools")
+      (comment "for determining resource/timing estimates of the design component")
+      (comment "represented by this netlist.")
+      (comment "Command line: -mdp2sp -w -secure led.ngc led.edif ")))
+  (external UNISIMS
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell VCC
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port P
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell GND
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port G
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell MUXCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port DI
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell XORCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port LI
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT6
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port I4
+              (direction INPUT)
+            )
+            (port I5
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell OBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT1
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT3
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FD
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT2
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell BUFGP
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell INV
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+  )
+
+  (library led_lib
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell led
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CLK
+              (direction INPUT)
+            )
+            (port LED1
+              (direction OUTPUT)
+            )
+            (designator "xc6slx9-2-tqg144")
+            (property TYPE (string "led") (owner "Xilinx"))
+            (property SHREG_MIN_SIZE (string "2") (owner "Xilinx"))
+            (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx"))
+            (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_ALIAS (string "led_led") (owner "Xilinx"))
+          )
+          (contents
+            (instance XST_VCC
+              (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance XST_GND
+              (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_0___renamed_0 "Mcount_count_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_0__ "Mcount_count_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_1___renamed_1 "Mcount_count_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_1__ "Mcount_count_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_2___renamed_2 "Mcount_count_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_2__ "Mcount_count_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_3___renamed_3 "Mcount_count_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_3__ "Mcount_count_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_4___renamed_4 "Mcount_count_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_4__ "Mcount_count_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_5___renamed_5 "Mcount_count_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_5__ "Mcount_count_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_6___renamed_6 "Mcount_count_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_6__ "Mcount_count_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_7___renamed_7 "Mcount_count_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_7__ "Mcount_count_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_8___renamed_8 "Mcount_count_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_8__ "Mcount_count_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_9___renamed_9 "Mcount_count_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_9__ "Mcount_count_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_10___renamed_10 "Mcount_count_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_10__ "Mcount_count_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_11___renamed_11 "Mcount_count_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_11__ "Mcount_count_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_12___renamed_12 "Mcount_count_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_12__ "Mcount_count_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_13___renamed_13 "Mcount_count_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_13__ "Mcount_count_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_14___renamed_14 "Mcount_count_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_14__ "Mcount_count_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_15__ "Mcount_count_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename count_15__GND_1_o_equal_2_o_15_1_renamed_15 "count[15]_GND_1_o_equal_2_o<15>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename count_15__GND_1_o_equal_2_o_15_2 "count[15]_GND_1_o_equal_2_o<15>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename count_15__GND_1_o_equal_2_o_15_3 "count[15]_GND_1_o_equal_2_o<15>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0001000000000000") (owner "Xilinx"))
+            )
+            (instance (rename LED1_OBUF_renamed_16 "LED1_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_0__rt_renamed_17 "Mcount_count_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename LED1_dpot_renamed_18 "LED1_dpot")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAA9AAAAAAAA") (owner "Xilinx"))
+            )
+            (instance (rename LED1_rstpot_renamed_19 "LED1_rstpot")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E2") (owner "Xilinx"))
+            )
+            (instance (rename LED1_renamed_20 "LED1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_1_rstpot_renamed_21 "count_1_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_1
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_0_rstpot_renamed_22 "count_0_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_0
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_2_rstpot_renamed_23 "count_2_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_2
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_3_rstpot_renamed_24 "count_3_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_3
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_4_rstpot_renamed_25 "count_4_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_4
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_5_rstpot_renamed_26 "count_5_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_5
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_6_rstpot_renamed_27 "count_6_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_6
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_7_rstpot_renamed_28 "count_7_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_7
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_8_rstpot_renamed_29 "count_8_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_8
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_9_rstpot_renamed_30 "count_9_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_9
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_10_rstpot_renamed_31 "count_10_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_10
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_11_rstpot_renamed_32 "count_11_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_11
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_12_rstpot_renamed_33 "count_12_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_12
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_13_rstpot_renamed_34 "count_13_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_13
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_14_rstpot_renamed_35 "count_14_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_14
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_15_rstpot_renamed_36 "count_15_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_15
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename CLK_BUFGP_renamed_37 "CLK_BUFGP")
+              (viewRef view_1 (cellRef BUFGP (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_1__INV_0 "Mcount_count_lut<1>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_2__INV_0 "Mcount_count_lut<2>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_3__INV_0 "Mcount_count_lut<3>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_4__INV_0 "Mcount_count_lut<4>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_5__INV_0 "Mcount_count_lut<5>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_6__INV_0 "Mcount_count_lut<6>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_7__INV_0 "Mcount_count_lut<7>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_8__INV_0 "Mcount_count_lut<8>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_9__INV_0 "Mcount_count_lut<9>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_10__INV_0 "Mcount_count_lut<10>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_11__INV_0 "Mcount_count_lut<11>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_12__INV_0 "Mcount_count_lut<12>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_13__INV_0 "Mcount_count_lut<13>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_14__INV_0 "Mcount_count_lut<14>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_15__INV_0 "Mcount_count_lut<15>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (net CLK_BUFGP
+              (joined
+                (portRef C (instanceRef LED1_renamed_20))
+                (portRef C (instanceRef count_1))
+                (portRef C (instanceRef count_0))
+                (portRef C (instanceRef count_2))
+                (portRef C (instanceRef count_3))
+                (portRef C (instanceRef count_4))
+                (portRef C (instanceRef count_5))
+                (portRef C (instanceRef count_6))
+                (portRef C (instanceRef count_7))
+                (portRef C (instanceRef count_8))
+                (portRef C (instanceRef count_9))
+                (portRef C (instanceRef count_10))
+                (portRef C (instanceRef count_11))
+                (portRef C (instanceRef count_12))
+                (portRef C (instanceRef count_13))
+                (portRef C (instanceRef count_14))
+                (portRef C (instanceRef count_15))
+                (portRef O (instanceRef CLK_BUFGP_renamed_37))
+              )
+            )
+            (net (rename count_15__ "count<15>")
+              (joined
+                (portRef I4 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef count_15))
+                (portRef I (instanceRef Mcount_count_lut_15__INV_0))
+                (portRef I0 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_14__ "count<14>")
+              (joined
+                (portRef I3 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef count_14))
+                (portRef I (instanceRef Mcount_count_lut_14__INV_0))
+                (portRef I1 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_13__ "count<13>")
+              (joined
+                (portRef I1 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef count_13))
+                (portRef I (instanceRef Mcount_count_lut_13__INV_0))
+                (portRef I3 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_12__ "count<12>")
+              (joined
+                (portRef I2 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef count_12))
+                (portRef I (instanceRef Mcount_count_lut_12__INV_0))
+                (portRef I2 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_11__ "count<11>")
+              (joined
+                (portRef I5 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_11))
+                (portRef I (instanceRef Mcount_count_lut_11__INV_0))
+              )
+            )
+            (net (rename count_10__ "count<10>")
+              (joined
+                (portRef I4 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_10))
+                (portRef I (instanceRef Mcount_count_lut_10__INV_0))
+              )
+            )
+            (net (rename count_9__ "count<9>")
+              (joined
+                (portRef I3 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_9))
+                (portRef I (instanceRef Mcount_count_lut_9__INV_0))
+              )
+            )
+            (net (rename count_8__ "count<8>")
+              (joined
+                (portRef I2 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_8))
+                (portRef I (instanceRef Mcount_count_lut_8__INV_0))
+              )
+            )
+            (net (rename count_7__ "count<7>")
+              (joined
+                (portRef I0 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_7))
+                (portRef I (instanceRef Mcount_count_lut_7__INV_0))
+              )
+            )
+            (net (rename count_6__ "count<6>")
+              (joined
+                (portRef I1 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_6))
+                (portRef I (instanceRef Mcount_count_lut_6__INV_0))
+              )
+            )
+            (net (rename count_5__ "count<5>")
+              (joined
+                (portRef I5 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_5))
+                (portRef I (instanceRef Mcount_count_lut_5__INV_0))
+              )
+            )
+            (net (rename count_4__ "count<4>")
+              (joined
+                (portRef I4 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_4))
+                (portRef I (instanceRef Mcount_count_lut_4__INV_0))
+              )
+            )
+            (net (rename count_3__ "count<3>")
+              (joined
+                (portRef I3 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_3))
+                (portRef I (instanceRef Mcount_count_lut_3__INV_0))
+              )
+            )
+            (net (rename count_2__ "count<2>")
+              (joined
+                (portRef I2 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_2))
+                (portRef I (instanceRef Mcount_count_lut_2__INV_0))
+              )
+            )
+            (net (rename count_1__ "count<1>")
+              (joined
+                (portRef I0 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_1))
+                (portRef I (instanceRef Mcount_count_lut_1__INV_0))
+              )
+            )
+            (net (rename count_0__ "count<0>")
+              (joined
+                (portRef I1 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef I0 (instanceRef Mcount_count_cy_0__rt_renamed_17))
+                (portRef Q (instanceRef count_0))
+              )
+            )
+            (net LED1_OBUF
+              (joined
+                (portRef I (instanceRef LED1_OBUF_renamed_16))
+                (portRef I0 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef LED1_renamed_20))
+                (portRef I0 (instanceRef LED1_rstpot_renamed_19))
+              )
+            )
+            (net (rename count_15__GND_1_o_equal_2_o "count[15]_GND_1_o_equal_2_o")
+              (joined
+                (portRef O (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+                (portRef I1 (instanceRef count_1_rstpot_renamed_21))
+                (portRef I1 (instanceRef count_0_rstpot_renamed_22))
+                (portRef I1 (instanceRef count_2_rstpot_renamed_23))
+                (portRef I1 (instanceRef count_3_rstpot_renamed_24))
+                (portRef I1 (instanceRef count_4_rstpot_renamed_25))
+                (portRef I1 (instanceRef count_5_rstpot_renamed_26))
+                (portRef I1 (instanceRef count_6_rstpot_renamed_27))
+                (portRef I1 (instanceRef count_7_rstpot_renamed_28))
+                (portRef I1 (instanceRef count_8_rstpot_renamed_29))
+                (portRef I1 (instanceRef count_9_rstpot_renamed_30))
+                (portRef I1 (instanceRef count_10_rstpot_renamed_31))
+                (portRef I1 (instanceRef count_11_rstpot_renamed_32))
+                (portRef I1 (instanceRef count_12_rstpot_renamed_33))
+                (portRef I1 (instanceRef count_13_rstpot_renamed_34))
+                (portRef I1 (instanceRef count_14_rstpot_renamed_35))
+                (portRef I1 (instanceRef count_15_rstpot_renamed_36))
+              )
+            )
+            (net N0
+              (joined
+                (portRef P (instanceRef XST_VCC))
+                (portRef CI (instanceRef Mcount_count_cy_0___renamed_0))
+                (portRef CI (instanceRef Mcount_count_xor_0__))
+                (portRef DI (instanceRef Mcount_count_cy_1___renamed_1))
+                (portRef DI (instanceRef Mcount_count_cy_2___renamed_2))
+                (portRef DI (instanceRef Mcount_count_cy_3___renamed_3))
+                (portRef DI (instanceRef Mcount_count_cy_4___renamed_4))
+                (portRef DI (instanceRef Mcount_count_cy_5___renamed_5))
+                (portRef DI (instanceRef Mcount_count_cy_6___renamed_6))
+                (portRef DI (instanceRef Mcount_count_cy_7___renamed_7))
+                (portRef DI (instanceRef Mcount_count_cy_8___renamed_8))
+                (portRef DI (instanceRef Mcount_count_cy_9___renamed_9))
+                (portRef DI (instanceRef Mcount_count_cy_10___renamed_10))
+                (portRef DI (instanceRef Mcount_count_cy_11___renamed_11))
+                (portRef DI (instanceRef Mcount_count_cy_12___renamed_12))
+                (portRef DI (instanceRef Mcount_count_cy_13___renamed_13))
+                (portRef DI (instanceRef Mcount_count_cy_14___renamed_14))
+              )
+            )
+            (net N1
+              (joined
+                (portRef G (instanceRef XST_GND))
+                (portRef DI (instanceRef Mcount_count_cy_0___renamed_0))
+              )
+            )
+            (net (rename Result_0__ "Result<0>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_0__))
+                (portRef I0 (instanceRef count_0_rstpot_renamed_22))
+              )
+            )
+            (net (rename Result_1__ "Result<1>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_1__))
+                (portRef I0 (instanceRef count_1_rstpot_renamed_21))
+              )
+            )
+            (net (rename Result_2__ "Result<2>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_2__))
+                (portRef I0 (instanceRef count_2_rstpot_renamed_23))
+              )
+            )
+            (net (rename Result_3__ "Result<3>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_3__))
+                (portRef I0 (instanceRef count_3_rstpot_renamed_24))
+              )
+            )
+            (net (rename Result_4__ "Result<4>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_4__))
+                (portRef I0 (instanceRef count_4_rstpot_renamed_25))
+              )
+            )
+            (net (rename Result_5__ "Result<5>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_5__))
+                (portRef I0 (instanceRef count_5_rstpot_renamed_26))
+              )
+            )
+            (net (rename Result_6__ "Result<6>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_6__))
+                (portRef I0 (instanceRef count_6_rstpot_renamed_27))
+              )
+            )
+            (net (rename Result_7__ "Result<7>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_7__))
+                (portRef I0 (instanceRef count_7_rstpot_renamed_28))
+              )
+            )
+            (net (rename Result_8__ "Result<8>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_8__))
+                (portRef I0 (instanceRef count_8_rstpot_renamed_29))
+              )
+            )
+            (net (rename Result_9__ "Result<9>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_9__))
+                (portRef I0 (instanceRef count_9_rstpot_renamed_30))
+              )
+            )
+            (net (rename Result_10__ "Result<10>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_10__))
+                (portRef I0 (instanceRef count_10_rstpot_renamed_31))
+              )
+            )
+            (net (rename Result_11__ "Result<11>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_11__))
+                (portRef I0 (instanceRef count_11_rstpot_renamed_32))
+              )
+            )
+            (net (rename Result_12__ "Result<12>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_12__))
+                (portRef I0 (instanceRef count_12_rstpot_renamed_33))
+              )
+            )
+            (net (rename Result_13__ "Result<13>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_13__))
+                (portRef I0 (instanceRef count_13_rstpot_renamed_34))
+              )
+            )
+            (net (rename Result_14__ "Result<14>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_14__))
+                (portRef I0 (instanceRef count_14_rstpot_renamed_35))
+              )
+            )
+            (net (rename Result_15__ "Result<15>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_15__))
+                (portRef I0 (instanceRef count_15_rstpot_renamed_36))
+              )
+            )
+            (net (rename Mcount_count_cy_0__ "Mcount_count_cy<0>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_0___renamed_0))
+                (portRef CI (instanceRef Mcount_count_cy_1___renamed_1))
+                (portRef CI (instanceRef Mcount_count_xor_1__))
+              )
+            )
+            (net (rename Mcount_count_lut_1__ "Mcount_count_lut<1>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_1___renamed_1))
+                (portRef LI (instanceRef Mcount_count_xor_1__))
+                (portRef O (instanceRef Mcount_count_lut_1__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_1__ "Mcount_count_cy<1>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_1___renamed_1))
+                (portRef CI (instanceRef Mcount_count_cy_2___renamed_2))
+                (portRef CI (instanceRef Mcount_count_xor_2__))
+              )
+            )
+            (net (rename Mcount_count_lut_2__ "Mcount_count_lut<2>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_2___renamed_2))
+                (portRef LI (instanceRef Mcount_count_xor_2__))
+                (portRef O (instanceRef Mcount_count_lut_2__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_2__ "Mcount_count_cy<2>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_2___renamed_2))
+                (portRef CI (instanceRef Mcount_count_cy_3___renamed_3))
+                (portRef CI (instanceRef Mcount_count_xor_3__))
+              )
+            )
+            (net (rename Mcount_count_lut_3__ "Mcount_count_lut<3>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_3___renamed_3))
+                (portRef LI (instanceRef Mcount_count_xor_3__))
+                (portRef O (instanceRef Mcount_count_lut_3__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_3__ "Mcount_count_cy<3>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_3___renamed_3))
+                (portRef CI (instanceRef Mcount_count_cy_4___renamed_4))
+                (portRef CI (instanceRef Mcount_count_xor_4__))
+              )
+            )
+            (net (rename Mcount_count_lut_4__ "Mcount_count_lut<4>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_4___renamed_4))
+                (portRef LI (instanceRef Mcount_count_xor_4__))
+                (portRef O (instanceRef Mcount_count_lut_4__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_4__ "Mcount_count_cy<4>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_4___renamed_4))
+                (portRef CI (instanceRef Mcount_count_cy_5___renamed_5))
+                (portRef CI (instanceRef Mcount_count_xor_5__))
+              )
+            )
+            (net (rename Mcount_count_lut_5__ "Mcount_count_lut<5>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_5___renamed_5))
+                (portRef LI (instanceRef Mcount_count_xor_5__))
+                (portRef O (instanceRef Mcount_count_lut_5__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_5__ "Mcount_count_cy<5>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_5___renamed_5))
+                (portRef CI (instanceRef Mcount_count_cy_6___renamed_6))
+                (portRef CI (instanceRef Mcount_count_xor_6__))
+              )
+            )
+            (net (rename Mcount_count_lut_6__ "Mcount_count_lut<6>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_6___renamed_6))
+                (portRef LI (instanceRef Mcount_count_xor_6__))
+                (portRef O (instanceRef Mcount_count_lut_6__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_6__ "Mcount_count_cy<6>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_6___renamed_6))
+                (portRef CI (instanceRef Mcount_count_cy_7___renamed_7))
+                (portRef CI (instanceRef Mcount_count_xor_7__))
+              )
+            )
+            (net (rename Mcount_count_lut_7__ "Mcount_count_lut<7>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_7___renamed_7))
+                (portRef LI (instanceRef Mcount_count_xor_7__))
+                (portRef O (instanceRef Mcount_count_lut_7__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_7__ "Mcount_count_cy<7>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_7___renamed_7))
+                (portRef CI (instanceRef Mcount_count_cy_8___renamed_8))
+                (portRef CI (instanceRef Mcount_count_xor_8__))
+              )
+            )
+            (net (rename Mcount_count_lut_8__ "Mcount_count_lut<8>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_8___renamed_8))
+                (portRef LI (instanceRef Mcount_count_xor_8__))
+                (portRef O (instanceRef Mcount_count_lut_8__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_8__ "Mcount_count_cy<8>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_8___renamed_8))
+                (portRef CI (instanceRef Mcount_count_cy_9___renamed_9))
+                (portRef CI (instanceRef Mcount_count_xor_9__))
+              )
+            )
+            (net (rename Mcount_count_lut_9__ "Mcount_count_lut<9>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_9___renamed_9))
+                (portRef LI (instanceRef Mcount_count_xor_9__))
+                (portRef O (instanceRef Mcount_count_lut_9__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_9__ "Mcount_count_cy<9>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_9___renamed_9))
+                (portRef CI (instanceRef Mcount_count_cy_10___renamed_10))
+                (portRef CI (instanceRef Mcount_count_xor_10__))
+              )
+            )
+            (net (rename Mcount_count_lut_10__ "Mcount_count_lut<10>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_10___renamed_10))
+                (portRef LI (instanceRef Mcount_count_xor_10__))
+                (portRef O (instanceRef Mcount_count_lut_10__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_10__ "Mcount_count_cy<10>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_10___renamed_10))
+                (portRef CI (instanceRef Mcount_count_cy_11___renamed_11))
+                (portRef CI (instanceRef Mcount_count_xor_11__))
+              )
+            )
+            (net (rename Mcount_count_lut_11__ "Mcount_count_lut<11>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_11___renamed_11))
+                (portRef LI (instanceRef Mcount_count_xor_11__))
+                (portRef O (instanceRef Mcount_count_lut_11__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_11__ "Mcount_count_cy<11>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_11___renamed_11))
+                (portRef CI (instanceRef Mcount_count_cy_12___renamed_12))
+                (portRef CI (instanceRef Mcount_count_xor_12__))
+              )
+            )
+            (net (rename Mcount_count_lut_12__ "Mcount_count_lut<12>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_12___renamed_12))
+                (portRef LI (instanceRef Mcount_count_xor_12__))
+                (portRef O (instanceRef Mcount_count_lut_12__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_12__ "Mcount_count_cy<12>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_12___renamed_12))
+                (portRef CI (instanceRef Mcount_count_cy_13___renamed_13))
+                (portRef CI (instanceRef Mcount_count_xor_13__))
+              )
+            )
+            (net (rename Mcount_count_lut_13__ "Mcount_count_lut<13>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_13___renamed_13))
+                (portRef LI (instanceRef Mcount_count_xor_13__))
+                (portRef O (instanceRef Mcount_count_lut_13__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_13__ "Mcount_count_cy<13>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_13___renamed_13))
+                (portRef CI (instanceRef Mcount_count_cy_14___renamed_14))
+                (portRef CI (instanceRef Mcount_count_xor_14__))
+              )
+            )
+            (net (rename Mcount_count_lut_14__ "Mcount_count_lut<14>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_14___renamed_14))
+                (portRef LI (instanceRef Mcount_count_xor_14__))
+                (portRef O (instanceRef Mcount_count_lut_14__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_14__ "Mcount_count_cy<14>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_14___renamed_14))
+                (portRef CI (instanceRef Mcount_count_xor_15__))
+              )
+            )
+            (net (rename Mcount_count_lut_15__ "Mcount_count_lut<15>")
+              (joined
+                (portRef LI (instanceRef Mcount_count_xor_15__))
+                (portRef O (instanceRef Mcount_count_lut_15__INV_0))
+              )
+            )
+            (net (rename count_15__GND_1_o_equal_2_o_15__ "count[15]_GND_1_o_equal_2_o<15>")
+              (joined
+                (portRef O (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef I5 (instanceRef LED1_dpot_renamed_18))
+                (portRef I4 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_15__GND_1_o_equal_2_o_15_1 "count[15]_GND_1_o_equal_2_o<15>1")
+              (joined
+                (portRef O (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef I5 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+                (portRef I1 (instanceRef LED1_rstpot_renamed_19))
+              )
+            )
+            (net CLK
+              (joined
+                (portRef CLK)
+                (portRef I (instanceRef CLK_BUFGP_renamed_37))
+              )
+            )
+            (net LED1
+              (joined
+                (portRef LED1)
+                (portRef O (instanceRef LED1_OBUF_renamed_16))
+              )
+            )
+            (net (rename Mcount_count_cy_0__rt "Mcount_count_cy<0>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_0__rt_renamed_17))
+                (portRef S (instanceRef Mcount_count_cy_0___renamed_0))
+                (portRef LI (instanceRef Mcount_count_xor_0__))
+              )
+            )
+            (net LED1_dpot
+              (joined
+                (portRef O (instanceRef LED1_dpot_renamed_18))
+                (portRef I2 (instanceRef LED1_rstpot_renamed_19))
+              )
+            )
+            (net LED1_rstpot
+              (joined
+                (portRef O (instanceRef LED1_rstpot_renamed_19))
+                (portRef D (instanceRef LED1_renamed_20))
+              )
+            )
+            (net count_1_rstpot
+              (joined
+                (portRef O (instanceRef count_1_rstpot_renamed_21))
+                (portRef D (instanceRef count_1))
+              )
+            )
+            (net count_0_rstpot
+              (joined
+                (portRef O (instanceRef count_0_rstpot_renamed_22))
+                (portRef D (instanceRef count_0))
+              )
+            )
+            (net count_2_rstpot
+              (joined
+                (portRef O (instanceRef count_2_rstpot_renamed_23))
+                (portRef D (instanceRef count_2))
+              )
+            )
+            (net count_3_rstpot
+              (joined
+                (portRef O (instanceRef count_3_rstpot_renamed_24))
+                (portRef D (instanceRef count_3))
+              )
+            )
+            (net count_4_rstpot
+              (joined
+                (portRef O (instanceRef count_4_rstpot_renamed_25))
+                (portRef D (instanceRef count_4))
+              )
+            )
+            (net count_5_rstpot
+              (joined
+                (portRef O (instanceRef count_5_rstpot_renamed_26))
+                (portRef D (instanceRef count_5))
+              )
+            )
+            (net count_6_rstpot
+              (joined
+                (portRef O (instanceRef count_6_rstpot_renamed_27))
+                (portRef D (instanceRef count_6))
+              )
+            )
+            (net count_7_rstpot
+              (joined
+                (portRef O (instanceRef count_7_rstpot_renamed_28))
+                (portRef D (instanceRef count_7))
+              )
+            )
+            (net count_8_rstpot
+              (joined
+                (portRef O (instanceRef count_8_rstpot_renamed_29))
+                (portRef D (instanceRef count_8))
+              )
+            )
+            (net count_9_rstpot
+              (joined
+                (portRef O (instanceRef count_9_rstpot_renamed_30))
+                (portRef D (instanceRef count_9))
+              )
+            )
+            (net count_10_rstpot
+              (joined
+                (portRef O (instanceRef count_10_rstpot_renamed_31))
+                (portRef D (instanceRef count_10))
+              )
+            )
+            (net count_11_rstpot
+              (joined
+                (portRef O (instanceRef count_11_rstpot_renamed_32))
+                (portRef D (instanceRef count_11))
+              )
+            )
+            (net count_12_rstpot
+              (joined
+                (portRef O (instanceRef count_12_rstpot_renamed_33))
+                (portRef D (instanceRef count_12))
+              )
+            )
+            (net count_13_rstpot
+              (joined
+                (portRef O (instanceRef count_13_rstpot_renamed_34))
+                (portRef D (instanceRef count_13))
+              )
+            )
+            (net count_14_rstpot
+              (joined
+                (portRef O (instanceRef count_14_rstpot_renamed_35))
+                (portRef D (instanceRef count_14))
+              )
+            )
+            (net count_15_rstpot
+              (joined
+                (portRef O (instanceRef count_15_rstpot_renamed_36))
+                (portRef D (instanceRef count_15))
+              )
+            )
+          )
+      )
+    )
+  )
+
+  (design led
+    (cellRef led
+      (libraryRef led_lib)
+    )
+    (property PART (string "xc6slx9-2-tqg144") (owner "Xilinx"))
+  )
+)
+
diff --git a/planAhead_run_3/FPGA-led-lights.data/constrs_1/fileset.xml b/planAhead_run_3/FPGA-led-lights.data/constrs_1/fileset.xml
new file mode 100644
index 0000000..27cbdc8
--- /dev/null
+++ b/planAhead_run_3/FPGA-led-lights.data/constrs_1/fileset.xml
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../../../Downloads/BPC3011-Papilio_Pro-general.ucf">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PPRDIR/../../../Downloads/BPC3011-Papilio_Pro-general.ucf"/>
+      <Option Name="ConstrsType" Val="UCF"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_3/FPGA-led-lights.data/runs/impl_1.psg b/planAhead_run_3/FPGA-led-lights.data/runs/impl_1.psg
new file mode 100644
index 0000000..147f3a9
--- /dev/null
+++ b/planAhead_run_3/FPGA-led-lights.data/runs/impl_1.psg
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+	<StratHandle Name="ISE Defaults" Flow="ISE14">
+		<Desc>ISE Defaults, including packing registers in IOs off</Desc>
+	</StratHandle>
+	<Step Id="ngdbuild">
+	</Step>
+	<Step Id="map">
+		<Option Id="FFPackEnum">3</Option>
+	</Step>
+	<Step Id="par">
+	</Step>
+	<Step Id="trce">
+	</Step>
+	<Step Id="xdl">
+	</Step>
+	<Step Id="bitgen">
+	</Step>
+</Strategy>
+
diff --git a/planAhead_run_3/FPGA-led-lights.data/runs/runs.xml b/planAhead_run_3/FPGA-led-lights.data/runs/runs.xml
new file mode 100644
index 0000000..7708ac8
--- /dev/null
+++ b/planAhead_run_3/FPGA-led-lights.data/runs/runs.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="8">
+	<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx9tqg144-2" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/>
+</Runs>
+
diff --git a/planAhead_run_3/FPGA-led-lights.data/sim_1/fileset.xml b/planAhead_run_3/FPGA-led-lights.data/sim_1/fileset.xml
new file mode 100644
index 0000000..65babe3
--- /dev/null
+++ b/planAhead_run_3/FPGA-led-lights.data/sim_1/fileset.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+      <Option Name="SrcSet" Val="sources_1"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_3/FPGA-led-lights.data/sources_1/fileset.xml b/planAhead_run_3/FPGA-led-lights.data/sources_1/fileset.xml
new file mode 100644
index 0000000..ddc517f
--- /dev/null
+++ b/planAhead_run_3/FPGA-led-lights.data/sources_1/fileset.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="EDIFSrcs"/>
+    <File Path="$PPRDIR/../led.ngc">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="GateLvl"/>
+      <Option Name="GateLvlMode" Val="EDIF"/>
+      <Option Name="TopFile" Val="$PPRDIR/../led.ngc"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_3/FPGA-led-lights.data/wt/project.wpc b/planAhead_run_3/FPGA-led-lights.data/wt/project.wpc
new file mode 100644
index 0000000..5fed558
--- /dev/null
+++ b/planAhead_run_3/FPGA-led-lights.data/wt/project.wpc
@@ -0,0 +1,4 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+6d6f64655f636f756e7465727c4953454d6f6465:1
+eof:
diff --git a/planAhead_run_3/FPGA-led-lights.data/wt/webtalk_pa.xml b/planAhead_run_3/FPGA-led-lights.data/wt/webtalk_pa.xml
new file mode 100644
index 0000000..bcf762b
--- /dev/null
+++ b/planAhead_run_3/FPGA-led-lights.data/wt/webtalk_pa.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Tue Feb 21 21:46:52 2017">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="d7760f03443a44478d77a0a1b11453ed" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="GateLvl" type="DesignMode"/>
+<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="0" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
+<property name="ISEMode" value="5" type="ISEMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/planAhead_run_3/FPGA-led-lights.ppr b/planAhead_run_3/FPGA-led-lights.ppr
new file mode 100644
index 0000000..37dd0f8
--- /dev/null
+++ b/planAhead_run_3/FPGA-led-lights.ppr
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<!--Product Version: PlanAhead v14.7 (64-bit)-->
+<Project Version="4" Minor="36">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<FileSet Dir="sim_1" File="fileset.xml"/>
+	<RunSet Dir="runs" File="runs.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Id" Val="d4c47d74488c47ee94ce84f048fd9639"/>
+		<Option Name="Part" Val="xc6slx9tqg144-2"/>
+		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+		<Option Name="TargetLanguage" Val="Verilog"/>
+		<Option Name="TargetSimulator" Val="ISim"/>
+		<Option Name="Board" Val=""/>
+		<Option Name="SourceMgmtMode" Val="All"/>
+		<Option Name="ActiveSimSet" Val="sim_1"/>
+		<Option Name="CxlOverwriteLibs" Val="1"/>
+		<Option Name="CxlFuncsim" Val="1"/>
+		<Option Name="CxlTimesim" Val="1"/>
+		<Option Name="CxlCore" Val="1"/>
+		<Option Name="CxlEdk" Val="0"/>
+		<Option Name="CxlExcludeCores" Val="1"/>
+		<Option Name="CxlExcludeSubLibs" Val="0"/>
+	</Config>
+</Project>
+
diff --git a/planAhead_run_3/planAhead.jou b/planAhead_run_3/planAhead.jou
new file mode 100644
index 0000000..7488ccd
--- /dev/null
+++ b/planAhead_run_3/planAhead.jou
@@ -0,0 +1,10 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Start of session at: Tue Feb 21 21:46:05 2017
+# Process ID: 24048
+# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_3/planAhead.log
+# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_3/planAhead.jou
+#-----------------------------------------------------------
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNetlist.tcl
diff --git a/planAhead_run_3/planAhead.log b/planAhead_run_3/planAhead.log
new file mode 100644
index 0000000..6d93eb0
--- /dev/null
+++ b/planAhead_run_3/planAhead.log
@@ -0,0 +1,70 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Start of session at: Tue Feb 21 21:46:05 2017
+# Process ID: 24048
+# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_3/planAhead.log
+# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_3/planAhead.jou
+#-----------------------------------------------------------
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNetlist.tcl
+# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_3" -part xc6slx9tqg144-2
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} }
+# set_param project.pinAheadLayout  yes
+# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1'
+# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+# link_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to project part: xc6slx9tqg144-2
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design led.ngc ...
+WARNING:NetListWriters:298 - No output is written to led.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file led.edif ...
+ngc2edif: Total memory usage is 103532 kilobytes
+
+Parsing EDIF File [./planAhead_run_3/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+Finished Parsing EDIF File [./planAhead_run_3/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
+Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
+Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
+Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
+Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 1 instances were transformed.
+  BUFGP => BUFGP (IBUF, BUFG): 1 instances
+
+Phase 0 | Netlist Checksum: 23693229
+link_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 2838.551 ; gain = 157.191
+exit
+ERROR: [#UNDEF] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+ (See /home/yannherklotz/Github/FPGA-led-lights/planAhead_pid24048.debug)
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 21:46:54 2017...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/planAhead_run_3/planAhead_run.log b/planAhead_run_3/planAhead_run.log
new file mode 100644
index 0000000..fdddce6
--- /dev/null
+++ b/planAhead_run_3/planAhead_run.log
@@ -0,0 +1,61 @@
+
+****** PlanAhead v14.7 (64-bit)
+  **** Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNetlist.tcl
+# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_3" -part xc6slx9tqg144-2
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} }
+# set_param project.pinAheadLayout  yes
+# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1'
+# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+# link_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to project part: xc6slx9tqg144-2
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design led.ngc ...
+WARNING:NetListWriters:298 - No output is written to led.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file led.edif ...
+ngc2edif: Total memory usage is 103532 kilobytes
+
+Parsing EDIF File [./planAhead_run_3/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+Finished Parsing EDIF File [./planAhead_run_3/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
+Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
+Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
+Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
+Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 1 instances were transformed.
+  BUFGP => BUFGP (IBUF, BUFG): 1 instances
+
+Phase 0 | Netlist Checksum: 23693229
+link_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 2838.551 ; gain = 157.191
+exit
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 21:46:54 2017...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif b/planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif
new file mode 100644
index 0000000..d478d16
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif
@@ -0,0 +1,1286 @@
+(edif led
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2017 2 21 21 50 3)
+      (program "Xilinx ngc2edif" (version "P.20131013"))
+      (author "Xilinx. Inc ")
+      (comment "This EDIF netlist is to be used within supported synthesis tools")
+      (comment "for determining resource/timing estimates of the design component")
+      (comment "represented by this netlist.")
+      (comment "Command line: -mdp2sp -w -secure led.ngc led.edif ")))
+  (external UNISIMS
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell VCC
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port P
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell GND
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port G
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell MUXCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port DI
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell XORCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port LI
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT6
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port I4
+              (direction INPUT)
+            )
+            (port I5
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell OBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT1
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT3
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FD
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT2
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell BUFGP
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell INV
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+  )
+
+  (library led_lib
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell led
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CLK
+              (direction INPUT)
+            )
+            (port LED1
+              (direction OUTPUT)
+            )
+            (designator "xc6slx9-2-tqg144")
+            (property TYPE (string "led") (owner "Xilinx"))
+            (property SHREG_MIN_SIZE (string "2") (owner "Xilinx"))
+            (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx"))
+            (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_ALIAS (string "led_led") (owner "Xilinx"))
+          )
+          (contents
+            (instance XST_VCC
+              (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance XST_GND
+              (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_0___renamed_0 "Mcount_count_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_0__ "Mcount_count_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_1___renamed_1 "Mcount_count_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_1__ "Mcount_count_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_2___renamed_2 "Mcount_count_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_2__ "Mcount_count_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_3___renamed_3 "Mcount_count_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_3__ "Mcount_count_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_4___renamed_4 "Mcount_count_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_4__ "Mcount_count_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_5___renamed_5 "Mcount_count_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_5__ "Mcount_count_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_6___renamed_6 "Mcount_count_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_6__ "Mcount_count_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_7___renamed_7 "Mcount_count_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_7__ "Mcount_count_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_8___renamed_8 "Mcount_count_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_8__ "Mcount_count_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_9___renamed_9 "Mcount_count_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_9__ "Mcount_count_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_10___renamed_10 "Mcount_count_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_10__ "Mcount_count_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_11___renamed_11 "Mcount_count_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_11__ "Mcount_count_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_12___renamed_12 "Mcount_count_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_12__ "Mcount_count_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_13___renamed_13 "Mcount_count_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_13__ "Mcount_count_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_14___renamed_14 "Mcount_count_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_14__ "Mcount_count_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_15__ "Mcount_count_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename count_15__GND_1_o_equal_2_o_15_1_renamed_15 "count[15]_GND_1_o_equal_2_o<15>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename count_15__GND_1_o_equal_2_o_15_2 "count[15]_GND_1_o_equal_2_o<15>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename count_15__GND_1_o_equal_2_o_15_3 "count[15]_GND_1_o_equal_2_o<15>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0001000000000000") (owner "Xilinx"))
+            )
+            (instance (rename LED1_OBUF_renamed_16 "LED1_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_0__rt_renamed_17 "Mcount_count_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename LED1_dpot_renamed_18 "LED1_dpot")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAA9AAAAAAAA") (owner "Xilinx"))
+            )
+            (instance (rename LED1_rstpot_renamed_19 "LED1_rstpot")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E2") (owner "Xilinx"))
+            )
+            (instance (rename LED1_renamed_20 "LED1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_1_rstpot_renamed_21 "count_1_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_1
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_0_rstpot_renamed_22 "count_0_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_0
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_2_rstpot_renamed_23 "count_2_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_2
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_3_rstpot_renamed_24 "count_3_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_3
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_4_rstpot_renamed_25 "count_4_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_4
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_5_rstpot_renamed_26 "count_5_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_5
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_6_rstpot_renamed_27 "count_6_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_6
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_7_rstpot_renamed_28 "count_7_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_7
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_8_rstpot_renamed_29 "count_8_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_8
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_9_rstpot_renamed_30 "count_9_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_9
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_10_rstpot_renamed_31 "count_10_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_10
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_11_rstpot_renamed_32 "count_11_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_11
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_12_rstpot_renamed_33 "count_12_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_12
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_13_rstpot_renamed_34 "count_13_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_13
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_14_rstpot_renamed_35 "count_14_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_14
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_15_rstpot_renamed_36 "count_15_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_15
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename CLK_BUFGP_renamed_37 "CLK_BUFGP")
+              (viewRef view_1 (cellRef BUFGP (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_1__INV_0 "Mcount_count_lut<1>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_2__INV_0 "Mcount_count_lut<2>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_3__INV_0 "Mcount_count_lut<3>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_4__INV_0 "Mcount_count_lut<4>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_5__INV_0 "Mcount_count_lut<5>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_6__INV_0 "Mcount_count_lut<6>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_7__INV_0 "Mcount_count_lut<7>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_8__INV_0 "Mcount_count_lut<8>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_9__INV_0 "Mcount_count_lut<9>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_10__INV_0 "Mcount_count_lut<10>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_11__INV_0 "Mcount_count_lut<11>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_12__INV_0 "Mcount_count_lut<12>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_13__INV_0 "Mcount_count_lut<13>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_14__INV_0 "Mcount_count_lut<14>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_15__INV_0 "Mcount_count_lut<15>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (net CLK_BUFGP
+              (joined
+                (portRef C (instanceRef LED1_renamed_20))
+                (portRef C (instanceRef count_1))
+                (portRef C (instanceRef count_0))
+                (portRef C (instanceRef count_2))
+                (portRef C (instanceRef count_3))
+                (portRef C (instanceRef count_4))
+                (portRef C (instanceRef count_5))
+                (portRef C (instanceRef count_6))
+                (portRef C (instanceRef count_7))
+                (portRef C (instanceRef count_8))
+                (portRef C (instanceRef count_9))
+                (portRef C (instanceRef count_10))
+                (portRef C (instanceRef count_11))
+                (portRef C (instanceRef count_12))
+                (portRef C (instanceRef count_13))
+                (portRef C (instanceRef count_14))
+                (portRef C (instanceRef count_15))
+                (portRef O (instanceRef CLK_BUFGP_renamed_37))
+              )
+            )
+            (net (rename count_15__ "count<15>")
+              (joined
+                (portRef I4 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef count_15))
+                (portRef I (instanceRef Mcount_count_lut_15__INV_0))
+                (portRef I0 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_14__ "count<14>")
+              (joined
+                (portRef I3 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef count_14))
+                (portRef I (instanceRef Mcount_count_lut_14__INV_0))
+                (portRef I1 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_13__ "count<13>")
+              (joined
+                (portRef I1 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef count_13))
+                (portRef I (instanceRef Mcount_count_lut_13__INV_0))
+                (portRef I3 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_12__ "count<12>")
+              (joined
+                (portRef I2 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef count_12))
+                (portRef I (instanceRef Mcount_count_lut_12__INV_0))
+                (portRef I2 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_11__ "count<11>")
+              (joined
+                (portRef I5 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_11))
+                (portRef I (instanceRef Mcount_count_lut_11__INV_0))
+              )
+            )
+            (net (rename count_10__ "count<10>")
+              (joined
+                (portRef I4 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_10))
+                (portRef I (instanceRef Mcount_count_lut_10__INV_0))
+              )
+            )
+            (net (rename count_9__ "count<9>")
+              (joined
+                (portRef I3 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_9))
+                (portRef I (instanceRef Mcount_count_lut_9__INV_0))
+              )
+            )
+            (net (rename count_8__ "count<8>")
+              (joined
+                (portRef I2 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_8))
+                (portRef I (instanceRef Mcount_count_lut_8__INV_0))
+              )
+            )
+            (net (rename count_7__ "count<7>")
+              (joined
+                (portRef I0 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_7))
+                (portRef I (instanceRef Mcount_count_lut_7__INV_0))
+              )
+            )
+            (net (rename count_6__ "count<6>")
+              (joined
+                (portRef I1 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_6))
+                (portRef I (instanceRef Mcount_count_lut_6__INV_0))
+              )
+            )
+            (net (rename count_5__ "count<5>")
+              (joined
+                (portRef I5 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_5))
+                (portRef I (instanceRef Mcount_count_lut_5__INV_0))
+              )
+            )
+            (net (rename count_4__ "count<4>")
+              (joined
+                (portRef I4 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_4))
+                (portRef I (instanceRef Mcount_count_lut_4__INV_0))
+              )
+            )
+            (net (rename count_3__ "count<3>")
+              (joined
+                (portRef I3 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_3))
+                (portRef I (instanceRef Mcount_count_lut_3__INV_0))
+              )
+            )
+            (net (rename count_2__ "count<2>")
+              (joined
+                (portRef I2 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_2))
+                (portRef I (instanceRef Mcount_count_lut_2__INV_0))
+              )
+            )
+            (net (rename count_1__ "count<1>")
+              (joined
+                (portRef I0 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_1))
+                (portRef I (instanceRef Mcount_count_lut_1__INV_0))
+              )
+            )
+            (net (rename count_0__ "count<0>")
+              (joined
+                (portRef I1 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef I0 (instanceRef Mcount_count_cy_0__rt_renamed_17))
+                (portRef Q (instanceRef count_0))
+              )
+            )
+            (net LED1_OBUF
+              (joined
+                (portRef I (instanceRef LED1_OBUF_renamed_16))
+                (portRef I0 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef LED1_renamed_20))
+                (portRef I0 (instanceRef LED1_rstpot_renamed_19))
+              )
+            )
+            (net (rename count_15__GND_1_o_equal_2_o "count[15]_GND_1_o_equal_2_o")
+              (joined
+                (portRef O (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+                (portRef I1 (instanceRef count_1_rstpot_renamed_21))
+                (portRef I1 (instanceRef count_0_rstpot_renamed_22))
+                (portRef I1 (instanceRef count_2_rstpot_renamed_23))
+                (portRef I1 (instanceRef count_3_rstpot_renamed_24))
+                (portRef I1 (instanceRef count_4_rstpot_renamed_25))
+                (portRef I1 (instanceRef count_5_rstpot_renamed_26))
+                (portRef I1 (instanceRef count_6_rstpot_renamed_27))
+                (portRef I1 (instanceRef count_7_rstpot_renamed_28))
+                (portRef I1 (instanceRef count_8_rstpot_renamed_29))
+                (portRef I1 (instanceRef count_9_rstpot_renamed_30))
+                (portRef I1 (instanceRef count_10_rstpot_renamed_31))
+                (portRef I1 (instanceRef count_11_rstpot_renamed_32))
+                (portRef I1 (instanceRef count_12_rstpot_renamed_33))
+                (portRef I1 (instanceRef count_13_rstpot_renamed_34))
+                (portRef I1 (instanceRef count_14_rstpot_renamed_35))
+                (portRef I1 (instanceRef count_15_rstpot_renamed_36))
+              )
+            )
+            (net N0
+              (joined
+                (portRef P (instanceRef XST_VCC))
+                (portRef CI (instanceRef Mcount_count_cy_0___renamed_0))
+                (portRef CI (instanceRef Mcount_count_xor_0__))
+                (portRef DI (instanceRef Mcount_count_cy_1___renamed_1))
+                (portRef DI (instanceRef Mcount_count_cy_2___renamed_2))
+                (portRef DI (instanceRef Mcount_count_cy_3___renamed_3))
+                (portRef DI (instanceRef Mcount_count_cy_4___renamed_4))
+                (portRef DI (instanceRef Mcount_count_cy_5___renamed_5))
+                (portRef DI (instanceRef Mcount_count_cy_6___renamed_6))
+                (portRef DI (instanceRef Mcount_count_cy_7___renamed_7))
+                (portRef DI (instanceRef Mcount_count_cy_8___renamed_8))
+                (portRef DI (instanceRef Mcount_count_cy_9___renamed_9))
+                (portRef DI (instanceRef Mcount_count_cy_10___renamed_10))
+                (portRef DI (instanceRef Mcount_count_cy_11___renamed_11))
+                (portRef DI (instanceRef Mcount_count_cy_12___renamed_12))
+                (portRef DI (instanceRef Mcount_count_cy_13___renamed_13))
+                (portRef DI (instanceRef Mcount_count_cy_14___renamed_14))
+              )
+            )
+            (net N1
+              (joined
+                (portRef G (instanceRef XST_GND))
+                (portRef DI (instanceRef Mcount_count_cy_0___renamed_0))
+              )
+            )
+            (net (rename Result_0__ "Result<0>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_0__))
+                (portRef I0 (instanceRef count_0_rstpot_renamed_22))
+              )
+            )
+            (net (rename Result_1__ "Result<1>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_1__))
+                (portRef I0 (instanceRef count_1_rstpot_renamed_21))
+              )
+            )
+            (net (rename Result_2__ "Result<2>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_2__))
+                (portRef I0 (instanceRef count_2_rstpot_renamed_23))
+              )
+            )
+            (net (rename Result_3__ "Result<3>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_3__))
+                (portRef I0 (instanceRef count_3_rstpot_renamed_24))
+              )
+            )
+            (net (rename Result_4__ "Result<4>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_4__))
+                (portRef I0 (instanceRef count_4_rstpot_renamed_25))
+              )
+            )
+            (net (rename Result_5__ "Result<5>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_5__))
+                (portRef I0 (instanceRef count_5_rstpot_renamed_26))
+              )
+            )
+            (net (rename Result_6__ "Result<6>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_6__))
+                (portRef I0 (instanceRef count_6_rstpot_renamed_27))
+              )
+            )
+            (net (rename Result_7__ "Result<7>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_7__))
+                (portRef I0 (instanceRef count_7_rstpot_renamed_28))
+              )
+            )
+            (net (rename Result_8__ "Result<8>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_8__))
+                (portRef I0 (instanceRef count_8_rstpot_renamed_29))
+              )
+            )
+            (net (rename Result_9__ "Result<9>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_9__))
+                (portRef I0 (instanceRef count_9_rstpot_renamed_30))
+              )
+            )
+            (net (rename Result_10__ "Result<10>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_10__))
+                (portRef I0 (instanceRef count_10_rstpot_renamed_31))
+              )
+            )
+            (net (rename Result_11__ "Result<11>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_11__))
+                (portRef I0 (instanceRef count_11_rstpot_renamed_32))
+              )
+            )
+            (net (rename Result_12__ "Result<12>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_12__))
+                (portRef I0 (instanceRef count_12_rstpot_renamed_33))
+              )
+            )
+            (net (rename Result_13__ "Result<13>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_13__))
+                (portRef I0 (instanceRef count_13_rstpot_renamed_34))
+              )
+            )
+            (net (rename Result_14__ "Result<14>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_14__))
+                (portRef I0 (instanceRef count_14_rstpot_renamed_35))
+              )
+            )
+            (net (rename Result_15__ "Result<15>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_15__))
+                (portRef I0 (instanceRef count_15_rstpot_renamed_36))
+              )
+            )
+            (net (rename Mcount_count_cy_0__ "Mcount_count_cy<0>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_0___renamed_0))
+                (portRef CI (instanceRef Mcount_count_cy_1___renamed_1))
+                (portRef CI (instanceRef Mcount_count_xor_1__))
+              )
+            )
+            (net (rename Mcount_count_lut_1__ "Mcount_count_lut<1>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_1___renamed_1))
+                (portRef LI (instanceRef Mcount_count_xor_1__))
+                (portRef O (instanceRef Mcount_count_lut_1__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_1__ "Mcount_count_cy<1>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_1___renamed_1))
+                (portRef CI (instanceRef Mcount_count_cy_2___renamed_2))
+                (portRef CI (instanceRef Mcount_count_xor_2__))
+              )
+            )
+            (net (rename Mcount_count_lut_2__ "Mcount_count_lut<2>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_2___renamed_2))
+                (portRef LI (instanceRef Mcount_count_xor_2__))
+                (portRef O (instanceRef Mcount_count_lut_2__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_2__ "Mcount_count_cy<2>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_2___renamed_2))
+                (portRef CI (instanceRef Mcount_count_cy_3___renamed_3))
+                (portRef CI (instanceRef Mcount_count_xor_3__))
+              )
+            )
+            (net (rename Mcount_count_lut_3__ "Mcount_count_lut<3>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_3___renamed_3))
+                (portRef LI (instanceRef Mcount_count_xor_3__))
+                (portRef O (instanceRef Mcount_count_lut_3__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_3__ "Mcount_count_cy<3>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_3___renamed_3))
+                (portRef CI (instanceRef Mcount_count_cy_4___renamed_4))
+                (portRef CI (instanceRef Mcount_count_xor_4__))
+              )
+            )
+            (net (rename Mcount_count_lut_4__ "Mcount_count_lut<4>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_4___renamed_4))
+                (portRef LI (instanceRef Mcount_count_xor_4__))
+                (portRef O (instanceRef Mcount_count_lut_4__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_4__ "Mcount_count_cy<4>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_4___renamed_4))
+                (portRef CI (instanceRef Mcount_count_cy_5___renamed_5))
+                (portRef CI (instanceRef Mcount_count_xor_5__))
+              )
+            )
+            (net (rename Mcount_count_lut_5__ "Mcount_count_lut<5>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_5___renamed_5))
+                (portRef LI (instanceRef Mcount_count_xor_5__))
+                (portRef O (instanceRef Mcount_count_lut_5__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_5__ "Mcount_count_cy<5>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_5___renamed_5))
+                (portRef CI (instanceRef Mcount_count_cy_6___renamed_6))
+                (portRef CI (instanceRef Mcount_count_xor_6__))
+              )
+            )
+            (net (rename Mcount_count_lut_6__ "Mcount_count_lut<6>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_6___renamed_6))
+                (portRef LI (instanceRef Mcount_count_xor_6__))
+                (portRef O (instanceRef Mcount_count_lut_6__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_6__ "Mcount_count_cy<6>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_6___renamed_6))
+                (portRef CI (instanceRef Mcount_count_cy_7___renamed_7))
+                (portRef CI (instanceRef Mcount_count_xor_7__))
+              )
+            )
+            (net (rename Mcount_count_lut_7__ "Mcount_count_lut<7>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_7___renamed_7))
+                (portRef LI (instanceRef Mcount_count_xor_7__))
+                (portRef O (instanceRef Mcount_count_lut_7__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_7__ "Mcount_count_cy<7>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_7___renamed_7))
+                (portRef CI (instanceRef Mcount_count_cy_8___renamed_8))
+                (portRef CI (instanceRef Mcount_count_xor_8__))
+              )
+            )
+            (net (rename Mcount_count_lut_8__ "Mcount_count_lut<8>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_8___renamed_8))
+                (portRef LI (instanceRef Mcount_count_xor_8__))
+                (portRef O (instanceRef Mcount_count_lut_8__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_8__ "Mcount_count_cy<8>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_8___renamed_8))
+                (portRef CI (instanceRef Mcount_count_cy_9___renamed_9))
+                (portRef CI (instanceRef Mcount_count_xor_9__))
+              )
+            )
+            (net (rename Mcount_count_lut_9__ "Mcount_count_lut<9>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_9___renamed_9))
+                (portRef LI (instanceRef Mcount_count_xor_9__))
+                (portRef O (instanceRef Mcount_count_lut_9__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_9__ "Mcount_count_cy<9>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_9___renamed_9))
+                (portRef CI (instanceRef Mcount_count_cy_10___renamed_10))
+                (portRef CI (instanceRef Mcount_count_xor_10__))
+              )
+            )
+            (net (rename Mcount_count_lut_10__ "Mcount_count_lut<10>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_10___renamed_10))
+                (portRef LI (instanceRef Mcount_count_xor_10__))
+                (portRef O (instanceRef Mcount_count_lut_10__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_10__ "Mcount_count_cy<10>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_10___renamed_10))
+                (portRef CI (instanceRef Mcount_count_cy_11___renamed_11))
+                (portRef CI (instanceRef Mcount_count_xor_11__))
+              )
+            )
+            (net (rename Mcount_count_lut_11__ "Mcount_count_lut<11>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_11___renamed_11))
+                (portRef LI (instanceRef Mcount_count_xor_11__))
+                (portRef O (instanceRef Mcount_count_lut_11__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_11__ "Mcount_count_cy<11>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_11___renamed_11))
+                (portRef CI (instanceRef Mcount_count_cy_12___renamed_12))
+                (portRef CI (instanceRef Mcount_count_xor_12__))
+              )
+            )
+            (net (rename Mcount_count_lut_12__ "Mcount_count_lut<12>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_12___renamed_12))
+                (portRef LI (instanceRef Mcount_count_xor_12__))
+                (portRef O (instanceRef Mcount_count_lut_12__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_12__ "Mcount_count_cy<12>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_12___renamed_12))
+                (portRef CI (instanceRef Mcount_count_cy_13___renamed_13))
+                (portRef CI (instanceRef Mcount_count_xor_13__))
+              )
+            )
+            (net (rename Mcount_count_lut_13__ "Mcount_count_lut<13>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_13___renamed_13))
+                (portRef LI (instanceRef Mcount_count_xor_13__))
+                (portRef O (instanceRef Mcount_count_lut_13__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_13__ "Mcount_count_cy<13>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_13___renamed_13))
+                (portRef CI (instanceRef Mcount_count_cy_14___renamed_14))
+                (portRef CI (instanceRef Mcount_count_xor_14__))
+              )
+            )
+            (net (rename Mcount_count_lut_14__ "Mcount_count_lut<14>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_14___renamed_14))
+                (portRef LI (instanceRef Mcount_count_xor_14__))
+                (portRef O (instanceRef Mcount_count_lut_14__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_14__ "Mcount_count_cy<14>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_14___renamed_14))
+                (portRef CI (instanceRef Mcount_count_xor_15__))
+              )
+            )
+            (net (rename Mcount_count_lut_15__ "Mcount_count_lut<15>")
+              (joined
+                (portRef LI (instanceRef Mcount_count_xor_15__))
+                (portRef O (instanceRef Mcount_count_lut_15__INV_0))
+              )
+            )
+            (net (rename count_15__GND_1_o_equal_2_o_15__ "count[15]_GND_1_o_equal_2_o<15>")
+              (joined
+                (portRef O (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef I5 (instanceRef LED1_dpot_renamed_18))
+                (portRef I4 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_15__GND_1_o_equal_2_o_15_1 "count[15]_GND_1_o_equal_2_o<15>1")
+              (joined
+                (portRef O (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef I5 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+                (portRef I1 (instanceRef LED1_rstpot_renamed_19))
+              )
+            )
+            (net CLK
+              (joined
+                (portRef CLK)
+                (portRef I (instanceRef CLK_BUFGP_renamed_37))
+              )
+            )
+            (net LED1
+              (joined
+                (portRef LED1)
+                (portRef O (instanceRef LED1_OBUF_renamed_16))
+              )
+            )
+            (net (rename Mcount_count_cy_0__rt "Mcount_count_cy<0>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_0__rt_renamed_17))
+                (portRef S (instanceRef Mcount_count_cy_0___renamed_0))
+                (portRef LI (instanceRef Mcount_count_xor_0__))
+              )
+            )
+            (net LED1_dpot
+              (joined
+                (portRef O (instanceRef LED1_dpot_renamed_18))
+                (portRef I2 (instanceRef LED1_rstpot_renamed_19))
+              )
+            )
+            (net LED1_rstpot
+              (joined
+                (portRef O (instanceRef LED1_rstpot_renamed_19))
+                (portRef D (instanceRef LED1_renamed_20))
+              )
+            )
+            (net count_1_rstpot
+              (joined
+                (portRef O (instanceRef count_1_rstpot_renamed_21))
+                (portRef D (instanceRef count_1))
+              )
+            )
+            (net count_0_rstpot
+              (joined
+                (portRef O (instanceRef count_0_rstpot_renamed_22))
+                (portRef D (instanceRef count_0))
+              )
+            )
+            (net count_2_rstpot
+              (joined
+                (portRef O (instanceRef count_2_rstpot_renamed_23))
+                (portRef D (instanceRef count_2))
+              )
+            )
+            (net count_3_rstpot
+              (joined
+                (portRef O (instanceRef count_3_rstpot_renamed_24))
+                (portRef D (instanceRef count_3))
+              )
+            )
+            (net count_4_rstpot
+              (joined
+                (portRef O (instanceRef count_4_rstpot_renamed_25))
+                (portRef D (instanceRef count_4))
+              )
+            )
+            (net count_5_rstpot
+              (joined
+                (portRef O (instanceRef count_5_rstpot_renamed_26))
+                (portRef D (instanceRef count_5))
+              )
+            )
+            (net count_6_rstpot
+              (joined
+                (portRef O (instanceRef count_6_rstpot_renamed_27))
+                (portRef D (instanceRef count_6))
+              )
+            )
+            (net count_7_rstpot
+              (joined
+                (portRef O (instanceRef count_7_rstpot_renamed_28))
+                (portRef D (instanceRef count_7))
+              )
+            )
+            (net count_8_rstpot
+              (joined
+                (portRef O (instanceRef count_8_rstpot_renamed_29))
+                (portRef D (instanceRef count_8))
+              )
+            )
+            (net count_9_rstpot
+              (joined
+                (portRef O (instanceRef count_9_rstpot_renamed_30))
+                (portRef D (instanceRef count_9))
+              )
+            )
+            (net count_10_rstpot
+              (joined
+                (portRef O (instanceRef count_10_rstpot_renamed_31))
+                (portRef D (instanceRef count_10))
+              )
+            )
+            (net count_11_rstpot
+              (joined
+                (portRef O (instanceRef count_11_rstpot_renamed_32))
+                (portRef D (instanceRef count_11))
+              )
+            )
+            (net count_12_rstpot
+              (joined
+                (portRef O (instanceRef count_12_rstpot_renamed_33))
+                (portRef D (instanceRef count_12))
+              )
+            )
+            (net count_13_rstpot
+              (joined
+                (portRef O (instanceRef count_13_rstpot_renamed_34))
+                (portRef D (instanceRef count_13))
+              )
+            )
+            (net count_14_rstpot
+              (joined
+                (portRef O (instanceRef count_14_rstpot_renamed_35))
+                (portRef D (instanceRef count_14))
+              )
+            )
+            (net count_15_rstpot
+              (joined
+                (portRef O (instanceRef count_15_rstpot_renamed_36))
+                (portRef D (instanceRef count_15))
+              )
+            )
+          )
+      )
+    )
+  )
+
+  (design led
+    (cellRef led
+      (libraryRef led_lib)
+    )
+    (property PART (string "xc6slx9-2-tqg144") (owner "Xilinx"))
+  )
+)
+
diff --git a/planAhead_run_4/FPGA-led-lights.data/constrs_1/fileset.xml b/planAhead_run_4/FPGA-led-lights.data/constrs_1/fileset.xml
new file mode 100644
index 0000000..27cbdc8
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/constrs_1/fileset.xml
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../../../Downloads/BPC3011-Papilio_Pro-general.ucf">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PPRDIR/../../../Downloads/BPC3011-Papilio_Pro-general.ucf"/>
+      <Option Name="ConstrsType" Val="UCF"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_4/FPGA-led-lights.data/runs/impl_1.psg b/planAhead_run_4/FPGA-led-lights.data/runs/impl_1.psg
new file mode 100644
index 0000000..147f3a9
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/runs/impl_1.psg
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+	<StratHandle Name="ISE Defaults" Flow="ISE14">
+		<Desc>ISE Defaults, including packing registers in IOs off</Desc>
+	</StratHandle>
+	<Step Id="ngdbuild">
+	</Step>
+	<Step Id="map">
+		<Option Id="FFPackEnum">3</Option>
+	</Step>
+	<Step Id="par">
+	</Step>
+	<Step Id="trce">
+	</Step>
+	<Step Id="xdl">
+	</Step>
+	<Step Id="bitgen">
+	</Step>
+</Strategy>
+
diff --git a/planAhead_run_4/FPGA-led-lights.data/runs/runs.xml b/planAhead_run_4/FPGA-led-lights.data/runs/runs.xml
new file mode 100644
index 0000000..7708ac8
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/runs/runs.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="8">
+	<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx9tqg144-2" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/>
+</Runs>
+
diff --git a/planAhead_run_4/FPGA-led-lights.data/sim_1/fileset.xml b/planAhead_run_4/FPGA-led-lights.data/sim_1/fileset.xml
new file mode 100644
index 0000000..65babe3
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/sim_1/fileset.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+      <Option Name="SrcSet" Val="sources_1"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_4/FPGA-led-lights.data/sources_1/fileset.xml b/planAhead_run_4/FPGA-led-lights.data/sources_1/fileset.xml
new file mode 100644
index 0000000..ddc517f
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/sources_1/fileset.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="EDIFSrcs"/>
+    <File Path="$PPRDIR/../led.ngc">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="GateLvl"/>
+      <Option Name="GateLvlMode" Val="EDIF"/>
+      <Option Name="TopFile" Val="$PPRDIR/../led.ngc"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_4/FPGA-led-lights.data/wt/java_command_handlers.wdf b/planAhead_run_4/FPGA-led-lights.data/wt/java_command_handlers.wdf
new file mode 100644
index 0000000..90b0b33
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/wt/java_command_handlers.wdf
@@ -0,0 +1,4 @@
+version:1
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e736372697074:31:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:32:00:00
+eof:2778578561
diff --git a/planAhead_run_4/FPGA-led-lights.data/wt/project.wpc b/planAhead_run_4/FPGA-led-lights.data/wt/project.wpc
new file mode 100644
index 0000000..5fed558
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/wt/project.wpc
@@ -0,0 +1,4 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+6d6f64655f636f756e7465727c4953454d6f6465:1
+eof:
diff --git a/planAhead_run_4/FPGA-led-lights.data/wt/webtalk_pa.xml b/planAhead_run_4/FPGA-led-lights.data/wt/webtalk_pa.xml
new file mode 100644
index 0000000..0ab2f73
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/wt/webtalk_pa.xml
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Tue Feb 21 21:53:14 2017">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="5839cde962314e60853ae32f9ffcb4a0" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="GateLvl" type="DesignMode"/>
+<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="RunScript" value="1" type="JavaHandler"/>
+<property name="ShowView" value="2" type="JavaHandler"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="0" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
+<property name="ISEMode" value="7" type="ISEMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/planAhead_run_4/FPGA-led-lights.ppr b/planAhead_run_4/FPGA-led-lights.ppr
new file mode 100644
index 0000000..42d291d
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.ppr
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<!--Product Version: PlanAhead v14.7 (64-bit)-->
+<Project Version="4" Minor="36">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<FileSet Dir="sim_1" File="fileset.xml"/>
+	<RunSet Dir="runs" File="runs.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Id" Val="903fcee33e314607aca91ab5aed60bb7"/>
+		<Option Name="Part" Val="xc6slx9tqg144-2"/>
+		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+		<Option Name="TargetLanguage" Val="Verilog"/>
+		<Option Name="TargetSimulator" Val="ISim"/>
+		<Option Name="Board" Val=""/>
+		<Option Name="SourceMgmtMode" Val="All"/>
+		<Option Name="ActiveSimSet" Val="sim_1"/>
+		<Option Name="CxlOverwriteLibs" Val="1"/>
+		<Option Name="CxlFuncsim" Val="1"/>
+		<Option Name="CxlTimesim" Val="1"/>
+		<Option Name="CxlCore" Val="1"/>
+		<Option Name="CxlEdk" Val="0"/>
+		<Option Name="CxlExcludeCores" Val="1"/>
+		<Option Name="CxlExcludeSubLibs" Val="0"/>
+	</Config>
+</Project>
+
diff --git a/planAhead_run_4/planAhead.jou b/planAhead_run_4/planAhead.jou
new file mode 100644
index 0000000..236855b
--- /dev/null
+++ b/planAhead_run_4/planAhead.jou
@@ -0,0 +1,14 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Start of session at: Tue Feb 21 21:49:52 2017
+# Process ID: 24218
+# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4/planAhead.log
+# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4/planAhead.jou
+#-----------------------------------------------------------
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNcd.tcl
+add wave clock enable
+create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
+add
+run
diff --git a/planAhead_run_4/planAhead.log b/planAhead_run_4/planAhead.log
new file mode 100644
index 0000000..00270f3
--- /dev/null
+++ b/planAhead_run_4/planAhead.log
@@ -0,0 +1,96 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Start of session at: Tue Feb 21 21:49:52 2017
+# Process ID: 24218
+# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4/planAhead.log
+# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4/planAhead.jou
+#-----------------------------------------------------------
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNcd.tcl
+# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4" -part xc6slx9tqg144-2
+# set srcset [get_property srcset [current_run -impl]]
+# set_property design_mode GateLvl $srcset
+# set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} }
+# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1'
+# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+# link_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to project part: xc6slx9tqg144-2
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design led.ngc ...
+WARNING:NetListWriters:298 - No output is written to led.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file led.edif ...
+ngc2edif: Total memory usage is 103540 kilobytes
+
+Parsing EDIF File [./planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+Finished Parsing EDIF File [./planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
+Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
+Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
+Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
+Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 1 instances were transformed.
+  BUFGP => BUFGP (IBUF, BUFG): 1 instances
+
+Phase 0 | Netlist Checksum: 23693229
+link_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2864.305 ; gain = 189.508
+# read_xdl -file "/home/yannherklotz/Github/FPGA-led-lights/led.ncd"
+Release 14.7 - xdl P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
+Loading device for application Rf_Device from file '6slx9.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
+   "led" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
+Successfully converted design '/home/yannherklotz/Github/FPGA-led-lights/led.ncd' to '/home/yannherklotz/Github/FPGA-led-lights/led.xdl'.
+INFO: [Designutils 20-669] Parsing Placement File : /home/yannherklotz/Github/FPGA-led-lights/led.ncd
+INFO: [Designutils 20-658] Finished Parsing Placement File : /home/yannherklotz/Github/FPGA-led-lights/led.ncd
+INFO: [Designutils 20-671] Placed 87 instances
+read_xdl: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 2864.305 ; gain = 0.000
+# if {[catch {read_twx -name results_1 -file "/home/yannherklotz/Github/FPGA-led-lights/led.twx"} eInfo]} {
+#    puts "WARNING: there was a problem importing \"/home/yannherklotz/Github/FPGA-led-lights/led.twx\": $eInfo"
+# }
+add wave clock enable
+invalid command name "add"
+ambiguous command name "add": add_cells_to_pblock add_files
+create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
+WARNING: [PlanAhead 12-584] No ports matched 'CLOCK_50'.
+invalid command name "create_clock"
+add
+invalid command name "add"
+ambiguous command name "add": add_cells_to_pblock add_files
+run
+invalid command name "run"
+exit
+ERROR: [#UNDEF] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+ (See /home/yannherklotz/Github/FPGA-led-lights/planAhead_pid24218.debug)
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 21:53:15 2017...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/planAhead_run_4/planAhead_run.log b/planAhead_run_4/planAhead_run.log
new file mode 100644
index 0000000..39a91d8
--- /dev/null
+++ b/planAhead_run_4/planAhead_run.log
@@ -0,0 +1,105 @@
+
+****** PlanAhead v14.7 (64-bit)
+  **** Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNcd.tcl
+# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4" -part xc6slx9tqg144-2
+# set srcset [get_property srcset [current_run -impl]]
+# set_property design_mode GateLvl $srcset
+# set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} }
+# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1'
+# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+# link_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to project part: xc6slx9tqg144-2
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design led.ngc ...
+WARNING:NetListWriters:298 - No output is written to led.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file led.edif ...
+ngc2edif: Total memory usage is 103540 kilobytes
+
+Parsing EDIF File [./planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+Finished Parsing EDIF File [./planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
+Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
+Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
+Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
+Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 1 instances were transformed.
+  BUFGP => BUFGP (IBUF, BUFG): 1 instances
+
+Phase 0 | Netlist Checksum: 23693229
+link_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2864.305 ; gain = 189.508
+# read_xdl -file "/home/yannherklotz/Github/FPGA-led-lights/led.ncd"
+Release 14.7 - xdl P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
+Loading device for application Rf_Device from file '6slx9.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
+   "led" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
+Successfully converted design '/home/yannherklotz/Github/FPGA-led-lights/led.ncd' to '/home/yannherklotz/Github/FPGA-led-lights/led.xdl'.
+INFO: [Designutils 20-669] Parsing Placement File : /home/yannherklotz/Github/FPGA-led-lights/led.ncd
+INFO: [Designutils 20-658] Finished Parsing Placement File : /home/yannherklotz/Github/FPGA-led-lights/led.ncd
+INFO: [Designutils 20-671] Placed 87 instances
+read_xdl: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 2864.305 ; gain = 0.000
+# if {[catch {read_twx -name results_1 -file "/home/yannherklotz/Github/FPGA-led-lights/led.twx"} eInfo]} {
+#    puts "WARNING: there was a problem importing \"/home/yannherklotz/Github/FPGA-led-lights/led.twx\": $eInfo"
+# }
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+add wave clock enable
+invalid command name "add"
+ambiguous command name "add": add_cells_to_pblock add_files
+create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
+WARNING: [PlanAhead 12-584] No ports matched 'CLOCK_50'.
+invalid command name "create_clock"
+add
+invalid command name "add"
+ambiguous command name "add": add_cells_to_pblock add_files
+run
+invalid command name "run"
+exit
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 21:53:15 2017...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/usage_statistics_webtalk.html b/usage_statistics_webtalk.html
new file mode 100644
index 0000000..0160d16
--- /dev/null
+++ b/usage_statistics_webtalk.html
@@ -0,0 +1,943 @@
+<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>&nbsp;<BR><HR>&nbsp;<BR>
+<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Software Version and Target Device</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
+<TD><xtag-property name="ProductVersion">ISE:14.7</xtag-property><xtag-property name="ProductConfiguration"> (WebPack)</xtag-property><xtag-property name="BuildVersion"> - P.20131013</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Target Family:</B></TD>
+<TD><xtag-property name="TargetFamily">Spartan6</xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>OS Platform:</B></TD>
+<TD><xtag-property name="OSPlatform">LIN64</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD><xtag-property name="TargetDevice">xc6slx9</xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
+<TD><xtag-property name="RandomID">5b396c39235244c09f945ee08d948a14</xtag-property>.<xtag-property name="ProjectID">8C4A34387ED46BFEECE9D369B6F8AAAE</xtag-property>.<xtag-property name="ProjectIteration">19</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
+<TD><xtag-property name="TargetPackage">tqg144</xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Registration ID</B></TD>
+<TD><xtag-property name="RegistrationID">211291888_0_0_214</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Target Speed:</B></TD>
+<TD><xtag-property name="TargetSpeed">-2</xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
+<TD><xtag-property name="Date Generated">2017-02-21T22:17:09</xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
+<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
+</TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="UserEnvironment">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>User Environment</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>unknown</xtag-env-param-value></xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>unknown</xtag-env-param-value></xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz</xtag-env-param-value></xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3099.957 MHz</xtag-env-param-value></xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>unknown</xtag-env-param-value></xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>unknown</xtag-env-param-value></xtag-property></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz</xtag-env-param-value></xtag-property></TD>
+<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
+<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3100.122 MHz</xtag-env-param-value></xtag-property></TD>
+</TR>
+</xtag-section></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Device Usage Statistics</B></TD></TR>
+<TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Macro Statistics</B></TD><TD><B>Miscellaneous Statistics</B></TD><TD><B>Net Statistics</B></TD><TD><B>Site Usage</B></TD></TR><TR VALIGN=TOP>
+<xtag-section name="MacroStatistics">
+<TD>
+<xtag-group><xtag-group-name name="Counters=1">Counters=1</xtag-group-name>
+<UL>
+<LI><xtag-item1>27-bit down counter=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="Registers=1">Registers=1</xtag-group-name>
+<UL>
+<LI><xtag-item1>Flip-Flops=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+</TD>
+</xtag-section>
+<xtag-section name="DesignStatistics">
+<TD>
+<xtag-group><xtag-group-name name="MiscellaneousStatistics">MiscellaneousStatistics</xtag-group-name>
+<UL>
+<LI><xtag-item1>AGG_BONDED_IO=2</xtag-item1></LI>
+<LI><xtag-item1>AGG_IO=2</xtag-item1></LI>
+<LI><xtag-item1>AGG_LOCED_IO=2</xtag-item1></LI>
+<LI><xtag-item1>AGG_SLICE=15</xtag-item1></LI>
+<LI><xtag-item1>NUM_BONDED_IOB=2</xtag-item1></LI>
+<LI><xtag-item1>NUM_BSFULL=25</xtag-item1></LI>
+<LI><xtag-item1>NUM_BSLUTONLY=32</xtag-item1></LI>
+<LI><xtag-item1>NUM_BSUSED=57</xtag-item1></LI>
+<LI><xtag-item1>NUM_BUFG=1</xtag-item1></LI>
+<LI><xtag-item1>NUM_LOCED_IOB=2</xtag-item1></LI>
+<LI><xtag-item1>NUM_LOGIC_O5ANDO6=22</xtag-item1></LI>
+<LI><xtag-item1>NUM_LOGIC_O5ONLY=1</xtag-item1></LI>
+<LI><xtag-item1>NUM_LOGIC_O6ONLY=34</xtag-item1></LI>
+<LI><xtag-item1>NUM_LUT_RT_O6=1</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICEL=6</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICEX=9</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICE_CARRY4=6</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICE_CONTROLSET=1</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICE_CYINIT=81</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICE_FF=25</xtag-item1></LI>
+<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=7</xtag-item1></LI>
+<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=7</xtag-item1></LI>
+</UL>
+</xtag-group>
+</TD>
+<TD>
+<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
+<UL>
+<LI><xtag-item1>NumNets_Active=66</xtag-item1></LI>
+<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=2</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=7</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=8</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=41</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_GENERIC=2</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=10</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_INPUT=6</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=197</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=60</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=66</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=1</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=17</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_PINFEED=207</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_QUAD=7</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Active_SINGLE=76</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=6</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=23</xtag-item1></LI>
+<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=23</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
+<UL>
+<LI><xtag-item1>BUFG-BUFGMUX=1</xtag-item1></LI>
+<LI><xtag-item1>IOB-IOBM=1</xtag-item1></LI>
+<LI><xtag-item1>IOB-IOBS=1</xtag-item1></LI>
+<LI><xtag-item1>SLICEL-SLICEM=6</xtag-item1></LI>
+<LI><xtag-item1>SLICEX-SLICEL=1</xtag-item1></LI>
+<LI><xtag-item1>SLICEX-SLICEM=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+</TD>
+</xtag-section>
+<xtag-section name="DeviceUsage">
+<TD>
+<xtag-group><xtag-group-name name="SiteSummary">SiteSummary</xtag-group-name>
+<UL>
+<LI><xtag-item2>BUFG=1</xtag-item2></LI>
+<LI><xtag-item2>BUFG_BUFG=1</xtag-item2></LI>
+<LI><xtag-item2>CARRY4=6</xtag-item2></LI>
+<LI><xtag-item2>HARD1=1</xtag-item2></LI>
+<LI><xtag-item2>IOB=2</xtag-item2></LI>
+<LI><xtag-item2>IOB_IMUX=1</xtag-item2></LI>
+<LI><xtag-item2>IOB_INBUF=1</xtag-item2></LI>
+<LI><xtag-item2>IOB_OUTBUF=1</xtag-item2></LI>
+<LI><xtag-item2>LUT5=23</xtag-item2></LI>
+<LI><xtag-item2>LUT6=57</xtag-item2></LI>
+<LI><xtag-item2>PAD=2</xtag-item2></LI>
+<LI><xtag-item2>REG_SR=25</xtag-item2></LI>
+<LI><xtag-item2>SLICEL=6</xtag-item2></LI>
+<LI><xtag-item2>SLICEX=9</xtag-item2></LI>
+</UL>
+</xtag-group>
+</TD>
+</xtag-section>
+</TR></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Configuration Data</B></TD></TR><TR VALIGN=TOP>
+<xtag-section name="ReportConfigData">
+<TD>
+<xtag-group><xtag-group-name name="BUFGMUX">BUFGMUX</xtag-group-name>
+<UL>
+<LI><xtag-item3>S=[S_INV:1] [S:0]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="BUFGMUX_GCLKMUX">BUFGMUX_GCLKMUX</xtag-group-name>
+<UL>
+<LI><xtag-item3>DISABLE_ATTR=[LOW:1]</xtag-item3></LI>
+<LI><xtag-item3>S=[S_INV:1] [S:0]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IBUF_PAD">IBUF_PAD</xtag-group-name>
+<UL>
+<LI><xtag-item3>IOATTRBOX=[LVTTL:1]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
+<UL>
+<LI><xtag-item3>O1=[O1_INV:0] [O1:1]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
+<UL>
+<LI><xtag-item3>DRIVEATTRBOX=[8:1]</xtag-item3></LI>
+<LI><xtag-item3>SLEW=[SLOW:1]</xtag-item3></LI>
+<LI><xtag-item3>SUSPEND=[3STATE:1]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB_PAD">IOB_PAD</xtag-group-name>
+<UL>
+<LI><xtag-item3>DRIVEATTRBOX=[8:1]</xtag-item3></LI>
+<LI><xtag-item3>IOATTRBOX=[LVTTL:1]</xtag-item3></LI>
+<LI><xtag-item3>SLEW=[SLOW:1]</xtag-item3></LI>
+</UL>
+</TD>
+<TD>
+</xtag-group>
+<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
+<UL>
+<LI><xtag-item3>CK=[CK:25] [CK_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>LATCH_OR_FF=[FF:25]</xtag-item3></LI>
+<LI><xtag-item3>SRINIT=[SRINIT0:18] [SRINIT1:7]</xtag-item3></LI>
+<LI><xtag-item3>SYNC_ATTR=[ASYNC:25]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
+<UL>
+<LI><xtag-item3>BX=[BX_INV:0] [BX:1]</xtag-item3></LI>
+<LI><xtag-item3>BY=[BY:0] [BY_INV:1]</xtag-item3></LI>
+<LI><xtag-item3>CE=[CE:1] [CE_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>CIN=[CIN_INV:0] [CIN:7]</xtag-item3></LI>
+<LI><xtag-item3>CLK=[CLK:9] [CLK_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>SR=[SR:8] [SR_INV:0]</xtag-item3></LI>
+</UL>
+</TD>
+<TD>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_CYMUXF">SLICEL_CYMUXF</xtag-group-name>
+<UL>
+<LI><xtag-item3>0=[0:8] [0_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>1=[1_INV:0] [1:8]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_CYMUXG">SLICEL_CYMUXG</xtag-group-name>
+<UL>
+<LI><xtag-item3>0=[0:7] [0_INV:0]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_FFX">SLICEL_FFX</xtag-group-name>
+<UL>
+<LI><xtag-item3>CK=[CK:8] [CK_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>D=[D:8] [D_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>FFX_INIT_ATTR=[INIT0:3] [INIT1:5]</xtag-item3></LI>
+<LI><xtag-item3>FFX_SR_ATTR=[SRLOW:3] [SRHIGH:5]</xtag-item3></LI>
+<LI><xtag-item3>LATCH_OR_FF=[FF:8]</xtag-item3></LI>
+<LI><xtag-item3>SR=[SR:8] [SR_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>SYNC_ATTR=[SYNC:8]</xtag-item3></LI>
+</UL>
+</TD>
+<TD>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_FFY">SLICEL_FFY</xtag-group-name>
+<UL>
+<LI><xtag-item3>CE=[CE:1] [CE_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>CK=[CK:9] [CK_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>D=[D:8] [D_INV:1]</xtag-item3></LI>
+<LI><xtag-item3>FFY_INIT_ATTR=[INIT0:5] [INIT1:4]</xtag-item3></LI>
+<LI><xtag-item3>FFY_SR_ATTR=[SRLOW:5] [SRHIGH:4]</xtag-item3></LI>
+<LI><xtag-item3>LATCH_OR_FF=[FF:9]</xtag-item3></LI>
+<LI><xtag-item3>SR=[SR:8] [SR_INV:0]</xtag-item3></LI>
+<LI><xtag-item3>SYNC_ATTR=[ASYNC:1] [SYNC:8]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_XORF">SLICEL_XORF</xtag-group-name>
+<UL>
+<LI><xtag-item3>1=[1_INV:0] [1:8]</xtag-item3></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
+<UL>
+<LI><xtag-item3>CLK=[CLK:8] [CLK_INV:0]</xtag-item3></LI>
+</UL>
+</TD>
+<TD>
+</xtag-group>
+</TD>
+</xtag-section>
+</TR></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Pin Data</B></TD></TR><TR VALIGN=TOP>
+<xtag-section name="ReportConfigData">
+<TD>
+<xtag-group><xtag-group-name name="BUFG">BUFG</xtag-group-name>
+<UL>
+<LI><xtag-item1>I0=1</xtag-item1></LI>
+<LI><xtag-item1>O=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="BUFGMUX">BUFGMUX</xtag-group-name>
+<UL>
+<LI><xtag-item1>I0=1</xtag-item1></LI>
+<LI><xtag-item1>O=1</xtag-item1></LI>
+<LI><xtag-item1>S=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="BUFGMUX_GCLKMUX">BUFGMUX_GCLKMUX</xtag-group-name>
+<UL>
+<LI><xtag-item1>I0=1</xtag-item1></LI>
+<LI><xtag-item1>OUT=1</xtag-item1></LI>
+<LI><xtag-item1>S=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="BUFGMUX_GCLK_BUFFER">BUFGMUX_GCLK_BUFFER</xtag-group-name>
+<UL>
+<LI><xtag-item1>IN=1</xtag-item1></LI>
+<LI><xtag-item1>OUT=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="BUFG_BUFG">BUFG_BUFG</xtag-group-name>
+<UL>
+<LI><xtag-item1>I0=1</xtag-item1></LI>
+<LI><xtag-item1>O=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name>
+<UL>
+<LI><xtag-item1>CIN=5</xtag-item1></LI>
+<LI><xtag-item1>CO3=5</xtag-item1></LI>
+<LI><xtag-item1>CYINIT=1</xtag-item1></LI>
+<LI><xtag-item1>DI0=6</xtag-item1></LI>
+<LI><xtag-item1>DI1=6</xtag-item1></LI>
+<LI><xtag-item1>DI2=6</xtag-item1></LI>
+<LI><xtag-item1>DI3=5</xtag-item1></LI>
+<LI><xtag-item1>O0=6</xtag-item1></LI>
+<LI><xtag-item1>O1=6</xtag-item1></LI>
+<LI><xtag-item1>O2=6</xtag-item1></LI>
+<LI><xtag-item1>O3=6</xtag-item1></LI>
+<LI><xtag-item1>S0=6</xtag-item1></LI>
+<LI><xtag-item1>S1=6</xtag-item1></LI>
+<LI><xtag-item1>S2=6</xtag-item1></LI>
+<LI><xtag-item1>S3=6</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="HARD1">HARD1</xtag-group-name>
+<UL>
+<LI><xtag-item1>1=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IBUF">IBUF</xtag-group-name>
+<UL>
+<LI><xtag-item1>I=1</xtag-item1></LI>
+<LI><xtag-item1>PAD=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IBUF_INBUF">IBUF_INBUF</xtag-group-name>
+<UL>
+<LI><xtag-item1>IN=1</xtag-item1></LI>
+<LI><xtag-item1>OUT=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IBUF_PAD">IBUF_PAD</xtag-group-name>
+<UL>
+<LI><xtag-item1>PAD=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
+<UL>
+<LI><xtag-item1>I=1</xtag-item1></LI>
+<LI><xtag-item1>O=1</xtag-item1></LI>
+<LI><xtag-item1>PAD=2</xtag-item1></LI>
+</UL>
+</TD>
+<TD>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB_IMUX">IOB_IMUX</xtag-group-name>
+<UL>
+<LI><xtag-item1>I=1</xtag-item1></LI>
+<LI><xtag-item1>OUT=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB_INBUF">IOB_INBUF</xtag-group-name>
+<UL>
+<LI><xtag-item1>OUT=1</xtag-item1></LI>
+<LI><xtag-item1>PAD=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
+<UL>
+<LI><xtag-item1>IN=1</xtag-item1></LI>
+<LI><xtag-item1>OUT=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="IOB_PAD">IOB_PAD</xtag-group-name>
+<UL>
+<LI><xtag-item1>PAD=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
+<UL>
+<LI><xtag-item1>O5=23</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
+<UL>
+<LI><xtag-item1>A1=8</xtag-item1></LI>
+<LI><xtag-item1>A2=33</xtag-item1></LI>
+<LI><xtag-item1>A3=33</xtag-item1></LI>
+<LI><xtag-item1>A4=33</xtag-item1></LI>
+<LI><xtag-item1>A5=56</xtag-item1></LI>
+<LI><xtag-item1>A6=57</xtag-item1></LI>
+<LI><xtag-item1>O6=57</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="PAD">PAD</xtag-group-name>
+<UL>
+<LI><xtag-item1>PAD=2</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
+<UL>
+<LI><xtag-item1>CK=25</xtag-item1></LI>
+<LI><xtag-item1>D=25</xtag-item1></LI>
+<LI><xtag-item1>Q=25</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
+<UL>
+<LI><xtag-item1>A5=6</xtag-item1></LI>
+<LI><xtag-item1>A6=6</xtag-item1></LI>
+<LI><xtag-item1>AMUX=6</xtag-item1></LI>
+<LI><xtag-item1>B5=6</xtag-item1></LI>
+<LI><xtag-item1>B6=6</xtag-item1></LI>
+<LI><xtag-item1>BMUX=6</xtag-item1></LI>
+<LI><xtag-item1>C5=6</xtag-item1></LI>
+<LI><xtag-item1>C6=6</xtag-item1></LI>
+<LI><xtag-item1>CIN=5</xtag-item1></LI>
+<LI><xtag-item1>CMUX=6</xtag-item1></LI>
+<LI><xtag-item1>COUT=5</xtag-item1></LI>
+<LI><xtag-item1>D5=5</xtag-item1></LI>
+<LI><xtag-item1>D6=6</xtag-item1></LI>
+<LI><xtag-item1>DMUX=6</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_C1VDD">SLICEL_C1VDD</xtag-group-name>
+<UL>
+<LI><xtag-item1>1=7</xtag-item1></LI>
+</UL>
+</TD>
+<TD>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_C2VDD">SLICEL_C2VDD</xtag-group-name>
+<UL>
+<LI><xtag-item1>1=7</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_CYMUXF">SLICEL_CYMUXF</xtag-group-name>
+<UL>
+<LI><xtag-item1>0=8</xtag-item1></LI>
+<LI><xtag-item1>1=8</xtag-item1></LI>
+<LI><xtag-item1>OUT=8</xtag-item1></LI>
+<LI><xtag-item1>S0=8</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_CYMUXG">SLICEL_CYMUXG</xtag-group-name>
+<UL>
+<LI><xtag-item1>0=7</xtag-item1></LI>
+<LI><xtag-item1>1=7</xtag-item1></LI>
+<LI><xtag-item1>OUT=7</xtag-item1></LI>
+<LI><xtag-item1>S0=7</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_F">SLICEL_F</xtag-group-name>
+<UL>
+<LI><xtag-item1>A1=12</xtag-item1></LI>
+<LI><xtag-item1>A2=4</xtag-item1></LI>
+<LI><xtag-item1>A3=4</xtag-item1></LI>
+<LI><xtag-item1>A4=4</xtag-item1></LI>
+<LI><xtag-item1>D=12</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_FFX">SLICEL_FFX</xtag-group-name>
+<UL>
+<LI><xtag-item1>CK=8</xtag-item1></LI>
+<LI><xtag-item1>D=8</xtag-item1></LI>
+<LI><xtag-item1>Q=8</xtag-item1></LI>
+<LI><xtag-item1>SR=8</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_FFY">SLICEL_FFY</xtag-group-name>
+<UL>
+<LI><xtag-item1>CE=1</xtag-item1></LI>
+<LI><xtag-item1>CK=9</xtag-item1></LI>
+<LI><xtag-item1>D=9</xtag-item1></LI>
+<LI><xtag-item1>Q=9</xtag-item1></LI>
+<LI><xtag-item1>SR=8</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_G">SLICEL_G</xtag-group-name>
+<UL>
+<LI><xtag-item1>A1=9</xtag-item1></LI>
+<LI><xtag-item1>A2=1</xtag-item1></LI>
+<LI><xtag-item1>A3=1</xtag-item1></LI>
+<LI><xtag-item1>A4=1</xtag-item1></LI>
+<LI><xtag-item1>D=9</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_GNDF">SLICEL_GNDF</xtag-group-name>
+<UL>
+<LI><xtag-item1>0=1</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_GNDG">SLICEL_GNDG</xtag-group-name>
+<UL>
+<LI><xtag-item1>0=7</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_XORF">SLICEL_XORF</xtag-group-name>
+<UL>
+<LI><xtag-item1>0=8</xtag-item1></LI>
+<LI><xtag-item1>1=8</xtag-item1></LI>
+<LI><xtag-item1>O=8</xtag-item1></LI>
+</UL>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEL_XORG">SLICEL_XORG</xtag-group-name>
+<UL>
+<LI><xtag-item1>0=8</xtag-item1></LI>
+<LI><xtag-item1>1=8</xtag-item1></LI>
+<LI><xtag-item1>O=8</xtag-item1></LI>
+</UL>
+</TD>
+<TD>
+</xtag-group>
+<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
+<UL>
+<LI><xtag-item1>A=1</xtag-item1></LI>
+<LI><xtag-item1>A1=1</xtag-item1></LI>
+<LI><xtag-item1>A2=9</xtag-item1></LI>
+<LI><xtag-item1>A3=9</xtag-item1></LI>
+<LI><xtag-item1>A4=9</xtag-item1></LI>
+<LI><xtag-item1>A5=9</xtag-item1></LI>
+<LI><xtag-item1>A6=9</xtag-item1></LI>
+<LI><xtag-item1>AQ=8</xtag-item1></LI>
+<LI><xtag-item1>B=3</xtag-item1></LI>
+<LI><xtag-item1>B1=3</xtag-item1></LI>
+<LI><xtag-item1>B2=8</xtag-item1></LI>
+<LI><xtag-item1>B3=8</xtag-item1></LI>
+<LI><xtag-item1>B4=8</xtag-item1></LI>
+<LI><xtag-item1>B5=8</xtag-item1></LI>
+<LI><xtag-item1>B6=8</xtag-item1></LI>
+<LI><xtag-item1>BQ=5</xtag-item1></LI>
+<LI><xtag-item1>C=2</xtag-item1></LI>
+<LI><xtag-item1>C1=2</xtag-item1></LI>
+<LI><xtag-item1>C2=8</xtag-item1></LI>
+<LI><xtag-item1>C3=8</xtag-item1></LI>
+<LI><xtag-item1>C4=8</xtag-item1></LI>
+<LI><xtag-item1>C5=8</xtag-item1></LI>
+<LI><xtag-item1>C6=8</xtag-item1></LI>
+<LI><xtag-item1>CLK=8</xtag-item1></LI>
+<LI><xtag-item1>CQ=6</xtag-item1></LI>
+<LI><xtag-item1>D=2</xtag-item1></LI>
+<LI><xtag-item1>D1=2</xtag-item1></LI>
+<LI><xtag-item1>D2=8</xtag-item1></LI>
+<LI><xtag-item1>D3=8</xtag-item1></LI>
+<LI><xtag-item1>D4=8</xtag-item1></LI>
+<LI><xtag-item1>D5=8</xtag-item1></LI>
+<LI><xtag-item1>D6=8</xtag-item1></LI>
+<LI><xtag-item1>DQ=6</xtag-item1></LI>
+</UL>
+</xtag-group>
+</TD>
+</xtag-section>
+</TR></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD><B>Tool Usage</B></TD></TR>
+<TR VALIGN=TOP><TD ALIGN=LEFT>Command Line History<xtag-section name="CommandLineLog"><UL>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -t 1 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -t 1 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -t 1 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -t 1 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc3s250e-vq100-4 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc3s250e-vq100-4 -cm area -ir off -pr off -c 100 -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -t 1 &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx9-tqg144-2 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
+<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
+<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
+</xtag-section></UL></TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR><TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Program Name</B></TD><TD><B>Runs Started</B></TD><TD><B>Runs Finished</B></TD><TD><B>Errors</B></TD><TD><B>Fatal Errors</B></TD><TD><B>Internal Errors</B></TD><TD><B>Exceptions</B></TD><TD><B>Core Dumps</B></TD></TR>
+
+<tr>
+  <td><xtag-program-name>bitgen</xtag-program-name></td>
+  <td><xtag-total-run-started>18</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>18</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>map</xtag-program-name></td>
+  <td><xtag-total-run-started>23</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>19</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>ngc2edif</xtag-program-name></td>
+  <td><xtag-total-run-started>3</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>3</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>ngdbuild</xtag-program-name></td>
+  <td><xtag-total-run-started>29</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>29</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>par</xtag-program-name></td>
+  <td><xtag-total-run-started>19</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>18</xtag-total-run-finished></td>
+  <td><xtag-total-error>1</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>trce</xtag-program-name></td>
+  <td><xtag-total-run-started>18</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>18</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
+  <td><xtag-total-exception>0</xtag-total-exception></td>
+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+<tr>
+  <td><xtag-program-name>xst</xtag-program-name></td>
+  <td><xtag-total-run-started>23</xtag-total-run-started></td>
+  <td><xtag-total-run-finished>23</xtag-total-run-finished></td>
+  <td><xtag-total-error>0</xtag-total-error></td>
+  <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
+  <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
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+  <td><xtag-total-core-dump>0</xtag-total-core-dump></td>
+</tr>
+</xtag-section></TABLE>
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="Project Statistics">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Project Statistics</B></TD></TR>
+<TR>
+<TD><xtag-process-property-name>PROPEXT_xilxSynthMaxFanout_virtex2</xtag-process-property-name>=<xtag-process-property-value>100000</xtag-process-property-value></TD>
+<TD><xtag-design-property-name>PROP_Enable_Message_Filtering</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-process-property-name>PROP_FitterReportFormat</xtag-process-property-name>=<xtag-process-property-value>HTML</xtag-process-property-value></TD>
+<TD><xtag-design-property-name>PROP_LastAppliedGoal</xtag-design-property-name>=<xtag-design-property-value>Balanced</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_LastAppliedStrategy</xtag-design-property-name>=<xtag-design-property-value>Xilinx Default (unlocked)</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_ManualCompileOrderImp</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-process-property-name>PROP_ProjectDescription</xtag-process-property-name>=<xtag-process-property-value>This is a project that will make patterns with led lights.</xtag-process-property-value></TD>
+<TD><xtag-design-property-name>PROP_PropSpecInProjFile</xtag-design-property-name>=<xtag-design-property-value>Store all values</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_Simulator</xtag-design-property-name>=<xtag-design-property-value>ISim (VHDL/Verilog)</xtag-design-property-value></TD>
+<TD><xtag-process-property-name>PROP_SynthTopFile</xtag-process-property-name>=<xtag-process-property-value>changed</xtag-process-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_Top_Level_Module_Type</xtag-design-property-name>=<xtag-design-property-value>HDL</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_UseSmartGuide</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-process-property-name>PROP_UserConstraintEditorPreference</xtag-process-property-name>=<xtag-process-property-value>Text Editor</xtag-process-property-value></TD>
+<TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2017-02-19T23:09:37</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>8C4A34387ED46BFEECE9D369B6F8AAAE</xtag-design-property-value></TD>
+<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>19</xtag-process-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-process-property-name>PROP_xilxBitgStart_IntDone</xtag-process-property-name>=<xtag-process-property-value>true</xtag-process-property-value></TD>
+<TD><xtag-process-property-name>PROP_xilxNgdbld_AUL</xtag-process-property-name>=<xtag-process-property-value>true</xtag-process-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_AutoTop</xtag-design-property-name>=<xtag-design-property-value>true</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_DevFamily</xtag-design-property-name>=<xtag-design-property-value>Spartan6</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_DevDevice</xtag-design-property-name>=<xtag-design-property-value>xc6slx9</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_DevFamilyPMName</xtag-design-property-name>=<xtag-design-property-value>spartan6</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_DevPackage</xtag-design-property-name>=<xtag-design-property-value>tqg144</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_Synthesis_Tool</xtag-design-property-name>=<xtag-design-property-value>XST (VHDL/Verilog)</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-design-property-name>PROP_DevSpeed</xtag-design-property-name>=<xtag-design-property-value>-2</xtag-design-property-value></TD>
+<TD><xtag-design-property-name>PROP_PreferredLanguage</xtag-design-property-name>=<xtag-design-property-value>Verilog</xtag-design-property-value></TD>
+
+</TR><TR><TD><xtag-source-property-name>FILE_UCF</xtag-source-property-name>=<xtag-source-property-value>1</xtag-source-property-value></TD>
+<TD><xtag-source-property-name>FILE_VERILOG</xtag-source-property-name>=<xtag-source-property-value>1</xtag-source-property-value></TD>
+</TR></xtag-section></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="UnisimStatistics">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR>
+<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>25</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>23</xtag-preunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>25</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>8</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>23</xtag-preunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
+<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>24</xtag-preunisim-param-value></TD>
+<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>25</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>23</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>25</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>8</xtag-postunisim-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>23</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
+<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>24</xtag-postunisim-param-value></TD>
+</TR>
+</xtag-section></TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
+<xtag-section name="XstCommandLineOptions">
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>XST Command Line Options</B></TD></TR>
+<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-xstoption-type-name>XST_OPTION_SUMMARY</xtag-xstoption-type-name></B></TD></TR><TR>
+<TD><xtag-xstoptions-param-name>-ifn</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>&lt;fname&gt;.prj</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-ofn</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>&lt;design_top&gt;</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-ofmt</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NGC</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-p</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>xc6slx9-2-tqg144</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-top</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>&lt;design_top&gt;</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-opt_mode</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Speed</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-opt_level</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>1</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-power</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-iuc</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-keep_hierarchy</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>No</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-netlist_hierarchy</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>As_Optimized</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-rtlview</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Yes</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-glob_opt</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>AllClockNets</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-read_cores</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-write_timing_constraints</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-cross_clock_analysis</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-bus_delimiter</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value><></xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-slice_utilization_ratio</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>100</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-bram_utilization_ratio</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>100</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-dsp_utilization_ratio</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>100</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-reduce_control_sets</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-fsm_extract</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-fsm_encoding</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-safe_implementation</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>No</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-fsm_style</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>LUT</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-ram_extract</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Yes</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-ram_style</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-rom_extract</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Yes</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-shreg_extract</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-rom_style</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-auto_bram_packing</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-resource_sharing</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-async_to_sync</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-use_dsp48</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-iobuf</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-max_fanout</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>100000</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-bufg</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>16</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-register_duplication</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-register_balancing</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>No</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-optimize_primitives</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>NO</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-use_clock_enable</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-use_sync_set</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-use_sync_reset</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-iob</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>Auto</xtag-xstoptions-param-value></TD>
+</TR>
+<TR>
+<TD><xtag-xstoptions-param-name>-equivalent_register_removal</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>YES</xtag-xstoptions-param-value></TD>
+<TD><xtag-xstoptions-param-name>-slice_utilization_ratio_maxmargin</xtag-xstoptions-param-name>=<xtag-xstoptions-param-value>5</xtag-xstoptions-param-value></TD>
+</xtag-section></TABLE>
+&nbsp;<BR></BODY></HTML>
diff --git a/webtalk.log b/webtalk.log
new file mode 100644
index 0000000..ca7935a
--- /dev/null
+++ b/webtalk.log
@@ -0,0 +1,16 @@
+Release 14.7 - WebTalk (P.20131013)
+Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
+
+Project Information
+--------------------
+ProjectID=8C4A34387ED46BFEECE9D369B6F8AAAE
+ProjectIteration=19
+
+WebTalk Summary
+----------------
+INFO:WebTalk:1 - WebTalk is enabled because you are using a WebPACK license.
+
+INFO:WebTalk:8 - WebTalk Install setting is ON.
+INFO:WebTalk:6 - WebTalk User setting is ON.
+
+INFO:WebTalk:5 - /home/yannherklotz/Github/FPGA-led-lights/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx.  Please check your network and proxy settings.  For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/14.7/ISE_DS/ISE/data/reports/webtalk_introduction.html
diff --git a/webtalk_pn.xml b/webtalk_pn.xml
index e745db1..b5ece96 100644
--- a/webtalk_pn.xml
+++ b/webtalk_pn.xml
@@ -3,14 +3,15 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pn" timeStamp="Sun Feb 19 23:15:29 2017">
+<application name="pn" timeStamp="Tue Feb 21 22:16:54 2017">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="8C4A34387ED46BFEECE9D369B6F8AAAE" type="project"/>
-<property name="ProjectIteration" value="0" type="project"/>
+<property name="ProjectIteration" value="19" type="project"/>
 <property name="ProjectFile" value="/home/yannherklotz/Github/FPGA-led-lights/FPGA-led-lights.xise" type="project"/>
 <property name="ProjectCreationTimestamp" value="2017-02-19T23:09:37" type="project"/>
 </section>
 <section name="Project Statistics" visible="true">
+<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/>
 <property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
 <property name="PROP_FitterReportFormat" value="HTML" type="process"/>
 <property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
@@ -25,15 +26,18 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
 <property name="PROP_intProjectCreationTimestamp" value="2017-02-19T23:09:37" type="design"/>
 <property name="PROP_intWbtProjectID" value="8C4A34387ED46BFEECE9D369B6F8AAAE" type="design"/>
+<property name="PROP_intWbtProjectIteration" value="19" type="process"/>
 <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
 <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
+<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
+<property name="PROP_xilxNgdbld_AUL" value="true" type="process"/>
 <property name="PROP_AutoTop" value="true" type="design"/>
-<property name="PROP_DevFamily" value="Spartan3E" type="design"/>
-<property name="PROP_DevDevice" value="xc3s250e" type="design"/>
-<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
-<property name="PROP_DevPackage" value="vq100" type="design"/>
+<property name="PROP_DevFamily" value="Spartan6" type="design"/>
+<property name="PROP_DevDevice" value="xc6slx9" type="design"/>
+<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/>
+<property name="PROP_DevPackage" value="tqg144" type="design"/>
 <property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
-<property name="PROP_DevSpeed" value="-4" type="design"/>
+<property name="PROP_DevSpeed" value="-2" type="design"/>
 <property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
 <property name="FILE_UCF" value="1" type="source"/>
 <property name="FILE_VERILOG" value="1" type="source"/>
diff --git a/xlnx_auto_0_xdb/cst.xbcd b/xlnx_auto_0_xdb/cst.xbcd
new file mode 100644
index 0000000..10fb044
--- /dev/null
+++ b/xlnx_auto_0_xdb/cst.xbcd
diff --git a/xst/work/hdllib.ref b/xst/work/hdllib.ref
index a3fd458..c580ba8 100644
--- a/xst/work/hdllib.ref
+++ b/xst/work/hdllib.ref
@@ -1 +1 @@
-MO led NULL led.v vlg69/led.bin 1487546132
+MO led NULL led.v vlg69/led.bin 1487711944
diff --git a/xst/work/vlg69/led.bin b/xst/work/vlg69/led.bin
index 5060a66..df50a53 100644
--- a/xst/work/vlg69/led.bin
+++ b/xst/work/vlg69/led.bin
diff --git a/xst/work/work.sdbl b/xst/work/work.sdbl
new file mode 100644
index 0000000..5c59628
--- /dev/null
+++ b/xst/work/work.sdbl
diff --git a/xst/work/work.sdbx b/xst/work/work.sdbx
new file mode 100644
index 0000000..6050940
--- /dev/null
+++ b/xst/work/work.sdbx
author	Yann Herklotz <ymherklotz@gmail.com>	2017-02-22 00:14:38 +0000
committer	Yann Herklotz <ymherklotz@gmail.com>	2017-02-22 00:14:38 +0000
commit	e318230b35fc130d74f1b4c6b70bbb2d5afe6780 (patch)
tree	1a1730eb8f35f6932ce82e349c2dba1c089b1b64
parent	0446c43ffae38888dfad9120281acde6a7954509 (diff)
download	FPGA_Playground-master.tar.gz FPGA_Playground-master.zip