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| author | Yann Herklotz <ymherklotz@gmail.com> | 2016-11-21 21:50:12 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-11-21 21:50:12 +0000 |
| commit | 34bbafcfadde67fc4977d3d43218ddaec9d6dc48 (patch) | |
| tree | eaf93df8e24e408d42b5366407aa2ca26a699cb3 | |
| parent | e1ad49f62f7266000e4ed9f1bcc678cb9ebe1268 (diff) | |
| download | VerilogCoursework-34bbafcfadde67fc4977d3d43218ddaec9d6dc48.tar.gz VerilogCoursework-34bbafcfadde67fc4977d3d43218ddaec9d6dc48.zip | |
Update README.md
| -rw-r--r-- | part_1/README.md | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/part_1/README.md b/part_1/README.md index b6da5a9..8dbeb90 100644 --- a/part_1/README.md +++ b/part_1/README.md @@ -5,8 +5,14 @@ In this experiment we will be programming a Cyclone V FPGA from Altera on a DE1- ## Experiment 1: Schematic capture using Quartus II -- 7-Segment Display + +### Introduction + We first downloaded the solution for Exercise 1 and tried programming the FPGA using the Programmer from Quartus. The software didn't detect the DE1-SoC board and we had to turn it off and on again for the DE-SOC [USB-1] to appear. After we then added the right type of FPGA to the project (5CSEMA5) and deleted the ARM processor from the programmer window (SOCVHPS) we were able to add the solution to the FPGA and download it onto the board. + +### Using Block Diagram + We then used the truth table for the 7-Segment Decoder to create the K-map for the output number 4, so that we can extract the Sum of Products form from the K-map. We then added the missing output to the incomplete block diagram.  @@ -41,3 +47,8 @@ __Slow 1100mV 85°C TimeQuest Timing Analyzer Table__ The output on these tables shows the propagation delays from the inputs to the outputs. The 4 different rows have 4 different abreviations RR, RF, FR and FF, that stand for Rise-Rise, Rise-Fall, Fall-Rise and Fall-Fall respectively. These describe the time it takes for the signal to travel from a rise or fall of the signal to produce a rise or fall in the output signal. There are some boxes in the table that do not have a time in there, this is because these connections never happen and therefore the FPGA simplifies them and does not even connect them, and therefore they do not have a time. The times are also measured in nanoseconds. With the help of these tables we can observe that when the FPGA is at 85°C, the times between the inputs and outputs is higher than when the FPGA is cooled at 0°C. This can be explained by how fast the gates switch due to the transistor voltages switching. The switching time increases as the temperature increases and therefore the time between the inputs and outputs will increase as well. + + +## Experiment 2: 7-Segment Decoder in Verilog HDL + + |