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| author | Yann Herklotz <ymherklotz@gmail.com> | 2016-11-21 23:21:29 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-11-21 23:21:29 +0000 |
| commit | 511f9d0d5c0295dad4376592a56a571430f0450e (patch) | |
| tree | 98fb1f0d509bbc495e771fa10739cd118525dbc1 | |
| parent | 36efc8e72a28e00d58dea3ff889284aff85e3339 (diff) | |
| download | VerilogCoursework-511f9d0d5c0295dad4376592a56a571430f0450e.tar.gz VerilogCoursework-511f9d0d5c0295dad4376592a56a571430f0450e.zip | |
Update README.md
| -rw-r--r-- | part_1/README.md | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/part_1/README.md b/part_1/README.md index cfcced9..bc6754f 100644 --- a/part_1/README.md +++ b/part_1/README.md @@ -126,3 +126,12 @@ module ex3(SW, HEX0, HEX1, HEX2); endmodule ``` + +This takes in the 10-bit input from the 10 switches, which are assigned to by the text file, and set the output to be the hex display. We then checked the syntax again and ran the analysis and elaboration on the project to see if there are any errors. + +When programming the FPGA we tested it by setting known binary values into the switches and checked if the displays showed the correct values. + + +## Experiment 4: Displaying 10-bit binary as BCD digits on the 7-Segment Displays + + |