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| author | Yann Herklotz <ymherklotz@gmail.com> | 2016-11-15 22:59:05 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-11-15 22:59:05 +0000 |
| commit | 9ef26bb5e9cce099e52617a886bfd68db2c3bf43 (patch) | |
| tree | f0ad8815f64a2b0afcd319d5b35b8605bbca72c4 | |
| parent | b4ac07aaff157fc0a98375ed2fb7bfdd6debf366 (diff) | |
| download | VerilogCoursework-9ef26bb5e9cce099e52617a886bfd68db2c3bf43.tar.gz VerilogCoursework-9ef26bb5e9cce099e52617a886bfd68db2c3bf43.zip | |
Update README.md
| -rw-r--r-- | part_1/README.md | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/part_1/README.md b/part_1/README.md index 6e684ee..2e6e8d5 100644 --- a/part_1/README.md +++ b/part_1/README.md @@ -5,7 +5,15 @@ In this experiment we will be programming a Cyclone V FPGA from Altera on a DE1- We first downloaded the solution for Exercise 1 and tried programming the FPGA using the Programmer from Quartus. The software didn't detect the DE1-SoC board and we had to turn it off and on again for the DE-SOC [USB-1] to appear. After we then added the right type of FPGA to the project (5CSEMA5) and deleted the ARM processor from the programmer window (SOCVHPS) we were able to add the solution to the FPGA and download it onto the board. We then used the truth table for the 7-Segment Decoder to create the K-map for the output number 4, so that we can extract the Sum of Products form from the K-map. We then added the missing output to the incomplete block diagram. +  + We then created a new block diagram, and made a symbol file for the 7-Segment Decoder, so that we can include it in this block diagram. We then made this block diagram our top-level design. +  +We then compiled the Quartus project to see if there are any errors in the files, and then we added the pin assignments using the Pin Planner + + + + |