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| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /mylib/ex8.v | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'mylib/ex8.v')
| -rwxr-xr-x | mylib/ex8.v | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/mylib/ex8.v b/mylib/ex8.v new file mode 100755 index 0000000..aaa8488 --- /dev/null +++ b/mylib/ex8.v @@ -0,0 +1,23 @@ +module ex8(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);
+
+ input CLOCK_50;
+ input [3:0] KEY;
+ output [9:0] LEDR;
+ output [6:0] HEX0, HEX1, HEX2;
+
+ wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
+ wire [6:0] N;
+ wire [6:0] bcd_to_hex;
+ wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
+
+ tick_50000 TICK0(CLOCK_50, tick_ms);
+ tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
+ formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
+ LFSR LFSR0(tick_ms, en_lfsr, N);
+ delay DEL0(tick_ms, N, start_delay, time_out);
+ bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+ hex_to_7seg SEG0(HEX0, BCD_0);
+ hex_to_7seg SEG1(HEX1, BCD_1);
+ hex_to_7seg SEG2(HEX2, BCD_2);
+
+endmodule
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