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author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
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committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex10/db/ex10.lpc.txt | |
parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip |
adding part 2 and 3
Diffstat (limited to 'part_3/ex10/db/ex10.lpc.txt')
-rwxr-xr-x | part_3/ex10/db/ex10.lpc.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/part_3/ex10/db/ex10.lpc.txt b/part_3/ex10/db/ex10.lpc.txt new file mode 100755 index 0000000..44995a4 --- /dev/null +++ b/part_3/ex10/db/ex10.lpc.txt @@ -0,0 +1,8 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; s ; 12 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; t ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
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