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| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex10/db/ex10.tmw_info | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'part_3/ex10/db/ex10.tmw_info')
| -rwxr-xr-x | part_3/ex10/db/ex10.tmw_info | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/part_3/ex10/db/ex10.tmw_info b/part_3/ex10/db/ex10.tmw_info new file mode 100755 index 0000000..bc1ad30 --- /dev/null +++ b/part_3/ex10/db/ex10.tmw_info @@ -0,0 +1,7 @@ +start_full_compilation:s:00:01:00
+start_analysis_synthesis:s:00:00:11-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:34-start_full_compilation
+start_assembler:s:00:00:07-start_full_compilation
+start_timing_analyzer:s:00:00:06-start_full_compilation
+start_eda_netlist_writer:s:00:00:02-start_full_compilation
|