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author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
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committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex10/ex10_nativelink_simulation.rpt | |
parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip |
adding part 2 and 3
Diffstat (limited to 'part_3/ex10/ex10_nativelink_simulation.rpt')
-rwxr-xr-x | part_3/ex10/ex10_nativelink_simulation.rpt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/part_3/ex10/ex10_nativelink_simulation.rpt b/part_3/ex10/ex10_nativelink_simulation.rpt new file mode 100755 index 0000000..91c988e --- /dev/null +++ b/part_3/ex10/ex10_nativelink_simulation.rpt @@ -0,0 +1,22 @@ +Info: Start Nativelink Simulation process
+Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
+
+========= EDA Simulation Settings =====================
+
+Sim Mode : RTL
+Family : cyclonev
+Quartus root : c:/altera/16.0/quartus/bin64/
+Quartus sim root : c:/altera/16.0/quartus/eda/sim_lib
+Simulation Tool : modelsim-altera
+Simulation Language : verilog
+Simulation Mode : GUI
+Sim Output File :
+Sim SDF file :
+Sim dir : simulation\modelsim
+
+=======================================================
+
+Info: Starting NativeLink simulation with ModelSim-Altera software
+Sourced NativeLink script c:/altera/16.0/quartus/common/tcl/internal/nativelink/modelsim.tcl
+Warning: File ex10_run_msim_rtl_verilog.do already exists - backing up current file as ex10_run_msim_rtl_verilog.do.bak
+Info: Spawning ModelSim-Altera Simulation software
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