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| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex11/db/ex10.db_info | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'part_3/ex11/db/ex10.db_info')
| -rwxr-xr-x | part_3/ex11/db/ex10.db_info | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/part_3/ex11/db/ex10.db_info b/part_3/ex11/db/ex10.db_info new file mode 100755 index 0000000..008242d --- /dev/null +++ b/part_3/ex11/db/ex10.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 29 10:59:52 2016
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