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| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex11/db/ex10.smp_dump.txt | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'part_3/ex11/db/ex10.smp_dump.txt')
| -rwxr-xr-x | part_3/ex11/db/ex10.smp_dump.txt | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/part_3/ex11/db/ex10.smp_dump.txt b/part_3/ex11/db/ex10.smp_dump.txt new file mode 100755 index 0000000..f4c4929 --- /dev/null +++ b/part_3/ex11/db/ex10.smp_dump.txt @@ -0,0 +1,6 @@ +
+State Machine - |ex11|spi2dac:s|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL
+sr_state.IDLE 0 0 0
+sr_state.WAIT_CSB_FALL 1 0 1
+sr_state.WAIT_CSB_HIGH 1 1 0
|