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| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex11/output_files/ex10.fit.summary | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'part_3/ex11/output_files/ex10.fit.summary')
| -rwxr-xr-x | part_3/ex11/output_files/ex10.fit.summary | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/part_3/ex11/output_files/ex10.fit.summary b/part_3/ex11/output_files/ex10.fit.summary new file mode 100755 index 0000000..5625c82 --- /dev/null +++ b/part_3/ex11/output_files/ex10.fit.summary @@ -0,0 +1,20 @@ +Fitter Status : Successful - Tue Nov 29 11:05:33 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex10
+Top-level Entity Name : ex11
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 43 / 32,070 ( < 1 % )
+Total registers : 78
+Total pins : 16 / 457 ( 4 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
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