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| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do')
| -rwxr-xr-x | part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do new file mode 100755 index 0000000..b12a7d7 --- /dev/null +++ b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do @@ -0,0 +1,17 @@ +add wave -position end sysclk +add wave -position end -hexadecimal data_in +add wave -position end load +add wave -position end dac_sdi +add wave -position end dac_cs +add wave -position end dac_sck +add wave -position end dac_ld +force sysclk 1 0, 0 10ns -r 20ns +force data_in 10'h23b +force load 0 +run 200ns +force load 1 +run 400ns +force load 0 +run 20us + + |