diff options
| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex11/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'part_3/ex11/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak')
| -rwxr-xr-x | part_3/ex11/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/part_3/ex11/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak b/part_3/ex11/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak new file mode 100755 index 0000000..281cccf --- /dev/null +++ b/part_3/ex11/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak @@ -0,0 +1,9 @@ +transcript on
+if {[file exists rtl_work]} {
+ vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/New\ folder/ex10/verilog_files {C:/New folder/ex10/verilog_files/spi2dac.v}
+
|