adding part 2 and 3

1 files changed, 25 insertions, 0 deletions

diff --git a/part_3/ex11/verilog_files/pwm.v b/part_3/ex11/verilog_files/pwm.v
new file mode 100755
index 0000000..6a6e10c
--- /dev/null
+++ b/part_3/ex11/verilog_files/pwm.v
@@ -0,0 +1,25 @@
+module pwm(clk, data_in, load, pwm_out);

+

+	input clk;

+	input [9:0] data_in;

+	input load;

+	output pwm_out;

+	

+	reg[9:0] d;

+	reg [9:0] count;

+	reg pwm_out;

+	

+	always @ (posedge clk)

+		if(load == 1'b1) d <= data_in;

+		

+	initial count = 10'b0;

+	

+	always @ (posedge clk) begin

+		count <= count + 1'b1;

+		if(count > d)

+			pwm_out <= 1'b0;

+		else

+			pwm_out <= 1'b1;

+		end

+		

+endmodule
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