adding part 2 and 3

author: zedarider <ymherklotz@gmail.com> 2016-12-01 23:57:19 +0000
committer: zedarider <ymherklotz@gmail.com> 2016-12-01 23:57:19 +0000
commit: 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch)
tree: e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex12
parent: 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff)
download: VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz
VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip
129 files changed, 8595 insertions, 0 deletions
diff --git a/part_3/ex12/ROM.qip b/part_3/ex12/ROM.qip
new file mode 100755
index 0000000..dc92785
--- /dev/null
+++ b/part_3/ex12/ROM.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "16.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ROM.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ROM_bb.v"]
diff --git a/part_3/ex12/ROM.v b/part_3/ex12/ROM.v
new file mode 100755
index 0000000..296e57c
--- /dev/null
+++ b/part_3/ex12/ROM.v
@@ -0,0 +1,160 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ROM.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ROM (
+	address,
+	clock,
+	q);
+
+	input	[9:0]  address;
+	input	  clock;
+	output	[9:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [9:0] sub_wire0;
+	wire [9:0] q = sub_wire0[9:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a ({10{1'b1}}),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = "./rom_data/rom_data.mif",
+		altsyncram_component.intended_device_family = "Cyclone V",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 1024,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.widthad_a = 10,
+		altsyncram_component.width_a = 10,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "./rom_data/rom_data.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
+// Retrieval info: PRIVATE: WidthData NUMERIC "10"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "./rom_data/rom_data.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
+// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 10 0 @q_a 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_3/ex12/ROM_bb.v b/part_3/ex12/ROM_bb.v
new file mode 100755
index 0000000..b8730db
--- /dev/null
+++ b/part_3/ex12/ROM_bb.v
@@ -0,0 +1,111 @@
+// megafunction wizard: %ROM: 1-PORT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ROM.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+module ROM (
+	address,
+	clock,
+	q);
+
+	input	[9:0]  address;
+	input	  clock;
+	output	[9:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "./rom_data/rom_data.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
+// Retrieval info: PRIVATE: WidthData NUMERIC "10"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "./rom_data/rom_data.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
+// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 10 0 @q_a 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_3/ex12/c5_pin_model_dump.txt b/part_3/ex12/c5_pin_model_dump.txt
new file mode 100755
index 0000000..a895a64
--- /dev/null
+++ b/part_3/ex12/c5_pin_model_dump.txt
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_3/ex12/db/.cmp.kpt b/part_3/ex12/db/.cmp.kpt
new file mode 100755
index 0000000..fa3c9a7
--- /dev/null
+++ b/part_3/ex12/db/.cmp.kpt
diff --git a/part_3/ex12/db/altsyncram_6ng1.tdf b/part_3/ex12/db/altsyncram_6ng1.tdf
new file mode 100755
index 0000000..e896d11
--- /dev/null
+++ b/part_3/ex12/db/altsyncram_6ng1.tdf
@@ -0,0 +1,264 @@
+--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./rom_data/rom_data.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=10 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 16.0 cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
+RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M10K 1 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_6ng1
+( 
+	address_a[9..0]	:	input;
+	clock0	:	input;
+	q_a[9..0]	:	output;
+) 
+VARIABLE 
+	ram_block1a0 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a8 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a9 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[9..0]	: WIRE;
+
+BEGIN 
+	ram_block1a[9..0].clk0 = clock0;
+	ram_block1a[9..0].portaaddr[] = ( address_a_wire[9..0]);
+	ram_block1a[9..0].portare = B"1111111111";
+	address_a_wire[] = address_a[];
+	q_a[] = ( ram_block1a[9..0].portadataout[0..0]);
+END;
+--VALID FILE
diff --git a/part_3/ex12/db/ex12.(0).cnf.cdb b/part_3/ex12/db/ex12.(0).cnf.cdb
new file mode 100755
index 0000000..c432c30
--- /dev/null
+++ b/part_3/ex12/db/ex12.(0).cnf.cdb
diff --git a/part_3/ex12/db/ex12.(0).cnf.hdb b/part_3/ex12/db/ex12.(0).cnf.hdb
new file mode 100755
index 0000000..14f465e
--- /dev/null
+++ b/part_3/ex12/db/ex12.(0).cnf.hdb
diff --git a/part_3/ex12/db/ex12.(1).cnf.cdb b/part_3/ex12/db/ex12.(1).cnf.cdb
new file mode 100755
index 0000000..afb003e
--- /dev/null
+++ b/part_3/ex12/db/ex12.(1).cnf.cdb
diff --git a/part_3/ex12/db/ex12.(1).cnf.hdb b/part_3/ex12/db/ex12.(1).cnf.hdb
new file mode 100755
index 0000000..f798bd2
--- /dev/null
+++ b/part_3/ex12/db/ex12.(1).cnf.hdb
diff --git a/part_3/ex12/db/ex12.(2).cnf.cdb b/part_3/ex12/db/ex12.(2).cnf.cdb
new file mode 100755
index 0000000..65d5103
--- /dev/null
+++ b/part_3/ex12/db/ex12.(2).cnf.cdb
diff --git a/part_3/ex12/db/ex12.(2).cnf.hdb b/part_3/ex12/db/ex12.(2).cnf.hdb
new file mode 100755
index 0000000..d30343a
--- /dev/null
+++ b/part_3/ex12/db/ex12.(2).cnf.hdb
diff --git a/part_3/ex12/db/ex12.(3).cnf.cdb b/part_3/ex12/db/ex12.(3).cnf.cdb
new file mode 100755
index 0000000..ac08455
--- /dev/null
+++ b/part_3/ex12/db/ex12.(3).cnf.cdb
diff --git a/part_3/ex12/db/ex12.(3).cnf.hdb b/part_3/ex12/db/ex12.(3).cnf.hdb
new file mode 100755
index 0000000..a9f59ec
--- /dev/null
+++ b/part_3/ex12/db/ex12.(3).cnf.hdb
diff --git a/part_3/ex12/db/ex12.(6).cnf.cdb b/part_3/ex12/db/ex12.(6).cnf.cdb
new file mode 100755
index 0000000..363d2da
--- /dev/null
+++ b/part_3/ex12/db/ex12.(6).cnf.cdb
diff --git a/part_3/ex12/db/ex12.(6).cnf.hdb b/part_3/ex12/db/ex12.(6).cnf.hdb
new file mode 100755
index 0000000..cd94133
--- /dev/null
+++ b/part_3/ex12/db/ex12.(6).cnf.hdb
diff --git a/part_3/ex12/db/ex12.asm.qmsg b/part_3/ex12/db/ex12.asm.qmsg
new file mode 100755
index 0000000..e2031c5
--- /dev/null
+++ b/part_3/ex12/db/ex12.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480419427284 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480419427287 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:37:06 2016 " "Processing started: Tue Nov 29 11:37:06 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480419427287 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480419427287 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex12 -c ex12 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex12 -c ex12" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480419427287 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480419428089 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480419432567 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "892 " "Peak virtual memory: 892 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480419432907 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:37:12 2016 " "Processing ended: Tue Nov 29 11:37:12 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480419432907 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480419432907 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480419432907 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480419432907 ""}
diff --git a/part_3/ex12/db/ex12.asm.rdb b/part_3/ex12/db/ex12.asm.rdb
new file mode 100755
index 0000000..4177db4
--- /dev/null
+++ b/part_3/ex12/db/ex12.asm.rdb
diff --git a/part_3/ex12/db/ex12.cmp.ammdb b/part_3/ex12/db/ex12.cmp.ammdb
new file mode 100755
index 0000000..f62fa3d
--- /dev/null
+++ b/part_3/ex12/db/ex12.cmp.ammdb
diff --git a/part_3/ex12/db/ex12.cmp.bpm b/part_3/ex12/db/ex12.cmp.bpm
new file mode 100755
index 0000000..ee4df08
--- /dev/null
+++ b/part_3/ex12/db/ex12.cmp.bpm
diff --git a/part_3/ex12/db/ex12.cmp.cdb b/part_3/ex12/db/ex12.cmp.cdb
new file mode 100755
index 0000000..701ee68
--- /dev/null
+++ b/part_3/ex12/db/ex12.cmp.cdb
diff --git a/part_3/ex12/db/ex12.cmp.hdb b/part_3/ex12/db/ex12.cmp.hdb
new file mode 100755
index 0000000..94f641a
--- /dev/null
+++ b/part_3/ex12/db/ex12.cmp.hdb
diff --git a/part_3/ex12/db/ex12.cmp.idb b/part_3/ex12/db/ex12.cmp.idb
new file mode 100755
index 0000000..c1dd6b3
--- /dev/null
+++ b/part_3/ex12/db/ex12.cmp.idb
diff --git a/part_3/ex12/db/ex12.cmp.logdb b/part_3/ex12/db/ex12.cmp.logdb
new file mode 100755
index 0000000..68c48a6
--- /dev/null
+++ b/part_3/ex12/db/ex12.cmp.logdb
@@ -0,0 +1,71 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,32;0;32;0;0;32;32;0;32;32;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;32;0;32;32;0;0;32;0;0;32;32;32;32;32;32;32;32;32;32;32;32;32;32;32;32;32;32,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_3/ex12/db/ex12.cmp.rdb b/part_3/ex12/db/ex12.cmp.rdb
new file mode 100755
index 0000000..c874eb8
--- /dev/null
+++ b/part_3/ex12/db/ex12.cmp.rdb
diff --git a/part_3/ex12/db/ex12.cmp_merge.kpt b/part_3/ex12/db/ex12.cmp_merge.kpt
new file mode 100755
index 0000000..a831f53
--- /dev/null
+++ b/part_3/ex12/db/ex12.cmp_merge.kpt
diff --git a/part_3/ex12/db/ex12.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_3/ex12/db/ex12.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..5b115d6
--- /dev/null
+++ b/part_3/ex12/db/ex12.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_3/ex12/db/ex12.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_3/ex12/db/ex12.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..3a7a497
--- /dev/null
+++ b/part_3/ex12/db/ex12.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_3/ex12/db/ex12.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_3/ex12/db/ex12.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100755
index 0000000..aa473fa
--- /dev/null
+++ b/part_3/ex12/db/ex12.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_3/ex12/db/ex12.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_3/ex12/db/ex12.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100755
index 0000000..dce4f6b
--- /dev/null
+++ b/part_3/ex12/db/ex12.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_3/ex12/db/ex12.db_info b/part_3/ex12/db/ex12.db_info
new file mode 100755
index 0000000..4ea4912
--- /dev/null
+++ b/part_3/ex12/db/ex12.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 29 11:12:25 2016
diff --git a/part_3/ex12/db/ex12.fit.qmsg b/part_3/ex12/db/ex12.fit.qmsg
new file mode 100755
index 0000000..6070f60
--- /dev/null
+++ b/part_3/ex12/db/ex12.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480419398415 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480419398415 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex12 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex12\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480419398670 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480419398738 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480419398738 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480419399119 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480419399256 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1480419399257 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480419409152 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 10 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 10 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480419409221 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480419409221 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480419409221 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480419409224 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480419409224 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480419409224 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480419409225 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480419409225 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480419409225 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480419409225 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480419409226 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480419409226 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419409257 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480419409257 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480419409259 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex12.sdc " "Synopsys Design Constraints File file not found: 'ex12.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480419414829 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480419414829 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480419414831 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480419414831 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480419414832 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480419414834 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480419414904 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480419415353 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480419415738 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480419416013 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480419416013 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480419416901 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X67_Y0 X77_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex12/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10"} { { 12 { 0 ""} 67 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480419421348 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480419421348 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480419421517 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1480419421517 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480419421517 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480419421522 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.07 " "Total time spent on timing analysis during the Fitter is 0.07 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480419422520 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480419422555 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480419422864 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480419422864 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480419423172 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480419425299 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480419425526 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex12/output_files/ex12.fit.smsg " "Generated suppressed messages file C:/New folder/ex12/output_files/ex12.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480419425574 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 54 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 54 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2589 " "Peak virtual memory: 2589 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480419425960 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:37:05 2016 " "Processing ended: Tue Nov 29 11:37:05 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480419425960 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480419425960 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480419425960 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480419425960 ""}
diff --git a/part_3/ex12/db/ex12.hier_info b/part_3/ex12/db/ex12.hier_info
new file mode 100755
index 0000000..83aa3d5
--- /dev/null
+++ b/part_3/ex12/db/ex12.hier_info
@@ -0,0 +1,279 @@
+|ex12
+CLOCK_50 => CLOCK_50.IN1
+SW[0] => SW[0].IN1
+SW[1] => SW[1].IN1
+SW[2] => SW[2].IN1
+SW[3] => SW[3].IN1
+SW[4] => SW[4].IN1
+SW[5] => SW[5].IN1
+SW[6] => SW[6].IN1
+SW[7] => SW[7].IN1
+SW[8] => SW[8].IN1
+SW[9] => SW[9].IN1
+HEX0[0] <= hex_to_7seg:h0.port0
+HEX0[1] <= hex_to_7seg:h0.port0
+HEX0[2] <= hex_to_7seg:h0.port0
+HEX0[3] <= hex_to_7seg:h0.port0
+HEX0[4] <= hex_to_7seg:h0.port0
+HEX0[5] <= hex_to_7seg:h0.port0
+HEX0[6] <= hex_to_7seg:h0.port0
+HEX1[0] <= hex_to_7seg:h1.port0
+HEX1[1] <= hex_to_7seg:h1.port0
+HEX1[2] <= hex_to_7seg:h1.port0
+HEX1[3] <= hex_to_7seg:h1.port0
+HEX1[4] <= hex_to_7seg:h1.port0
+HEX1[5] <= hex_to_7seg:h1.port0
+HEX1[6] <= hex_to_7seg:h1.port0
+HEX2[0] <= hex_to_7seg:h2.port0
+HEX2[1] <= hex_to_7seg:h2.port0
+HEX2[2] <= hex_to_7seg:h2.port0
+HEX2[3] <= hex_to_7seg:h2.port0
+HEX2[4] <= hex_to_7seg:h2.port0
+HEX2[5] <= hex_to_7seg:h2.port0
+HEX2[6] <= hex_to_7seg:h2.port0
+
+
+|ex12|ROM:r
+address[0] => address[0].IN1
+address[1] => address[1].IN1
+address[2] => address[2].IN1
+address[3] => address[3].IN1
+address[4] => address[4].IN1
+address[5] => address[5].IN1
+address[6] => address[6].IN1
+address[7] => address[7].IN1
+address[8] => address[8].IN1
+address[9] => address[9].IN1
+clock => clock.IN1
+q[0] <= altsyncram:altsyncram_component.q_a
+q[1] <= altsyncram:altsyncram_component.q_a
+q[2] <= altsyncram:altsyncram_component.q_a
+q[3] <= altsyncram:altsyncram_component.q_a
+q[4] <= altsyncram:altsyncram_component.q_a
+q[5] <= altsyncram:altsyncram_component.q_a
+q[6] <= altsyncram:altsyncram_component.q_a
+q[7] <= altsyncram:altsyncram_component.q_a
+q[8] <= altsyncram:altsyncram_component.q_a
+q[9] <= altsyncram:altsyncram_component.q_a
+
+
+|ex12|ROM:r|altsyncram:altsyncram_component
+wren_a => ~NO_FANOUT~
+rden_a => ~NO_FANOUT~
+wren_b => ~NO_FANOUT~
+rden_b => ~NO_FANOUT~
+data_a[0] => ~NO_FANOUT~
+data_a[1] => ~NO_FANOUT~
+data_a[2] => ~NO_FANOUT~
+data_a[3] => ~NO_FANOUT~
+data_a[4] => ~NO_FANOUT~
+data_a[5] => ~NO_FANOUT~
+data_a[6] => ~NO_FANOUT~
+data_a[7] => ~NO_FANOUT~
+data_a[8] => ~NO_FANOUT~
+data_a[9] => ~NO_FANOUT~
+data_b[0] => ~NO_FANOUT~
+address_a[0] => altsyncram_6ng1:auto_generated.address_a[0]
+address_a[1] => altsyncram_6ng1:auto_generated.address_a[1]
+address_a[2] => altsyncram_6ng1:auto_generated.address_a[2]
+address_a[3] => altsyncram_6ng1:auto_generated.address_a[3]
+address_a[4] => altsyncram_6ng1:auto_generated.address_a[4]
+address_a[5] => altsyncram_6ng1:auto_generated.address_a[5]
+address_a[6] => altsyncram_6ng1:auto_generated.address_a[6]
+address_a[7] => altsyncram_6ng1:auto_generated.address_a[7]
+address_a[8] => altsyncram_6ng1:auto_generated.address_a[8]
+address_a[9] => altsyncram_6ng1:auto_generated.address_a[9]
+address_b[0] => ~NO_FANOUT~
+addressstall_a => ~NO_FANOUT~
+addressstall_b => ~NO_FANOUT~
+clock0 => altsyncram_6ng1:auto_generated.clock0
+clock1 => ~NO_FANOUT~
+clocken0 => ~NO_FANOUT~
+clocken1 => ~NO_FANOUT~
+clocken2 => ~NO_FANOUT~
+clocken3 => ~NO_FANOUT~
+aclr0 => ~NO_FANOUT~
+aclr1 => ~NO_FANOUT~
+byteena_a[0] => ~NO_FANOUT~
+byteena_b[0] => ~NO_FANOUT~
+q_a[0] <= altsyncram_6ng1:auto_generated.q_a[0]
+q_a[1] <= altsyncram_6ng1:auto_generated.q_a[1]
+q_a[2] <= altsyncram_6ng1:auto_generated.q_a[2]
+q_a[3] <= altsyncram_6ng1:auto_generated.q_a[3]
+q_a[4] <= altsyncram_6ng1:auto_generated.q_a[4]
+q_a[5] <= altsyncram_6ng1:auto_generated.q_a[5]
+q_a[6] <= altsyncram_6ng1:auto_generated.q_a[6]
+q_a[7] <= altsyncram_6ng1:auto_generated.q_a[7]
+q_a[8] <= altsyncram_6ng1:auto_generated.q_a[8]
+q_a[9] <= altsyncram_6ng1:auto_generated.q_a[9]
+q_b[0] <= <GND>
+eccstatus[0] <= <GND>
+eccstatus[1] <= <GND>
+eccstatus[2] <= <GND>
+
+
+|ex12|ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated
+address_a[0] => ram_block1a0.PORTAADDR
+address_a[0] => ram_block1a1.PORTAADDR
+address_a[0] => ram_block1a2.PORTAADDR
+address_a[0] => ram_block1a3.PORTAADDR
+address_a[0] => ram_block1a4.PORTAADDR
+address_a[0] => ram_block1a5.PORTAADDR
+address_a[0] => ram_block1a6.PORTAADDR
+address_a[0] => ram_block1a7.PORTAADDR
+address_a[0] => ram_block1a8.PORTAADDR
+address_a[0] => ram_block1a9.PORTAADDR
+address_a[1] => ram_block1a0.PORTAADDR1
+address_a[1] => ram_block1a1.PORTAADDR1
+address_a[1] => ram_block1a2.PORTAADDR1
+address_a[1] => ram_block1a3.PORTAADDR1
+address_a[1] => ram_block1a4.PORTAADDR1
+address_a[1] => ram_block1a5.PORTAADDR1
+address_a[1] => ram_block1a6.PORTAADDR1
+address_a[1] => ram_block1a7.PORTAADDR1
+address_a[1] => ram_block1a8.PORTAADDR1
+address_a[1] => ram_block1a9.PORTAADDR1
+address_a[2] => ram_block1a0.PORTAADDR2
+address_a[2] => ram_block1a1.PORTAADDR2
+address_a[2] => ram_block1a2.PORTAADDR2
+address_a[2] => ram_block1a3.PORTAADDR2
+address_a[2] => ram_block1a4.PORTAADDR2
+address_a[2] => ram_block1a5.PORTAADDR2
+address_a[2] => ram_block1a6.PORTAADDR2
+address_a[2] => ram_block1a7.PORTAADDR2
+address_a[2] => ram_block1a8.PORTAADDR2
+address_a[2] => ram_block1a9.PORTAADDR2
+address_a[3] => ram_block1a0.PORTAADDR3
+address_a[3] => ram_block1a1.PORTAADDR3
+address_a[3] => ram_block1a2.PORTAADDR3
+address_a[3] => ram_block1a3.PORTAADDR3
+address_a[3] => ram_block1a4.PORTAADDR3
+address_a[3] => ram_block1a5.PORTAADDR3
+address_a[3] => ram_block1a6.PORTAADDR3
+address_a[3] => ram_block1a7.PORTAADDR3
+address_a[3] => ram_block1a8.PORTAADDR3
+address_a[3] => ram_block1a9.PORTAADDR3
+address_a[4] => ram_block1a0.PORTAADDR4
+address_a[4] => ram_block1a1.PORTAADDR4
+address_a[4] => ram_block1a2.PORTAADDR4
+address_a[4] => ram_block1a3.PORTAADDR4
+address_a[4] => ram_block1a4.PORTAADDR4
+address_a[4] => ram_block1a5.PORTAADDR4
+address_a[4] => ram_block1a6.PORTAADDR4
+address_a[4] => ram_block1a7.PORTAADDR4
+address_a[4] => ram_block1a8.PORTAADDR4
+address_a[4] => ram_block1a9.PORTAADDR4
+address_a[5] => ram_block1a0.PORTAADDR5
+address_a[5] => ram_block1a1.PORTAADDR5
+address_a[5] => ram_block1a2.PORTAADDR5
+address_a[5] => ram_block1a3.PORTAADDR5
+address_a[5] => ram_block1a4.PORTAADDR5
+address_a[5] => ram_block1a5.PORTAADDR5
+address_a[5] => ram_block1a6.PORTAADDR5
+address_a[5] => ram_block1a7.PORTAADDR5
+address_a[5] => ram_block1a8.PORTAADDR5
+address_a[5] => ram_block1a9.PORTAADDR5
+address_a[6] => ram_block1a0.PORTAADDR6
+address_a[6] => ram_block1a1.PORTAADDR6
+address_a[6] => ram_block1a2.PORTAADDR6
+address_a[6] => ram_block1a3.PORTAADDR6
+address_a[6] => ram_block1a4.PORTAADDR6
+address_a[6] => ram_block1a5.PORTAADDR6
+address_a[6] => ram_block1a6.PORTAADDR6
+address_a[6] => ram_block1a7.PORTAADDR6
+address_a[6] => ram_block1a8.PORTAADDR6
+address_a[6] => ram_block1a9.PORTAADDR6
+address_a[7] => ram_block1a0.PORTAADDR7
+address_a[7] => ram_block1a1.PORTAADDR7
+address_a[7] => ram_block1a2.PORTAADDR7
+address_a[7] => ram_block1a3.PORTAADDR7
+address_a[7] => ram_block1a4.PORTAADDR7
+address_a[7] => ram_block1a5.PORTAADDR7
+address_a[7] => ram_block1a6.PORTAADDR7
+address_a[7] => ram_block1a7.PORTAADDR7
+address_a[7] => ram_block1a8.PORTAADDR7
+address_a[7] => ram_block1a9.PORTAADDR7
+address_a[8] => ram_block1a0.PORTAADDR8
+address_a[8] => ram_block1a1.PORTAADDR8
+address_a[8] => ram_block1a2.PORTAADDR8
+address_a[8] => ram_block1a3.PORTAADDR8
+address_a[8] => ram_block1a4.PORTAADDR8
+address_a[8] => ram_block1a5.PORTAADDR8
+address_a[8] => ram_block1a6.PORTAADDR8
+address_a[8] => ram_block1a7.PORTAADDR8
+address_a[8] => ram_block1a8.PORTAADDR8
+address_a[8] => ram_block1a9.PORTAADDR8
+address_a[9] => ram_block1a0.PORTAADDR9
+address_a[9] => ram_block1a1.PORTAADDR9
+address_a[9] => ram_block1a2.PORTAADDR9
+address_a[9] => ram_block1a3.PORTAADDR9
+address_a[9] => ram_block1a4.PORTAADDR9
+address_a[9] => ram_block1a5.PORTAADDR9
+address_a[9] => ram_block1a6.PORTAADDR9
+address_a[9] => ram_block1a7.PORTAADDR9
+address_a[9] => ram_block1a8.PORTAADDR9
+address_a[9] => ram_block1a9.PORTAADDR9
+clock0 => ram_block1a0.CLK0
+clock0 => ram_block1a1.CLK0
+clock0 => ram_block1a2.CLK0
+clock0 => ram_block1a3.CLK0
+clock0 => ram_block1a4.CLK0
+clock0 => ram_block1a5.CLK0
+clock0 => ram_block1a6.CLK0
+clock0 => ram_block1a7.CLK0
+clock0 => ram_block1a8.CLK0
+clock0 => ram_block1a9.CLK0
+q_a[0] <= ram_block1a0.PORTADATAOUT
+q_a[1] <= ram_block1a1.PORTADATAOUT
+q_a[2] <= ram_block1a2.PORTADATAOUT
+q_a[3] <= ram_block1a3.PORTADATAOUT
+q_a[4] <= ram_block1a4.PORTADATAOUT
+q_a[5] <= ram_block1a5.PORTADATAOUT
+q_a[6] <= ram_block1a6.PORTADATAOUT
+q_a[7] <= ram_block1a7.PORTADATAOUT
+q_a[8] <= ram_block1a8.PORTADATAOUT
+q_a[9] <= ram_block1a9.PORTADATAOUT
+
+
+|ex12|hex_to_7seg:h0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex12|hex_to_7seg:h1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex12|hex_to_7seg:h2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_3/ex12/db/ex12.hif b/part_3/ex12/db/ex12.hif
new file mode 100755
index 0000000..e31adee
--- /dev/null
+++ b/part_3/ex12/db/ex12.hif
diff --git a/part_3/ex12/db/ex12.lpc.html b/part_3/ex12/db/ex12.lpc.html
new file mode 100755
index 0000000..cd006fc
--- /dev/null
+++ b/part_3/ex12/db/ex12.lpc.html
@@ -0,0 +1,98 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >h2</TD>
+<TD >4</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >7</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >h1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >h0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >r|altsyncram_component|auto_generated</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >r</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_3/ex12/db/ex12.lpc.rdb b/part_3/ex12/db/ex12.lpc.rdb
new file mode 100755
index 0000000..e5bff82
--- /dev/null
+++ b/part_3/ex12/db/ex12.lpc.rdb
diff --git a/part_3/ex12/db/ex12.lpc.txt b/part_3/ex12/db/ex12.lpc.txt
new file mode 100755
index 0000000..5d6cf3c
--- /dev/null
+++ b/part_3/ex12/db/ex12.lpc.txt
@@ -0,0 +1,11 @@
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                 ;
++---------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                             ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++---------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; h2                                    ; 4     ; 2              ; 0            ; 2              ; 7      ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; h1                                    ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; h0                                    ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; r|altsyncram_component|auto_generated ; 11    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; r                                     ; 11    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++---------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_3/ex12/db/ex12.map.ammdb b/part_3/ex12/db/ex12.map.ammdb
new file mode 100755
index 0000000..174eb00
--- /dev/null
+++ b/part_3/ex12/db/ex12.map.ammdb
diff --git a/part_3/ex12/db/ex12.map.bpm b/part_3/ex12/db/ex12.map.bpm
new file mode 100755
index 0000000..3c7cc90
--- /dev/null
+++ b/part_3/ex12/db/ex12.map.bpm
diff --git a/part_3/ex12/db/ex12.map.cdb b/part_3/ex12/db/ex12.map.cdb
new file mode 100755
index 0000000..2589287
--- /dev/null
+++ b/part_3/ex12/db/ex12.map.cdb
diff --git a/part_3/ex12/db/ex12.map.hdb b/part_3/ex12/db/ex12.map.hdb
new file mode 100755
index 0000000..f809907
--- /dev/null
+++ b/part_3/ex12/db/ex12.map.hdb
diff --git a/part_3/ex12/db/ex12.map.kpt b/part_3/ex12/db/ex12.map.kpt
new file mode 100755
index 0000000..9b14ca2
--- /dev/null
+++ b/part_3/ex12/db/ex12.map.kpt
diff --git a/part_3/ex12/db/ex12.map.logdb b/part_3/ex12/db/ex12.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_3/ex12/db/ex12.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_3/ex12/db/ex12.map.qmsg b/part_3/ex12/db/ex12.map.qmsg
new file mode 100755
index 0000000..e3ca9a3
--- /dev/null
+++ b/part_3/ex12/db/ex12.map.qmsg
@@ -0,0 +1,21 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480419386856 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480419386858 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:36:26 2016 " "Processing started: Tue Nov 29 11:36:26 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480419386858 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419386858 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex12 -c ex12 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex12 -c ex12" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419386859 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480419387336 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480419387336 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex12/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480419395789 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419395789 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom.v 1 1 " "Found 1 design units, including 1 entities, in source file rom.v" { { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" {  } { { "ROM.v" "" { Text "C:/New folder/ex12/ROM.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480419395791 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419395791 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex12.v 1 1 " "Found 1 design units, including 1 entities, in source file ex12.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex12 " "Found entity 1: ex12" {  } { { "ex12.v" "" { Text "C:/New folder/ex12/ex12.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480419395792 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419395792 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex12 " "Elaborating entity \"ex12\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480419395832 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:r " "Elaborating entity \"ROM\" for hierarchy \"ROM:r\"" {  } { { "ex12.v" "r" { Text "C:/New folder/ex12/ex12.v" 9 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480419395844 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ROM:r\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ROM:r\|altsyncram:altsyncram_component\"" {  } { { "ROM.v" "altsyncram_component" { Text "C:/New folder/ex12/ROM.v" 82 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480419395884 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "ROM:r\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ROM:r\|altsyncram:altsyncram_component\"" {  } { { "ROM.v" "" { Text "C:/New folder/ex12/ROM.v" 82 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480419395885 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ROM:r\|altsyncram:altsyncram_component " "Instantiated megafunction \"ROM:r\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom_data/rom_data.mif " "Parameter \"init_file\" = \"./rom_data/rom_data.mif\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 10 " "Parameter \"width_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419395885 ""}  } { { "ROM.v" "" { Text "C:/New folder/ex12/ROM.v" 82 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1480419395885 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6ng1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_6ng1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6ng1 " "Found entity 1: altsyncram_6ng1" {  } { { "db/altsyncram_6ng1.tdf" "" { Text "C:/New folder/ex12/db/altsyncram_6ng1.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480419395930 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419395930 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_6ng1 ROM:r\|altsyncram:altsyncram_component\|altsyncram_6ng1:auto_generated " "Elaborating entity \"altsyncram_6ng1\" for hierarchy \"ROM:r\|altsyncram:altsyncram_component\|altsyncram_6ng1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480419395930 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:h0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:h0\"" {  } { { "ex12.v" "h0" { Text "C:/New folder/ex12/ex12.v" 11 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480419395933 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "ex12.v" "" { Text "C:/New folder/ex12/ex12.v" 5 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480419396324 "|ex12|HEX2[1]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480419396324 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480419396394 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480419396659 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480419396659 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "59 " "Implemented 59 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480419396694 ""} { "Info" "ICUT_CUT_TM_OPINS" "21 " "Implemented 21 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480419396694 ""} { "Info" "ICUT_CUT_TM_LCELLS" "17 " "Implemented 17 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480419396694 ""} { "Info" "ICUT_CUT_TM_RAMS" "10 " "Implemented 10 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1480419396694 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480419396694 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "892 " "Peak virtual memory: 892 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480419396705 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:36:36 2016 " "Processing ended: Tue Nov 29 11:36:36 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480419396705 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480419396705 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480419396705 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419396705 ""}
diff --git a/part_3/ex12/db/ex12.map.rdb b/part_3/ex12/db/ex12.map.rdb
new file mode 100755
index 0000000..7b16dc0
--- /dev/null
+++ b/part_3/ex12/db/ex12.map.rdb
diff --git a/part_3/ex12/db/ex12.map_bb.cdb b/part_3/ex12/db/ex12.map_bb.cdb
new file mode 100755
index 0000000..4db4903
--- /dev/null
+++ b/part_3/ex12/db/ex12.map_bb.cdb
diff --git a/part_3/ex12/db/ex12.map_bb.hdb b/part_3/ex12/db/ex12.map_bb.hdb
new file mode 100755
index 0000000..c5f7e51
--- /dev/null
+++ b/part_3/ex12/db/ex12.map_bb.hdb
diff --git a/part_3/ex12/db/ex12.map_bb.logdb b/part_3/ex12/db/ex12.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_3/ex12/db/ex12.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_3/ex12/db/ex12.pre_map.hdb b/part_3/ex12/db/ex12.pre_map.hdb
new file mode 100755
index 0000000..5d548ab
--- /dev/null
+++ b/part_3/ex12/db/ex12.pre_map.hdb
diff --git a/part_3/ex12/db/ex12.root_partition.map.reg_db.cdb b/part_3/ex12/db/ex12.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..9b9e043
--- /dev/null
+++ b/part_3/ex12/db/ex12.root_partition.map.reg_db.cdb
diff --git a/part_3/ex12/db/ex12.routing.rdb b/part_3/ex12/db/ex12.routing.rdb
new file mode 100755
index 0000000..bcbc185
--- /dev/null
+++ b/part_3/ex12/db/ex12.routing.rdb
diff --git a/part_3/ex12/db/ex12.rtlv.hdb b/part_3/ex12/db/ex12.rtlv.hdb
new file mode 100755
index 0000000..ae6d089
--- /dev/null
+++ b/part_3/ex12/db/ex12.rtlv.hdb
diff --git a/part_3/ex12/db/ex12.rtlv_sg.cdb b/part_3/ex12/db/ex12.rtlv_sg.cdb
new file mode 100755
index 0000000..afc708e
--- /dev/null
+++ b/part_3/ex12/db/ex12.rtlv_sg.cdb
diff --git a/part_3/ex12/db/ex12.rtlv_sg_swap.cdb b/part_3/ex12/db/ex12.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..20ded6b
--- /dev/null
+++ b/part_3/ex12/db/ex12.rtlv_sg_swap.cdb
diff --git a/part_3/ex12/db/ex12.sld_design_entry.sci b/part_3/ex12/db/ex12.sld_design_entry.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_3/ex12/db/ex12.sld_design_entry.sci
diff --git a/part_3/ex12/db/ex12.sld_design_entry_dsc.sci b/part_3/ex12/db/ex12.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_3/ex12/db/ex12.sld_design_entry_dsc.sci
diff --git a/part_3/ex12/db/ex12.smart_action.txt b/part_3/ex12/db/ex12.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_3/ex12/db/ex12.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/part_3/ex12/db/ex12.sta.qmsg b/part_3/ex12/db/ex12.sta.qmsg
new file mode 100755
index 0000000..39acff1
--- /dev/null
+++ b/part_3/ex12/db/ex12.sta.qmsg
@@ -0,0 +1,52 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480419434378 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480419434379 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:37:13 2016 " "Processing started: Tue Nov 29 11:37:13 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480419434379 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419434379 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex12 -c ex12 " "Command: quartus_sta ex12 -c ex12" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419434379 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480419434501 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435025 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435025 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435071 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435071 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex12.sdc " "Synopsys Design Constraints File file not found: 'ex12.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435587 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435587 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480419435587 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435587 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435588 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435588 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480419435589 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480419435596 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480419435602 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435602 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.105 " "Worst-case setup slack is -1.105" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419435603 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419435603 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.105             -11.022 CLOCK_50  " "   -1.105             -11.022 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419435603 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435603 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.721 " "Worst-case hold slack is 0.721" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419435605 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419435605 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.721               0.000 CLOCK_50  " "    0.721               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419435605 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435605 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435607 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435608 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419435610 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419435610 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174             -68.175 CLOCK_50  " "   -2.174             -68.175 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419435610 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435610 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480419435619 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419435652 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419436452 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419436489 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480419436492 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419436492 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.137 " "Worst-case setup slack is -1.137" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419436493 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419436493 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.137             -11.339 CLOCK_50  " "   -1.137             -11.339 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419436493 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419436493 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.752 " "Worst-case hold slack is 0.752" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419436495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419436495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.752               0.000 CLOCK_50  " "    0.752               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419436495 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419436495 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419436497 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419436498 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419436499 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419436499 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174             -67.971 CLOCK_50  " "   -2.174             -67.971 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419436499 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419436499 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480419436508 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419436649 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437336 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437368 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480419437369 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437369 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.257 " "Worst-case setup slack is -0.257" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.257              -2.544 CLOCK_50  " "   -0.257              -2.544 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437370 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437370 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.431 " "Worst-case hold slack is 0.431" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437372 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437372 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.431               0.000 CLOCK_50  " "    0.431               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437372 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437372 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437374 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437376 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174             -69.669 CLOCK_50  " "   -2.174             -69.669 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437377 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437377 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480419437385 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437519 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480419437520 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437520 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.238 " "Worst-case setup slack is -0.238" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.238              -2.357 CLOCK_50  " "   -0.238              -2.357 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437521 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437521 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.425 " "Worst-case hold slack is 0.425" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.425               0.000 CLOCK_50  " "    0.425               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437523 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437523 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437525 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437526 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174             -70.932 CLOCK_50  " "   -2.174             -70.932 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419437528 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419437528 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419438813 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419438813 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1205 " "Peak virtual memory: 1205 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480419438849 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:37:18 2016 " "Processing ended: Tue Nov 29 11:37:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480419438849 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480419438849 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480419438849 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419438849 ""}
diff --git a/part_3/ex12/db/ex12.sta.rdb b/part_3/ex12/db/ex12.sta.rdb
new file mode 100755
index 0000000..c66075e
--- /dev/null
+++ b/part_3/ex12/db/ex12.sta.rdb
diff --git a/part_3/ex12/db/ex12.sta_cmp.6_slow_1100mv_85c.tdb b/part_3/ex12/db/ex12.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..42a2ff7
--- /dev/null
+++ b/part_3/ex12/db/ex12.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_3/ex12/db/ex12.tis_db_list.ddb b/part_3/ex12/db/ex12.tis_db_list.ddb
new file mode 100755
index 0000000..88225e8
--- /dev/null
+++ b/part_3/ex12/db/ex12.tis_db_list.ddb
diff --git a/part_3/ex12/db/ex12.tiscmp.fast_1100mv_0c.ddb b/part_3/ex12/db/ex12.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..58917da
--- /dev/null
+++ b/part_3/ex12/db/ex12.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_3/ex12/db/ex12.tiscmp.fast_1100mv_85c.ddb b/part_3/ex12/db/ex12.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..c47eeec
--- /dev/null
+++ b/part_3/ex12/db/ex12.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_3/ex12/db/ex12.tiscmp.slow_1100mv_0c.ddb b/part_3/ex12/db/ex12.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..c430153
--- /dev/null
+++ b/part_3/ex12/db/ex12.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_3/ex12/db/ex12.tiscmp.slow_1100mv_85c.ddb b/part_3/ex12/db/ex12.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..9601b60
--- /dev/null
+++ b/part_3/ex12/db/ex12.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_3/ex12/db/ex12.tmw_info b/part_3/ex12/db/ex12.tmw_info
new file mode 100755
index 0000000..5e2d523
--- /dev/null
+++ b/part_3/ex12/db/ex12.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:53
+start_analysis_synthesis:s:00:00:11-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:29-start_full_compilation
+start_assembler:s:00:00:07-start_full_compilation
+start_timing_analyzer:s:00:00:06-start_full_compilation
diff --git a/part_3/ex12/db/ex12.vpr.ammdb b/part_3/ex12/db/ex12.vpr.ammdb
new file mode 100755
index 0000000..8d9dbac
--- /dev/null
+++ b/part_3/ex12/db/ex12.vpr.ammdb
diff --git a/part_3/ex12/db/ex12_partition_pins.json b/part_3/ex12/db/ex12_partition_pins.json
new file mode 100755
index 0000000..dc6f039
--- /dev/null
+++ b/part_3/ex12/db/ex12_partition_pins.json
@@ -0,0 +1,133 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "HEX0[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "CLOCK_50",
+					"strict" : false
+				},
+				{
+					"name" : "SW[0]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[1]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[2]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[3]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[4]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[5]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[6]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[7]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[8]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[9]",
+					"strict" : false
+				}
+			]
+		}
+	]
+}
+\ No newline at end of file
diff --git a/part_3/ex12/db/prev_cmp_ex12.qmsg b/part_3/ex12/db/prev_cmp_ex12.qmsg
new file mode 100755
index 0000000..fc3167f
--- /dev/null
+++ b/part_3/ex12/db/prev_cmp_ex12.qmsg
@@ -0,0 +1,132 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480419188594 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480419188596 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:33:08 2016 " "Processing started: Tue Nov 29 11:33:08 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480419188596 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419188596 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex12 -c ex12 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex12 -c ex12" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419188596 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480419189086 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480419189086 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex12/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480419197563 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419197563 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom.v 1 1 " "Found 1 design units, including 1 entities, in source file rom.v" { { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" {  } { { "ROM.v" "" { Text "C:/New folder/ex12/ROM.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480419197565 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419197565 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex12.v 1 1 " "Found 1 design units, including 1 entities, in source file ex12.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex12 " "Found entity 1: ex12" {  } { { "ex12.v" "" { Text "C:/New folder/ex12/ex12.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480419197566 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419197566 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex12 " "Elaborating entity \"ex12\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480419197603 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:r " "Elaborating entity \"ROM\" for hierarchy \"ROM:r\"" {  } { { "ex12.v" "r" { Text "C:/New folder/ex12/ex12.v" 9 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480419197613 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ROM:r\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ROM:r\|altsyncram:altsyncram_component\"" {  } { { "ROM.v" "altsyncram_component" { Text "C:/New folder/ex12/ROM.v" 82 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480419197655 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "ROM:r\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ROM:r\|altsyncram:altsyncram_component\"" {  } { { "ROM.v" "" { Text "C:/New folder/ex12/ROM.v" 82 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480419197656 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ROM:r\|altsyncram:altsyncram_component " "Instantiated megafunction \"ROM:r\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom_data/rom_data.mif " "Parameter \"init_file\" = \"./rom_data/rom_data.mif\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 10 " "Parameter \"width_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480419197656 ""}  } { { "ROM.v" "" { Text "C:/New folder/ex12/ROM.v" 82 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1480419197656 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6ng1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_6ng1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6ng1 " "Found entity 1: altsyncram_6ng1" {  } { { "db/altsyncram_6ng1.tdf" "" { Text "C:/New folder/ex12/db/altsyncram_6ng1.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480419197699 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419197699 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_6ng1 ROM:r\|altsyncram:altsyncram_component\|altsyncram_6ng1:auto_generated " "Elaborating entity \"altsyncram_6ng1\" for hierarchy \"ROM:r\|altsyncram:altsyncram_component\|altsyncram_6ng1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480419197699 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:h0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:h0\"" {  } { { "ex12.v" "h0" { Text "C:/New folder/ex12/ex12.v" 11 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480419197702 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480419198081 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480419198164 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480419198428 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480419198428 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "63 " "Implemented 63 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480419198462 ""} { "Info" "ICUT_CUT_TM_OPINS" "21 " "Implemented 21 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480419198462 ""} { "Info" "ICUT_CUT_TM_LCELLS" "21 " "Implemented 21 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480419198462 ""} { "Info" "ICUT_CUT_TM_RAMS" "10 " "Implemented 10 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1480419198462 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480419198462 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "890 " "Peak virtual memory: 890 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480419198473 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:33:18 2016 " "Processing ended: Tue Nov 29 11:33:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480419198473 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480419198473 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480419198473 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480419198473 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1480419199915 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480419199916 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:33:19 2016 " "Processing started: Tue Nov 29 11:33:19 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480419199916 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1480419199916 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex12 -c ex12 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex12 -c ex12" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1480419199917 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1480419200036 ""}
+{ "Info" "0" "" "Project  = ex12" {  } {  } 0 0 "Project  = ex12" 0 0 "Fitter" 0 0 1480419200037 ""}
+{ "Info" "0" "" "Revision = ex12" {  } {  } 0 0 "Revision = ex12" 0 0 "Fitter" 0 0 1480419200037 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480419200159 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480419200160 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex12 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex12\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480419200420 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480419200495 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480419200495 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480419200878 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480419201009 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1480419201010 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480419210852 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 10 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 10 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480419210921 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480419210921 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480419210922 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480419210924 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480419210924 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480419210924 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480419210925 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480419210925 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480419210925 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480419210925 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480419210926 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480419210926 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480419210956 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480419210956 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:09 " "Fitter preparation operations ending: elapsed time is 00:00:09" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480419210958 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex12.sdc " "Synopsys Design Constraints File file not found: 'ex12.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480419216614 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480419216614 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480419216616 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480419216616 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480419216617 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480419216619 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480419216691 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480419217185 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480419217582 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480419217840 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480419217840 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480419218718 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y11 X89_Y22 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22" {  } { { "loc" "" { Generic "C:/New folder/ex12/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22"} { { 12 { 0 ""} 78 11 12 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480419223161 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480419223161 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480419223351 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1480419223351 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480419223351 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480419223354 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480419224372 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480419224408 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480419224728 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480419224728 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480419225037 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480419227156 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480419227384 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex12/output_files/ex12.fit.smsg " "Generated suppressed messages file C:/New folder/ex12/output_files/ex12.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480419227432 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 54 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 54 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2589 " "Peak virtual memory: 2589 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480419227818 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:33:47 2016 " "Processing ended: Tue Nov 29 11:33:47 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480419227818 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480419227818 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:49 " "Total CPU time (on all processors): 00:00:49" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480419227818 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480419227818 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1480419229152 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480419229155 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:33:48 2016 " "Processing started: Tue Nov 29 11:33:48 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480419229155 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480419229155 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex12 -c ex12 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex12 -c ex12" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480419229155 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480419229930 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480419234451 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "891 " "Peak virtual memory: 891 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480419234794 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:33:54 2016 " "Processing ended: Tue Nov 29 11:33:54 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480419234794 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480419234794 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480419234794 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480419234794 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1480419235437 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1480419236232 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480419236233 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:33:55 2016 " "Processing started: Tue Nov 29 11:33:55 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480419236233 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419236233 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex12 -c ex12 " "Command: quartus_sta ex12 -c ex12" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419236233 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480419236356 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419236878 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419236878 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419236925 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419236925 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex12.sdc " "Synopsys Design Constraints File file not found: 'ex12.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419237438 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419237438 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480419237439 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419237439 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419237439 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419237440 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480419237441 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480419237448 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480419237453 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419237453 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.105 " "Worst-case setup slack is -1.105" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419237454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419237454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.105             -11.022 CLOCK_50  " "   -1.105             -11.022 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419237454 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419237454 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.721 " "Worst-case hold slack is 0.721" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419237456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419237456 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.721               0.000 CLOCK_50  " "    0.721               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419237456 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419237456 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419237458 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419237459 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419237460 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419237460 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174             -68.153 CLOCK_50  " "   -2.174             -68.153 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419237460 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419237460 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480419237470 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419237502 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419238303 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419238337 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480419238340 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419238340 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.137 " "Worst-case setup slack is -1.137" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419238341 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419238341 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.137             -11.339 CLOCK_50  " "   -1.137             -11.339 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419238341 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419238341 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.752 " "Worst-case hold slack is 0.752" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419238343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419238343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.752               0.000 CLOCK_50  " "    0.752               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419238343 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419238343 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419238345 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419238346 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419238347 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419238347 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174             -68.015 CLOCK_50  " "   -2.174             -68.015 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419238347 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419238347 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480419238356 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419238500 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239189 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239224 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480419239224 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239224 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.257 " "Worst-case setup slack is -0.257" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.257              -2.544 CLOCK_50  " "   -0.257              -2.544 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239226 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239226 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.431 " "Worst-case hold slack is 0.431" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239228 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239228 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.431               0.000 CLOCK_50  " "    0.431               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239228 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239228 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239229 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239231 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239232 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239232 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174             -69.738 CLOCK_50  " "   -2.174             -69.738 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239232 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239232 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480419239241 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239375 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480419239376 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239376 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.238 " "Worst-case setup slack is -0.238" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.238              -2.357 CLOCK_50  " "   -0.238              -2.357 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239377 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239377 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.425 " "Worst-case hold slack is 0.425" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.425               0.000 CLOCK_50  " "    0.425               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239379 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239379 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239381 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239383 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239384 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239384 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174             -71.001 CLOCK_50  " "   -2.174             -71.001 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480419239384 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419239384 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419240642 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419240642 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1205 " "Peak virtual memory: 1205 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480419240679 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:34:00 2016 " "Processing ended: Tue Nov 29 11:34:00 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480419240679 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480419240679 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480419240679 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419240679 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 63 s " "Quartus Prime Full Compilation was successful. 0 errors, 63 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480419241411 ""}
diff --git a/part_3/ex12/ex12.qpf b/part_3/ex12/ex12.qpf
new file mode 100755
index 0000000..dd153a7
--- /dev/null
+++ b/part_3/ex12/ex12.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 11:12:25  November 29, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "16.0"
+DATE = "11:12:25  November 29, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ex12"
diff --git a/part_3/ex12/ex12.qsf b/part_3/ex12/ex12.qsf
new file mode 100755
index 0000000..4f64369
--- /dev/null
+++ b/part_3/ex12/ex12.qsf
@@ -0,0 +1,268 @@
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 11:12:25  November 29, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ex12_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex12
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:12:25  NOVEMBER 29, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name QIP_FILE ROM.qip
+set_global_assignment -name VERILOG_FILE ex12.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+\ No newline at end of file
diff --git a/part_3/ex12/ex12.qsf.bak b/part_3/ex12/ex12.qsf.bak
new file mode 100755
index 0000000..4fb3c5d
--- /dev/null
+++ b/part_3/ex12/ex12.qsf.bak
@@ -0,0 +1,58 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 11:12:25  November 29, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ex12_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex12
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:12:25  NOVEMBER 29, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name QIP_FILE ROM.qip
+set_global_assignment -name VERILOG_FILE ex12.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+\ No newline at end of file
diff --git a/part_3/ex12/ex12.qws b/part_3/ex12/ex12.qws
new file mode 100755
index 0000000..7d460fe
--- /dev/null
+++ b/part_3/ex12/ex12.qws
diff --git a/part_3/ex12/ex12.v b/part_3/ex12/ex12.v
new file mode 100755
index 0000000..f501504
--- /dev/null
+++ b/part_3/ex12/ex12.v
@@ -0,0 +1,15 @@
+module ex12(CLOCK_50, SW, HEX0, HEX1, HEX2);
+
+	input CLOCK_50;
+	input [9:0] SW;
+	output [6:0] HEX0, HEX1, HEX2;
+	
+	wire[9:0] data;
+
+	ROM r(SW, CLOCK_50, data);
+
+	hex_to_7seg h0(HEX0, data[3:0]);
+	hex_to_7seg h1(HEX1, data[7:4]);
+	hex_to_7seg h2(HEX2, {2'b0, data[9:8]});
+
+endmodule
+\ No newline at end of file
diff --git a/part_3/ex12/ex12.v.bak b/part_3/ex12/ex12.v.bak
new file mode 100755
index 0000000..68ae602
--- /dev/null
+++ b/part_3/ex12/ex12.v.bak
@@ -0,0 +1 @@
+module 
+\ No newline at end of file
diff --git a/part_3/ex12/greybox_tmp/cbx_args.txt b/part_3/ex12/greybox_tmp/cbx_args.txt
new file mode 100755
index 0000000..b101ec9
--- /dev/null
+++ b/part_3/ex12/greybox_tmp/cbx_args.txt
@@ -0,0 +1,16 @@
+ADDRESS_ACLR_A=NONE
+CLOCK_ENABLE_INPUT_A=BYPASS
+CLOCK_ENABLE_OUTPUT_A=BYPASS
+INIT_FILE=./rom_data/rom_data.mif
+INTENDED_DEVICE_FAMILY="Cyclone V"
+NUMWORDS_A=1024
+OPERATION_MODE=ROM
+OUTDATA_ACLR_A=NONE
+OUTDATA_REG_A=CLOCK0
+WIDTHAD_A=10
+WIDTH_A=10
+WIDTH_BYTEENA_A=1
+DEVICE_FAMILY="Cyclone V"
+address_a
+clock0
+q_a
diff --git a/part_3/ex12/incremental_db/README b/part_3/ex12/incremental_db/README
new file mode 100755
index 0000000..6191fbe
--- /dev/null
+++ b/part_3/ex12/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.db_info b/part_3/ex12/incremental_db/compiled_partitions/ex12.db_info
new file mode 100755
index 0000000..1287d4c
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 29 11:29:33 2016
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.ammdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.ammdb
new file mode 100755
index 0000000..6e8db67
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.ammdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.cdb
new file mode 100755
index 0000000..e91a50c
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.cdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.dfp b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.dfp
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.hbdb.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..35b7e53
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.hbdb.cdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.hbdb.hdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..fe0a2d8
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.hbdb.hdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.hbdb.sig b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
+\ No newline at end of file
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.hdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.hdb
new file mode 100755
index 0000000..504accf
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.hdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.logdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.rcfdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..15be7b4
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.cmp.rcfdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.cdb
new file mode 100755
index 0000000..a6298f2
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.cdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.dpi b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.dpi
new file mode 100755
index 0000000..f003e73
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.dpi
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hbdb.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..6953d6a
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hbdb.cdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hbdb.hb_info b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hbdb.hb_info
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hbdb.hdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..5feaaf6
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hbdb.hdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hbdb.sig b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
+\ No newline at end of file
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hdb
new file mode 100755
index 0000000..7ab9d5b
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.hdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.kpt b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.kpt
new file mode 100755
index 0000000..901e338
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.kpt
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.olf.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.olf.cdb
new file mode 100755
index 0000000..711883f
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.olf.cdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.olm.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.olm.cdb
new file mode 100755
index 0000000..33ccc91
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.olm.cdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.oln.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.oln.cdb
new file mode 100755
index 0000000..6ada719
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.oln.cdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.opi b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.opi
@@ -0,0 +1 @@
+1
+\ No newline at end of file
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.orf.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.orf.cdb
new file mode 100755
index 0000000..711883f
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.orf.cdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.orm.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.orm.cdb
new file mode 100755
index 0000000..84bcb9f
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.orm.cdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.orn.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.orn.cdb
new file mode 100755
index 0000000..e0e41a9
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.map.orn.cdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.cdb
new file mode 100755
index 0000000..a6298f2
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.cdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.hbdb.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.hbdb.cdb
new file mode 100755
index 0000000..6953d6a
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.hbdb.cdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.hbdb.hdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..5feaaf6
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.hbdb.hdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.hdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.hdb
new file mode 100755
index 0000000..7ab9d5b
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.hdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.kpt b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.kpt
new file mode 100755
index 0000000..901e338
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.root_partition.rrp.kpt
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.rrp.hdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.rrp.hdb
new file mode 100755
index 0000000..1b8446c
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.rrp.hdb
diff --git a/part_3/ex12/incremental_db/compiled_partitions/ex12.rrs.cdb b/part_3/ex12/incremental_db/compiled_partitions/ex12.rrs.cdb
new file mode 100755
index 0000000..0fb10f0
--- /dev/null
+++ b/part_3/ex12/incremental_db/compiled_partitions/ex12.rrs.cdb
diff --git a/part_3/ex12/output_files/ex12.asm.rpt b/part_3/ex12/output_files/ex12.asm.rpt
new file mode 100755
index 0000000..57a7eb4
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for ex12
+Tue Nov 29 11:37:12 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/New folder/ex12/output_files/ex12.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Nov 29 11:37:12 2016 ;
+; Revision Name         ; ex12                                  ;
+; Top-level Entity Name ; ex12                                  ;
+; Family                ; Cyclone V                             ;
+; Device                ; 5CSEMA5F31C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++------------------------------------------+
+; Assembler Generated Files                ;
++------------------------------------------+
+; File Name                                ;
++------------------------------------------+
+; C:/New folder/ex12/output_files/ex12.sof ;
++------------------------------------------+
+
+
++--------------------------------------------------------------------+
+; Assembler Device Options: C:/New folder/ex12/output_files/ex12.sof ;
++----------------+---------------------------------------------------+
+; Option         ; Setting                                           ;
++----------------+---------------------------------------------------+
+; Device         ; 5CSEMA5F31C6                                      ;
+; JTAG usercode  ; 0x00B24C2F                                        ;
+; Checksum       ; 0x00B24C2F                                        ;
++----------------+---------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Tue Nov 29 11:37:06 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex12 -c ex12
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 892 megabytes
+    Info: Processing ended: Tue Nov 29 11:37:12 2016
+    Info: Elapsed time: 00:00:06
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_3/ex12/output_files/ex12.done b/part_3/ex12/output_files/ex12.done
new file mode 100755
index 0000000..d7d2ef8
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.done
@@ -0,0 +1 @@
+Tue Nov 29 11:37:19 2016
diff --git a/part_3/ex12/output_files/ex12.fit.rpt b/part_3/ex12/output_files/ex12.fit.rpt
new file mode 100755
index 0000000..3781ab8
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.fit.rpt
@@ -0,0 +1,1952 @@
+Fitter report for ex12
+Tue Nov 29 11:37:05 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Fitter Netlist Optimizations
+  7. Ignored Assignments
+  8. Incremental Compilation Preservation Summary
+  9. Incremental Compilation Partition Settings
+ 10. Incremental Compilation Placement Preservation
+ 11. Pin-Out File
+ 12. Fitter Resource Usage Summary
+ 13. Fitter Partition Statistics
+ 14. Input Pins
+ 15. Output Pins
+ 16. I/O Bank Usage
+ 17. All Package Pins
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Fitter RAM Summary
+ 24. Routing Usage Summary
+ 25. I/O Rules Summary
+ 26. I/O Rules Details
+ 27. I/O Rules Matrix
+ 28. Fitter Device Options
+ 29. Operating Settings and Conditions
+ 30. Fitter Messages
+ 31. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary                                                                    ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status                   ; Successful - Tue Nov 29 11:37:05 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex12                                            ;
+; Top-level Entity Name           ; ex12                                            ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 9 / 32,070 ( < 1 % )                            ;
+; Total registers                 ; 0                                               ;
+; Total pins                      ; 32 / 457 ( 7 % )                                ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 10,240 / 4,065,280 ( < 1 % )                    ;
+; Total RAM Blocks                ; 1 / 397 ( < 1 % )                               ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Clamping Diode                                                             ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.01        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.2%      ;
+;     Processor 3            ;   0.2%      ;
+;     Processor 4            ;   0.2%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings                         ;
++----------+--------------------------------------+
+; Pin Name ; Reason                               ;
++----------+--------------------------------------+
+; HEX0[0]  ; Missing drive strength and slew rate ;
+; HEX0[1]  ; Missing drive strength and slew rate ;
+; HEX0[2]  ; Missing drive strength and slew rate ;
+; HEX0[3]  ; Missing drive strength and slew rate ;
+; HEX0[4]  ; Missing drive strength and slew rate ;
+; HEX0[5]  ; Missing drive strength and slew rate ;
+; HEX0[6]  ; Missing drive strength and slew rate ;
+; HEX1[0]  ; Missing drive strength and slew rate ;
+; HEX1[1]  ; Missing drive strength and slew rate ;
+; HEX1[2]  ; Missing drive strength and slew rate ;
+; HEX1[3]  ; Missing drive strength and slew rate ;
+; HEX1[4]  ; Missing drive strength and slew rate ;
+; HEX1[5]  ; Missing drive strength and slew rate ;
+; HEX1[6]  ; Missing drive strength and slew rate ;
+; HEX2[0]  ; Missing drive strength and slew rate ;
+; HEX2[1]  ; Missing drive strength and slew rate ;
+; HEX2[2]  ; Missing drive strength and slew rate ;
+; HEX2[3]  ; Missing drive strength and slew rate ;
+; HEX2[4]  ; Missing drive strength and slew rate ;
+; HEX2[5]  ; Missing drive strength and slew rate ;
+; HEX2[6]  ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                        ;
++-----------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+
+; Node                  ; Action  ; Operation ; Reason                     ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
++-----------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ;           ;                ;                  ;                  ;                       ;
++-----------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                        ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[0]    ; PIN_AD26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[1]    ; PIN_AC27      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[2]    ; PIN_AD25      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[3]    ; PIN_AC25      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[4]    ; PIN_AB28      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[5]    ; PIN_AB25      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[6]    ; PIN_AB22      ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[0]    ; PIN_AA24      ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[1]    ; PIN_Y23       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[2]    ; PIN_Y24       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[3]    ; PIN_W22       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[4]    ; PIN_W24       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[5]    ; PIN_V23       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[6]    ; PIN_W25       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[0]     ; PIN_AA14      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[1]     ; PIN_AA15      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[2]     ; PIN_W15       ; QSF Assignment ;
+; Location     ;                ;              ; KEY[3]     ; PIN_Y16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[0]    ; PIN_V16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[1]    ; PIN_W16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[2]    ; PIN_V17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[3]    ; PIN_V18       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[4]    ; PIN_W17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[5]    ; PIN_W19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[6]    ; PIN_Y19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[7]    ; PIN_W20       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[8]    ; PIN_W21       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[9]    ; PIN_Y21       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
+; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX3[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX3[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX3[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX3[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX3[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX3[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX3[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX4[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX4[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX4[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX4[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX4[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX4[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX4[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; KEY[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; KEY[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; KEY[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; KEY[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; LEDR[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; LEDR[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; LEDR[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; LEDR[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; LEDR[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; LEDR[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; LEDR[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; LEDR[7]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; LEDR[8]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; LEDR[9]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex12           ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                    ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]     ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Placement (by node) ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 93 ) ; 0.00 % ( 0 / 93 )          ; 0.00 % ( 0 / 93 )        ;
+;     -- Achieved     ; 0.00 % ( 0 / 93 ) ; 0.00 % ( 0 / 93 )          ; 0.00 % ( 0 / 93 )        ;
+;                     ;                   ;                            ;                          ;
+; Routing (by net)    ;                   ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )  ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+-------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 93 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/New folder/ex12/output_files/ex12.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                                            ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource                                                    ; Usage              ; %     ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 9 / 32,070         ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 9                  ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 9 / 32,070         ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 0                  ;       ;
+;         [b] ALMs used for LUT logic                         ; 9                  ;       ;
+;         [c] ALMs used for registers                         ; 0                  ;       ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 32,070         ; 0 %   ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
+;         [a] Due to location constrained logic               ; 0                  ;       ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
+;         [c] Due to LAB input limits                         ; 0                  ;       ;
+;         [d] Due to virtual I/Os                             ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Difficulty packing design                                   ; Low                ;       ;
+;                                                             ;                    ;       ;
+; Total LABs:  partially or completely used                   ; 4 / 3,207          ; < 1 % ;
+;     -- Logic LABs                                           ; 4                  ;       ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Combinational ALUT usage for logic                          ; 18                 ;       ;
+;     -- 7 input functions                                    ; 0                  ;       ;
+;     -- 6 input functions                                    ; 0                  ;       ;
+;     -- 5 input functions                                    ; 0                  ;       ;
+;     -- 4 input functions                                    ; 14                 ;       ;
+;     -- <=3 input functions                                  ; 4                  ;       ;
+; Combinational ALUT usage for route-throughs                 ; 0                  ;       ;
+; Dedicated logic registers                                   ; 0                  ;       ;
+;     -- By type:                                             ;                    ;       ;
+;         -- Primary logic registers                          ; 0 / 64,140         ; 0 %   ;
+;         -- Secondary logic registers                        ; 0 / 64,140         ; 0 %   ;
+;     -- By function:                                         ;                    ;       ;
+;         -- Design implementation registers                  ; 0                  ;       ;
+;         -- Routing optimization registers                   ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Virtual pins                                                ; 0                  ;       ;
+; I/O pins                                                    ; 32 / 457           ; 7 %   ;
+;     -- Clock pins                                           ; 1 / 8              ; 13 %  ;
+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Hard processor system peripheral utilization                ;                    ;       ;
+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
+;                                                             ;                    ;       ;
+; Global signals                                              ; 1                  ;       ;
+; M10K blocks                                                 ; 1 / 397            ; < 1 % ;
+; Total MLAB memory bits                                      ; 0                  ;       ;
+; Total block memory bits                                     ; 10,240 / 4,065,280 ; < 1 % ;
+; Total block memory implementation bits                      ; 10,240 / 4,065,280 ; < 1 % ;
+;                                                             ;                    ;       ;
+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
+; Global clocks                                               ; 1 / 16             ; 6 %   ;
+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;
+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;
+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
+; JTAGs                                                       ; 0 / 1              ; 0 %   ;
+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
+; Average interconnect usage (total/H/V)                      ; 0.0% / 0.0% / 0.0% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 0.3% / 0.3% / 0.5% ;       ;
+; Maximum fan-out                                             ; 64                 ;       ;
+; Highest non-global fan-out                                  ; 7                  ;       ;
+; Total fan-out                                               ; 81                 ;       ;
+; Average fan-out                                             ; 0.96               ;       ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                                        ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+; Statistic                                                   ; Top                 ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 9 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 9                   ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 9 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 0                   ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 9                   ; 0                              ;
+;         [c] ALMs used for registers                         ; 0                   ; 0                              ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                   ; 0                              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 0 / 32070 ( 0 % )   ; 0 / 32070 ( 0 % )              ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )   ; 0 / 32070 ( 0 % )              ;
+;         [a] Due to location constrained logic               ; 0                   ; 0                              ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                   ; 0                              ;
+;         [c] Due to LAB input limits                         ; 0                   ; 0                              ;
+;         [d] Due to virtual I/Os                             ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Difficulty packing design                                   ; Low                 ; Low                            ;
+;                                                             ;                     ;                                ;
+; Total LABs:  partially or completely used                   ; 4 / 3207 ( < 1 % )  ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 4                   ; 0                              ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Combinational ALUT usage for logic                          ; 18                  ; 0                              ;
+;     -- 7 input functions                                    ; 0                   ; 0                              ;
+;     -- 6 input functions                                    ; 0                   ; 0                              ;
+;     -- 5 input functions                                    ; 0                   ; 0                              ;
+;     -- 4 input functions                                    ; 14                  ; 0                              ;
+;     -- <=3 input functions                                  ; 4                   ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 0                   ; 0                              ;
+; Memory ALUT usage                                           ; 0                   ; 0                              ;
+;     -- 64-address deep                                      ; 0                   ; 0                              ;
+;     -- 32-address deep                                      ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Dedicated logic registers                                   ; 0                   ; 0                              ;
+;     -- By type:                                             ;                     ;                                ;
+;         -- Primary logic registers                          ; 0 / 64140 ( 0 % )   ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 0 / 64140 ( 0 % )   ; 0 / 64140 ( 0 % )              ;
+;     -- By function:                                         ;                     ;                                ;
+;         -- Design implementation registers                  ; 0                   ; 0                              ;
+;         -- Routing optimization registers                   ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+;                                                             ;                     ;                                ;
+; Virtual pins                                                ; 0                   ; 0                              ;
+; I/O pins                                                    ; 32                  ; 0                              ;
+; I/O registers                                               ; 0                   ; 0                              ;
+; Total block memory bits                                     ; 10240               ; 0                              ;
+; Total block memory implementation bits                      ; 10240               ; 0                              ;
+; M10K block                                                  ; 1 / 397 ( < 1 % )   ; 0 / 397 ( 0 % )                ;
+; Clock enable block                                          ; 1 / 116 ( < 1 % )   ; 0 / 116 ( 0 % )                ;
+;                                                             ;                     ;                                ;
+; Connections                                                 ;                     ;                                ;
+;     -- Input Connections                                    ; 0                   ; 0                              ;
+;     -- Registered Input Connections                         ; 0                   ; 0                              ;
+;     -- Output Connections                                   ; 0                   ; 0                              ;
+;     -- Registered Output Connections                        ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Internal Connections                                        ;                     ;                                ;
+;     -- Total Connections                                    ; 126                 ; 0                              ;
+;     -- Registered Connections                               ; 64                  ; 0                              ;
+;                                                             ;                     ;                                ;
+; External Connections                                        ;                     ;                                ;
+;     -- Top                                                  ; 0                   ; 0                              ;
+;     -- hard_block:auto_generated_inst                       ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Partition Interface                                         ;                     ;                                ;
+;     -- Input Ports                                          ; 11                  ; 0                              ;
+;     -- Output Ports                                         ; 21                  ; 0                              ;
+;     -- Bidir Ports                                          ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Registered Ports                                            ;                     ;                                ;
+;     -- Registered Input Ports                               ; 0                   ; 0                              ;
+;     -- Registered Output Ports                              ; 0                   ; 0                              ;
+;                                                             ;                     ;                                ;
+; Port Connectivity                                           ;                     ;                                ;
+;     -- Input Ports driven by GND                            ; 0                   ; 0                              ;
+;     -- Output Ports driven by GND                           ; 0                   ; 0                              ;
+;     -- Input Ports driven by VCC                            ; 0                   ; 0                              ;
+;     -- Output Ports driven by VCC                           ; 0                   ; 0                              ;
+;     -- Input Ports with no Source                           ; 0                   ; 0                              ;
+;     -- Output Ports with no Source                          ; 0                   ; 0                              ;
+;     -- Input Ports with no Fanout                           ; 0                   ; 0                              ;
+;     -- Output Ports with no Fanout                          ; 0                   ; 0                              ;
++-------------------------------------------------------------+---------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 1                     ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[0]    ; AB12  ; 3A       ; 12           ; 0            ; 17           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[1]    ; AC12  ; 3A       ; 16           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[2]    ; AF9   ; 3A       ; 8            ; 0            ; 34           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[3]    ; AF10  ; 3A       ; 4            ; 0            ; 51           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[4]    ; AD11  ; 3A       ; 2            ; 0            ; 40           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[5]    ; AD12  ; 3A       ; 16           ; 0            ; 17           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[6]    ; AE11  ; 3A       ; 4            ; 0            ; 34           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[7]    ; AC9   ; 3A       ; 4            ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[8]    ; AD10  ; 3A       ; 4            ; 0            ; 17           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[9]    ; AE12  ; 3A       ; 2            ; 0            ; 57           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage                                                             ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; 3A       ; 10 / 32 ( 31 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 3B       ; 1 / 48 ( 2 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 4A       ; 0 / 80 ( 0 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 5A       ; 15 / 32 ( 47 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 5B       ; 6 / 16 ( 38 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                  ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA14     ; 122        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA15     ; 120        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AA24     ; 228        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB12     ; 72         ; 3A             ; SW[0]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB22     ; 225        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB25     ; 230        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB28     ; 249        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC9      ; 58         ; 3A             ; SW[7]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC12     ; 82         ; 3A             ; SW[1]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC25     ; 215        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC27     ; 242        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD10     ; 56         ; 3A             ; SW[8]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD11     ; 54         ; 3A             ; SW[4]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD12     ; 80         ; 3A             ; SW[5]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD25     ; 213        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD26     ; 240        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE11     ; 59         ; 3A             ; SW[6]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AE12     ; 52         ; 3A             ; SW[9]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF9      ; 67         ; 3A             ; SW[2]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF10     ; 57         ; 3A             ; SW[3]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V16      ; 138        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V17      ; 154        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V23      ; 236        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W15      ; 130        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W16      ; 136        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W17      ; 152        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W21      ; 221        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W22      ; 223        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; W24      ; 238        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W25      ; 244        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y16      ; 128        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y23      ; 232        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y24      ; 234        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++-------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node                ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                        ; Entity Name     ; Library Name ;
++-------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------------------------------------------------+-----------------+--------------+
+; |ex12                                     ; 9.0 (0.5)            ; 9.0 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 18 (1)              ; 0 (0)                     ; 0 (0)         ; 10240             ; 1     ; 0          ; 32   ; 0            ; |ex12                                                                      ; ex12            ; work         ;
+;    |ROM:r|                                ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 10240             ; 1     ; 0          ; 0    ; 0            ; |ex12|ROM:r                                                                ; ROM             ; work         ;
+;       |altsyncram:altsyncram_component|   ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 10240             ; 1     ; 0          ; 0    ; 0            ; |ex12|ROM:r|altsyncram:altsyncram_component                                ; altsyncram      ; work         ;
+;          |altsyncram_6ng1:auto_generated| ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 10240             ; 1     ; 0          ; 0    ; 0            ; |ex12|ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated ; altsyncram_6ng1 ; work         ;
+;    |hex_to_7seg:h0|                       ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex12|hex_to_7seg:h0                                                       ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h1|                       ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex12|hex_to_7seg:h1                                                       ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h2|                       ; 1.5 (1.5)            ; 1.5 (1.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex12|hex_to_7seg:h2                                                       ; hex_to_7seg     ; work         ;
++-------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                                     ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; CLOCK_50 ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[0]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[1]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[2]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[3]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[4]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[5]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[6]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[7]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[8]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[9]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                                                         ;
++------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                                                      ; Pad To Core Index ; Setting ;
++------------------------------------------------------------------------------------------+-------------------+---------+
+; CLOCK_50                                                                                 ;                   ;         ;
+; SW[0]                                                                                    ;                   ;         ;
+;      - ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a0 ; 0                 ; 0       ;
+; SW[1]                                                                                    ;                   ;         ;
+;      - ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a0 ; 0                 ; 0       ;
+; SW[2]                                                                                    ;                   ;         ;
+;      - ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a0 ; 0                 ; 0       ;
+; SW[3]                                                                                    ;                   ;         ;
+;      - ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a0 ; 1                 ; 0       ;
+; SW[4]                                                                                    ;                   ;         ;
+;      - ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a0 ; 1                 ; 0       ;
+; SW[5]                                                                                    ;                   ;         ;
+;      - ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a0 ; 1                 ; 0       ;
+; SW[6]                                                                                    ;                   ;         ;
+;      - ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a0 ; 1                 ; 0       ;
+; SW[7]                                                                                    ;                   ;         ;
+;      - ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a0 ; 0                 ; 0       ;
+; SW[8]                                                                                    ;                   ;         ;
+;      - ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a0 ; 1                 ; 0       ;
+; SW[9]                                                                                    ;                   ;         ;
+;      - ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a0 ; 0                 ; 0       ;
++------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                      ;
++----------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
+; Name     ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 1       ; Clock ; yes    ; Global Clock         ; GCLK6            ; --                        ;
++----------+----------+---------+-------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                         ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 1       ; Global Clock         ; GCLK6            ; --                        ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++---------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+-------------------------+----------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+; Name                                                                            ; Type ; Mode ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF                     ; Location       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs         ;
++---------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+-------------------------+----------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+; ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; Single Clock ; 1024         ; 10           ; --           ; --           ; yes                    ; yes                     ; --                     ; --                      ; 10240 ; 1024                        ; 10                          ; --                          ; --                          ; 10240               ; 1           ; 0          ; ./rom_data/rom_data.mif ; M10K_X76_Y4_N0 ; Don't care           ; New data        ; New data        ; Off      ; No                     ; No - Address Too Wide ;
++---------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+-------------------------+----------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++----------------------------------------------------------------------+
+; Routing Usage Summary                                                ;
++---------------------------------------------+------------------------+
+; Routing Resource Type                       ; Usage                  ;
++---------------------------------------------+------------------------+
+; Block interconnects                         ; 40 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 9 / 13,420 ( < 1 % )   ;
+; C2 interconnects                            ; 16 / 119,108 ( < 1 % ) ;
+; C4 interconnects                            ; 38 / 56,300 ( < 1 % )  ;
+; DQS bus muxes                               ; 0 / 25 ( 0 % )         ;
+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )         ;
+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )         ;
+; Direct links                                ; 4 / 289,320 ( < 1 % )  ;
+; Global clocks                               ; 1 / 16 ( 6 % )         ;
+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )          ;
+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )          ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )          ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )          ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )          ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )         ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )         ;
+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )         ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )         ;
+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )         ;
+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )          ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )        ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )        ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )        ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )        ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )        ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )        ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )        ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )         ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )         ;
+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )          ;
+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )        ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )         ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )          ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )          ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )         ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )         ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )         ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )         ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )         ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )         ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )         ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )         ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )         ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )         ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )         ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )         ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )         ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )         ;
+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )         ;
+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )        ;
+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )        ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )          ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )         ;
+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )         ;
+; Local interconnects                         ; 0 / 84,580 ( 0 % )     ;
+; Quadrant clocks                             ; 0 / 66 ( 0 % )         ;
+; R14 interconnects                           ; 46 / 12,676 ( < 1 % )  ;
+; R14/C12 interconnect drivers                ; 46 / 20,720 ( < 1 % )  ;
+; R3 interconnects                            ; 9 / 130,992 ( < 1 % )  ;
+; R6 interconnects                            ; 41 / 266,960 ( < 1 % ) ;
+; Spine clocks                                ; 1 / 360 ( < 1 % )      ;
+; Wire stub REs                               ; 0 / 15,858 ( 0 % )     ;
++---------------------------------------------+------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 28    ;
+; Number of I/O Rules Passed       ; 6     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 22    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                  ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass         ; 32        ; 0            ; 32        ; 0            ; 0            ; 32        ; 32        ; 0            ; 32        ; 32        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 32           ; 0         ; 32           ; 32           ; 0         ; 0         ; 32           ; 0         ; 0         ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ; 32           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[0]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                          ;
++------------------------------------------------------------------+-----------------------------+
+; Option                                                           ; Setting                     ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
+; Enable INIT_DONE output                                          ; Off                         ;
+; Configuration scheme                                             ; Passive Serial              ;
+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
+; Enable CvP_CONFDONE pin                                          ; Off                         ;
+; Enable open drain on CRC_ERROR pin                               ; On                          ;
+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
+; Enable open drain on INIT_DONE pin                               ; On                          ;
+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
+; Enable open drain on nCEO pin                                    ; On                          ;
+; Enable Partial Reconfiguration pins                              ; Off                         ;
+; Enable input tri-state on active configuration pins in user mode ; Off                         ;
+; Enable internal scrubbing                                        ; Off                         ;
+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
+; Device initialization clock source                               ; Internal Oscillator         ;
+; Configuration via Protocol                                       ; Off                         ;
+; Configuration Voltage Level                                      ; Auto                        ;
+; Force Configuration Voltage Level                                ; Off                         ;
+; Enable nCEO output                                               ; Off                         ;
+; Data[15..8]                                                      ; Unreserved                  ;
+; Data[7..5]                                                       ; Unreserved                  ;
+; Base pin-out file on sameframe device                            ; Off                         ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.10 V ;
+; Low Junction Temperature  ; 0 �C   ;
+; High Junction Temperature ; 85 �C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex12"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Info (184020): Starting Fitter periphery placement operations
+Info (11191): Automatically promoted 1 clock (1 global)
+    Info (11162): CLOCK_50~inputCLKENA0 with 10 fanout uses global clock CLKCTRL_G6
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex12.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.07 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file C:/New folder/ex12/output_files/ex12.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 54 warnings
+    Info: Peak virtual memory: 2589 megabytes
+    Info: Processing ended: Tue Nov 29 11:37:05 2016
+    Info: Elapsed time: 00:00:28
+    Info: Total CPU time (on all processors): 00:00:48
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/New folder/ex12/output_files/ex12.fit.smsg.
+
+
diff --git a/part_3/ex12/output_files/ex12.fit.smsg b/part_3/ex12/output_files/ex12.fit.smsg
new file mode 100755
index 0000000..43eead5
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_3/ex12/output_files/ex12.fit.summary b/part_3/ex12/output_files/ex12.fit.summary
new file mode 100755
index 0000000..5bc925b
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Tue Nov 29 11:37:05 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex12
+Top-level Entity Name : ex12
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 9 / 32,070 ( < 1 % )
+Total registers : 0
+Total pins : 32 / 457 ( 7 % )
+Total virtual pins : 0
+Total block memory bits : 10,240 / 4,065,280 ( < 1 % )
+Total RAM Blocks : 1 / 397 ( < 1 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_3/ex12/output_files/ex12.flow.rpt b/part_3/ex12/output_files/ex12.flow.rpt
new file mode 100755
index 0000000..0f49a8d
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.flow.rpt
@@ -0,0 +1,129 @@
+Flow report for ex12
+Tue Nov 29 11:37:18 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary                                                                      ;
++---------------------------------+-------------------------------------------------+
+; Flow Status                     ; Successful - Tue Nov 29 11:37:12 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex12                                            ;
+; Top-level Entity Name           ; ex12                                            ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 9 / 32,070 ( < 1 % )                            ;
+; Total registers                 ; 0                                               ;
+; Total pins                      ; 32 / 457 ( 7 % )                                ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 10,240 / 4,065,280 ( < 1 % )                    ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 11/29/2016 11:36:27 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ex12                ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                       ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564170200.148041938708096       ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; MISC_FILE                           ; ROM_bb.v                              ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:10     ; 1.0                     ; 892 MB              ; 00:00:21                           ;
+; Fitter                    ; 00:00:28     ; 1.0                     ; 2589 MB             ; 00:00:48                           ;
+; Assembler                 ; 00:00:06     ; 1.0                     ; 891 MB              ; 00:00:06                           ;
+; TimeQuest Timing Analyzer ; 00:00:05     ; 1.0                     ; 1205 MB             ; 00:00:05                           ;
+; Total                     ; 00:00:49     ; --                      ; --                  ; 00:01:20                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex12 -c ex12
+quartus_fit --read_settings_files=off --write_settings_files=off ex12 -c ex12
+quartus_asm --read_settings_files=off --write_settings_files=off ex12 -c ex12
+quartus_sta ex12 -c ex12
+
+
+
diff --git a/part_3/ex12/output_files/ex12.jdi b/part_3/ex12/output_files/ex12.jdi
new file mode 100755
index 0000000..19da7dc
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="7eece59e299d53d4f2fa"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="ex12.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/part_3/ex12/output_files/ex12.map.rpt b/part_3/ex12/output_files/ex12.map.rpt
new file mode 100755
index 0000000..643f3a5
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.map.rpt
@@ -0,0 +1,458 @@
+Analysis & Synthesis report for ex12
+Tue Nov 29 11:36:36 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis IP Cores Summary
+ 10. General Register Statistics
+ 11. Source assignments for ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated
+ 12. Parameter Settings for User Entity Instance: ROM:r|altsyncram:altsyncram_component
+ 13. altsyncram Parameter Settings by Entity Instance
+ 14. Port Connectivity Checks: "hex_to_7seg:h2"
+ 15. Post-Synthesis Netlist Statistics for Top Partition
+ 16. Elapsed Time Per Partition
+ 17. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                      ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Tue Nov 29 11:36:36 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex12                                            ;
+; Top-level Entity Name           ; ex12                                            ;
+; Family                          ; Cyclone V                                       ;
+; Logic utilization (in ALMs)     ; N/A                                             ;
+; Total registers                 ; 0                                               ;
+; Total pins                      ; 32                                              ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 10,240                                          ;
+; Total DSP Blocks                ; 0                                               ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0                                               ;
+; Total DLLs                      ; 0                                               ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; ex12               ; ex12               ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Synthesis Seed                                                                  ; 1                  ; 1                  ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
++----------------------------+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                       ;
++----------------------------------+-----------------+----------------------------------------+----------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                              ; File Name with Absolute Path                                         ; Library ;
++----------------------------------+-----------------+----------------------------------------+----------------------------------------------------------------------+---------+
+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File                  ; C:/New folder/ex12/verilog_files/hex_to_7seg.v                       ;         ;
+; ROM.v                            ; yes             ; User Wizard-Generated File             ; C:/New folder/ex12/ROM.v                                             ;         ;
+; ex12.v                           ; yes             ; User Verilog HDL File                  ; C:/New folder/ex12/ex12.v                                            ;         ;
+; altsyncram.tdf                   ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf        ;         ;
+; stratix_ram_block.inc            ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/stratix_ram_block.inc ;         ;
+; lpm_mux.inc                      ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_mux.inc           ;         ;
+; lpm_decode.inc                   ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_decode.inc        ;         ;
+; aglobal160.inc                   ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/aglobal160.inc        ;         ;
+; a_rdenreg.inc                    ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/a_rdenreg.inc         ;         ;
+; altrom.inc                       ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altrom.inc            ;         ;
+; altram.inc                       ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altram.inc            ;         ;
+; altdpram.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altdpram.inc          ;         ;
+; db/altsyncram_6ng1.tdf           ; yes             ; Auto-Generated Megafunction            ; C:/New folder/ex12/db/altsyncram_6ng1.tdf                            ;         ;
+; rom_data/rom_data.mif            ; yes             ; Auto-Found Memory Initialization File  ; C:/New folder/ex12/rom_data/rom_data.mif                             ;         ;
++----------------------------------+-----------------+----------------------------------------+----------------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                  ;
++---------------------------------------------+----------------+
+; Resource                                    ; Usage          ;
++---------------------------------------------+----------------+
+; Estimate of Logic utilization (ALMs needed) ; 9              ;
+;                                             ;                ;
+; Combinational ALUT usage for logic          ; 17             ;
+;     -- 7 input functions                    ; 0              ;
+;     -- 6 input functions                    ; 0              ;
+;     -- 5 input functions                    ; 0              ;
+;     -- 4 input functions                    ; 14             ;
+;     -- <=3 input functions                  ; 3              ;
+;                                             ;                ;
+; Dedicated logic registers                   ; 0              ;
+;                                             ;                ;
+; I/O pins                                    ; 32             ;
+; Total MLAB memory bits                      ; 0              ;
+; Total block memory bits                     ; 10240          ;
+;                                             ;                ;
+; Total DSP Blocks                            ; 0              ;
+;                                             ;                ;
+; Maximum fan-out node                        ; CLOCK_50~input ;
+; Maximum fan-out                             ; 10             ;
+; Total fan-out                               ; 224            ;
+; Average fan-out                             ; 2.46           ;
++---------------------------------------------+----------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                               ;
++-------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node                ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                        ; Entity Name     ; Library Name ;
++-------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------------------------------------------------+-----------------+--------------+
+; |ex12                                     ; 17 (0)            ; 0 (0)        ; 10240             ; 0          ; 32   ; 0            ; |ex12                                                                      ; ex12            ; work         ;
+;    |ROM:r|                                ; 0 (0)             ; 0 (0)        ; 10240             ; 0          ; 0    ; 0            ; |ex12|ROM:r                                                                ; ROM             ; work         ;
+;       |altsyncram:altsyncram_component|   ; 0 (0)             ; 0 (0)        ; 10240             ; 0          ; 0    ; 0            ; |ex12|ROM:r|altsyncram:altsyncram_component                                ; altsyncram      ; work         ;
+;          |altsyncram_6ng1:auto_generated| ; 0 (0)             ; 0 (0)        ; 10240             ; 0          ; 0    ; 0            ; |ex12|ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated ; altsyncram_6ng1 ; work         ;
+;    |hex_to_7seg:h0|                       ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex12|hex_to_7seg:h0                                                       ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h1|                       ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex12|hex_to_7seg:h1                                                       ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h2|                       ; 3 (3)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex12|hex_to_7seg:h2                                                       ; hex_to_7seg     ; work         ;
++-------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                            ;
++---------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-------------------------+
+; Name                                                                            ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF                     ;
++---------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-------------------------+
+; ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 1024         ; 10           ; --           ; --           ; 10240 ; ./rom_data/rom_data.mif ;
++---------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                             ;
++--------+--------------+---------+--------------+--------------+-----------------+-----------------+
+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
++--------+--------------+---------+--------------+--------------+-----------------+-----------------+
+; Altera ; ROM: 1-PORT  ; 16.0    ; N/A          ; N/A          ; |ex12|ROM:r     ; ROM.v           ;
++--------+--------------+---------+--------------+--------------+-----------------+-----------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++---------------------------------------------------------------------------------------------+
+; Source assignments for ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated ;
++---------------------------------+--------------------+------+-------------------------------+
+; Assignment                      ; Value              ; From ; To                            ;
++---------------------------------+--------------------+------+-------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                             ;
++---------------------------------+--------------------+------+-------------------------------+
+
+
++------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: ROM:r|altsyncram:altsyncram_component ;
++------------------------------------+-------------------------+---------------------+
+; Parameter Name                     ; Value                   ; Type                ;
++------------------------------------+-------------------------+---------------------+
+; BYTE_SIZE_BLOCK                    ; 8                       ; Untyped             ;
+; AUTO_CARRY_CHAINS                  ; ON                      ; AUTO_CARRY          ;
+; IGNORE_CARRY_BUFFERS               ; OFF                     ; IGNORE_CARRY        ;
+; AUTO_CASCADE_CHAINS                ; ON                      ; AUTO_CASCADE        ;
+; IGNORE_CASCADE_BUFFERS             ; OFF                     ; IGNORE_CASCADE      ;
+; WIDTH_BYTEENA                      ; 1                       ; Untyped             ;
+; OPERATION_MODE                     ; ROM                     ; Untyped             ;
+; WIDTH_A                            ; 10                      ; Signed Integer      ;
+; WIDTHAD_A                          ; 10                      ; Signed Integer      ;
+; NUMWORDS_A                         ; 1024                    ; Signed Integer      ;
+; OUTDATA_REG_A                      ; CLOCK0                  ; Untyped             ;
+; ADDRESS_ACLR_A                     ; NONE                    ; Untyped             ;
+; OUTDATA_ACLR_A                     ; NONE                    ; Untyped             ;
+; WRCONTROL_ACLR_A                   ; NONE                    ; Untyped             ;
+; INDATA_ACLR_A                      ; NONE                    ; Untyped             ;
+; BYTEENA_ACLR_A                     ; NONE                    ; Untyped             ;
+; WIDTH_B                            ; 1                       ; Untyped             ;
+; WIDTHAD_B                          ; 1                       ; Untyped             ;
+; NUMWORDS_B                         ; 1                       ; Untyped             ;
+; INDATA_REG_B                       ; CLOCK1                  ; Untyped             ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                  ; Untyped             ;
+; RDCONTROL_REG_B                    ; CLOCK1                  ; Untyped             ;
+; ADDRESS_REG_B                      ; CLOCK1                  ; Untyped             ;
+; OUTDATA_REG_B                      ; UNREGISTERED            ; Untyped             ;
+; BYTEENA_REG_B                      ; CLOCK1                  ; Untyped             ;
+; INDATA_ACLR_B                      ; NONE                    ; Untyped             ;
+; WRCONTROL_ACLR_B                   ; NONE                    ; Untyped             ;
+; ADDRESS_ACLR_B                     ; NONE                    ; Untyped             ;
+; OUTDATA_ACLR_B                     ; NONE                    ; Untyped             ;
+; RDCONTROL_ACLR_B                   ; NONE                    ; Untyped             ;
+; BYTEENA_ACLR_B                     ; NONE                    ; Untyped             ;
+; WIDTH_BYTEENA_A                    ; 1                       ; Signed Integer      ;
+; WIDTH_BYTEENA_B                    ; 1                       ; Untyped             ;
+; RAM_BLOCK_TYPE                     ; AUTO                    ; Untyped             ;
+; BYTE_SIZE                          ; 8                       ; Untyped             ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE               ; Untyped             ;
+; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ    ; Untyped             ;
+; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ    ; Untyped             ;
+; INIT_FILE                          ; ./rom_data/rom_data.mif ; Untyped             ;
+; INIT_FILE_LAYOUT                   ; PORT_A                  ; Untyped             ;
+; MAXIMUM_DEPTH                      ; 0                       ; Untyped             ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS                  ; Untyped             ;
+; CLOCK_ENABLE_INPUT_B               ; NORMAL                  ; Untyped             ;
+; CLOCK_ENABLE_OUTPUT_A              ; BYPASS                  ; Untyped             ;
+; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                  ; Untyped             ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN         ; Untyped             ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN         ; Untyped             ;
+; ENABLE_ECC                         ; FALSE                   ; Untyped             ;
+; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                   ; Untyped             ;
+; WIDTH_ECCSTATUS                    ; 3                       ; Untyped             ;
+; DEVICE_FAMILY                      ; Cyclone V               ; Untyped             ;
+; CBXI_PARAMETER                     ; altsyncram_6ng1         ; Untyped             ;
++------------------------------------+-------------------------+---------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------+
+; altsyncram Parameter Settings by Entity Instance                                  ;
++-------------------------------------------+---------------------------------------+
+; Name                                      ; Value                                 ;
++-------------------------------------------+---------------------------------------+
+; Number of entity instances                ; 1                                     ;
+; Entity Instance                           ; ROM:r|altsyncram:altsyncram_component ;
+;     -- OPERATION_MODE                     ; ROM                                   ;
+;     -- WIDTH_A                            ; 10                                    ;
+;     -- NUMWORDS_A                         ; 1024                                  ;
+;     -- OUTDATA_REG_A                      ; CLOCK0                                ;
+;     -- WIDTH_B                            ; 1                                     ;
+;     -- NUMWORDS_B                         ; 1                                     ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                ;
+;     -- OUTDATA_REG_B                      ; UNREGISTERED                          ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                  ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                             ;
++-------------------------------------------+---------------------------------------+
+
+
++--------------------------------------------+
+; Port Connectivity Checks: "hex_to_7seg:h2" ;
++----------+-------+----------+--------------+
+; Port     ; Type  ; Severity ; Details      ;
++----------+-------+----------+--------------+
+; in[3..2] ; Input ; Info     ; Stuck at GND ;
++----------+-------+----------+--------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_lcell_comb     ; 21                          ;
+;     normal            ; 21                          ;
+;         0 data inputs ; 1                           ;
+;         1 data inputs ; 3                           ;
+;         2 data inputs ; 3                           ;
+;         4 data inputs ; 14                          ;
+; boundary_port         ; 32                          ;
+; stratixv_ram_block    ; 10                          ;
+;                       ;                             ;
+; Max LUT depth         ; 2.00                        ;
+; Average LUT depth     ; 1.00                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Tue Nov 29 11:36:26 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex12 -c ex12
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex12/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file rom.v
+    Info (12023): Found entity 1: ROM File: C:/New folder/ex12/ROM.v Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file ex12.v
+    Info (12023): Found entity 1: ex12 File: C:/New folder/ex12/ex12.v Line: 1
+Info (12127): Elaborating entity "ex12" for the top level hierarchy
+Info (12128): Elaborating entity "ROM" for hierarchy "ROM:r" File: C:/New folder/ex12/ex12.v Line: 9
+Info (12128): Elaborating entity "altsyncram" for hierarchy "ROM:r|altsyncram:altsyncram_component" File: C:/New folder/ex12/ROM.v Line: 82
+Info (12130): Elaborated megafunction instantiation "ROM:r|altsyncram:altsyncram_component" File: C:/New folder/ex12/ROM.v Line: 82
+Info (12133): Instantiated megafunction "ROM:r|altsyncram:altsyncram_component" with the following parameter: File: C:/New folder/ex12/ROM.v Line: 82
+    Info (12134): Parameter "address_aclr_a" = "NONE"
+    Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
+    Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
+    Info (12134): Parameter "init_file" = "./rom_data/rom_data.mif"
+    Info (12134): Parameter "intended_device_family" = "Cyclone V"
+    Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
+    Info (12134): Parameter "lpm_type" = "altsyncram"
+    Info (12134): Parameter "numwords_a" = "1024"
+    Info (12134): Parameter "operation_mode" = "ROM"
+    Info (12134): Parameter "outdata_aclr_a" = "NONE"
+    Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
+    Info (12134): Parameter "widthad_a" = "10"
+    Info (12134): Parameter "width_a" = "10"
+    Info (12134): Parameter "width_byteena_a" = "1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_6ng1.tdf
+    Info (12023): Found entity 1: altsyncram_6ng1 File: C:/New folder/ex12/db/altsyncram_6ng1.tdf Line: 28
+Info (12128): Elaborating entity "altsyncram_6ng1" for hierarchy "ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 792
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:h0" File: C:/New folder/ex12/ex12.v Line: 11
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "HEX2[1]" is stuck at GND File: C:/New folder/ex12/ex12.v Line: 5
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 59 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 11 input pins
+    Info (21059): Implemented 21 output pins
+    Info (21061): Implemented 17 logic cells
+    Info (21064): Implemented 10 RAM segments
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings
+    Info: Peak virtual memory: 892 megabytes
+    Info: Processing ended: Tue Nov 29 11:36:36 2016
+    Info: Elapsed time: 00:00:10
+    Info: Total CPU time (on all processors): 00:00:21
+
+
diff --git a/part_3/ex12/output_files/ex12.map.smsg b/part_3/ex12/output_files/ex12.map.smsg
new file mode 100755
index 0000000..46a5fc9
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.map.smsg
@@ -0,0 +1,35 @@
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: C:/New folder/ex12/verilog_files/bin2bcd_16.v Line: 22
diff --git a/part_3/ex12/output_files/ex12.map.summary b/part_3/ex12/output_files/ex12.map.summary
new file mode 100755
index 0000000..5942e67
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Tue Nov 29 11:36:36 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex12
+Top-level Entity Name : ex12
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 0
+Total pins : 32
+Total virtual pins : 0
+Total block memory bits : 10,240
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_3/ex12/output_files/ex12.pin b/part_3/ex12/output_files/ex12.pin
new file mode 100755
index 0000000..1134a47
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.pin
@@ -0,0 +1,976 @@
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other 
+ -- applicable license agreement, including, without limitation, 
+ -- that your use is for the sole purpose of programming logic 
+ -- devices manufactured by Altera and sold by Altera or its 
+ -- authorized distributors.  Please refer to the applicable 
+ -- agreement for further details.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 3A:       3.3V
+ --                  Bank 3B:       3.3V
+ --                  Bank 4A:       3.3V
+ --                  Bank 5A:       3.3V
+ --                  Bank 5B:       3.3V
+ --                  Bank 6B:       2.5V
+ --                  Bank 6A:  2.5V
+ --                  Bank 7A:  2.5V
+ --                  Bank 7B:  2.5V
+ --                  Bank 7C:  2.5V
+ --                  Bank 7D:  2.5V
+ --                  Bank 8A:  2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP  "ex12"  ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
+GND                          : A12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
+GND                          : A17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
+GND                          : A26       :        :                   :         : 7A        :                
+GND                          : A27       : gnd    :                   :         :           :                
+HPS_TRST                     : A28       :        :                   :         : 7A        :                
+HPS_TMS                      : A29       :        :                   :         : 7A        :                
+GND                          : AA1       : gnd    :                   :         :           :                
+GND                          : AA2       : gnd    :                   :         :           :                
+GND                          : AA3       : gnd    :                   :         :           :                
+GND                          : AA4       : gnd    :                   :         :           :                
+VCC                          : AA5       : power  :                   : 1.1V    :           :                
+GND                          : AA6       : gnd    :                   :         :           :                
+DNU                          : AA7       :        :                   :         :           :                
+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
+GND                          : AA9       : gnd    :                   :         :           :                
+VCCPD3A                      : AA10      : power  :                   : 3.3V    : 3A        :                
+GND                          : AA11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
+VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
+GND                          : AA22      : gnd    :                   :         :           :                
+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
+VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
+GND                          : AB1       : gnd    :                   :         :           :                
+GND                          : AB2       : gnd    :                   :         :           :                
+DNU                          : AB3       :        :                   :         :           :                
+DNU                          : AB4       :        :                   :         :           :                
+GND                          : AB5       : gnd    :                   :         :           :                
+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
+GND                          : AB7       : gnd    :                   :         :           :                
+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
+TDO                          : AB9       : output :                   :         : 3A        :                
+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
+SW[0]                        : AB12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
+VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AB19      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22      :        :                   :         : 5A        :                
+HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28      :        :                   :         : 5B        :                
+GND                          : AB29      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
+GND                          : AC1       : gnd    :                   :         :           :                
+GND                          : AC2       : gnd    :                   :         :           :                
+GND                          : AC3       : gnd    :                   :         :           :                
+GND                          : AC4       : gnd    :                   :         :           :                
+TCK                          : AC5       : input  :                   :         : 3A        :                
+GND                          : AC6       : gnd    :                   :         :           :                
+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
+GND                          : AC8       : gnd    :                   :         :           :                
+SW[7]                        : AC9       : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCPD3A                      : AC10      : power  :                   : 3.3V    : 3A        :                
+VCCIO3A                      : AC11      : power  :                   : 3.3V    : 3A        :                
+SW[1]                        : AC12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
+VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AC16      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
+VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25      :        :                   :         : 5A        :                
+GND                          : AC26      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC27      :        :                   :         : 5A        :                
+HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AD1       : gnd    :                   :         :           :                
+GND                          : AD2       : gnd    :                   :         :           :                
+DNU                          : AD3       :        :                   :         :           :                
+DNU                          : AD4       :        :                   :         :           :                
+GND                          : AD5       : gnd    :                   :         :           :                
+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
+VCCIO3A                      : AD8       : power  :                   : 3.3V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
+SW[8]                        : AD10      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[4]                        : AD11      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[5]                        : AD12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
+DNU                          : AD15      :        :                   :         :           :                
+VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
+VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
+GND                          : AD23      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD26      :        :                   :         : 5A        :                
+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                
+HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AE1       : gnd    :                   :         :           :                
+GND                          : AE2       : gnd    :                   :         :           :                
+GND                          : AE3       : gnd    :                   :         :           :                
+GND                          : AE4       : gnd    :                   :         :           :                
+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
+GND                          : AE10      : gnd    :                   :         :           :                
+SW[6]                        : AE11      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[9]                        : AE12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
+VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
+GND                          : AE20      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
+VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                
+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                
+GND                          : AF1       : gnd    :                   :         :           :                
+GND                          : AF2       : gnd    :                   :         :           :                
+GND                          : AF3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
+VCCIO3A                      : AF7       : power  :                   : 3.3V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
+SW[2]                        : AF9       : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[3]                        : AF10      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
+GND                          : AF12      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
+CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
+GND                          : AF17      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
+VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
+GND                          : AF27      : gnd    :                   :         :           :                
+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
+VCCIO3A                      : AG4       : power  :                   : 3.3V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
+GND                          : AG9       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
+GND                          : AG14      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
+VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
+GND                          : AG24      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                
+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AH1       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
+GND                          : AH6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
+GND                          : AH11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
+VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
+GND                          : AH21      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
+VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
+GND                          : AJ3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
+VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
+VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
+GND                          : AJ18      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
+VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
+GND                          : AJ28      : gnd    :                   :         :           :                
+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AJ30      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
+GND                          : AK5       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
+VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
+GND                          : AK15      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
+VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
+GND                          : AK25      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
+GND                          : B9        : gnd    :                   :         :           :                
+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
+GND                          : B14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
+GND                          : B19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
+GND                          : B24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
+HPS_TDI                      : B27       :        :                   :         : 7A        :                
+HPS_TDO                      : B28       :        :                   :         : 7A        :                
+GND                          : B29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
+GND                          : C1        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
+GND                          : C6        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
+GND                          : C21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
+GND                          : C26       : gnd    :                   :         :           :                
+HPS_nRST                     : C27       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
+GND                          : D3        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
+GND                          : D13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
+GND                          : D23       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
+HPS_CLK1                     : D25       :        :                   :         : 7A        :                
+GND                          : D26       :        :                   :         : 7A        :                
+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
+GND                          : E10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
+GND                          : E25       : gnd    :                   :         :           :                
+DNU                          : E26       :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
+GND                          : E30       : gnd    :                   :         :           :                
+DNU                          : F1        :        :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+CONF_DONE                    : F3        :        :                   :         : 9A        :                
+nSTATUS                      : F4        :        :                   :         : 9A        :                
+GND                          : F5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
+GND                          : F7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
+GND                          : F17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
+HPS_nPOR                     : F23       :        :                   :         : 7A        :                
+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
+HPS_CLK2                     : F25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
+GND                          : F27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
+GND                          : G1        :        :                   :         :           :                
+DNU                          : G2        :        :                   :         :           :                
+GND                          : G3        : gnd    :                   :         :           :                
+GND                          : G4        : gnd    :                   :         :           :                
+nCE                          : G5        :        :                   :         : 9A        :                
+MSEL2                        : G6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
+GND                          : G24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+DNU                          : H3        :        :                   :         :           :                
+DNU                          : H4        :        :                   :         :           :                
+GND                          : H5        : gnd    :                   :         :           :                
+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
+GND                          : H11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
+HPS_TCK                      : H22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
+GND                          : J1        : gnd    :                   :         :           :                
+GND                          : J2        : gnd    :                   :         :           :                
+GND                          : J3        : gnd    :                   :         :           :                
+GND                          : J4        : gnd    :                   :         :           :                
+nCONFIG                      : J5        :        :                   :         : 9A        :                
+GND                          : J6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
+GND                          : J8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
+DNU                          : J15       :        :                   :         :           :                
+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
+GND                          : J18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
+GND                          : J22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
+GND                          : J28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+DNU                          : K3        :        :                   :         :           :                
+DNU                          : K4        :        :                   :         :           :                
+GND                          : K5        : gnd    :                   :         :           :                
+MSEL1                        : K6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
+GND                          : K15       : gnd    :                   :         :           :                
+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
+GND                          : K20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
+GND                          : K25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
+GND                          : L1        : gnd    :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+GND                          : L3        : gnd    :                   :         :           :                
+GND                          : L4        : gnd    :                   :         :           :                
+VCC                          : L5        : power  :                   : 1.1V    :           :                
+GND                          : L6        : gnd    :                   :         :           :                
+MSEL3                        : L7        :        :                   :         : 9A        :                
+MSEL0                        : L8        :        :                   :         : 9A        :                
+MSEL4                        : L9        :        :                   :         : 9A        :                
+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
+GND                          : L17       : gnd    :                   :         :           :                
+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
+GND                          : L19       : gnd    :                   :         :           :                
+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
+GND                          : L22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
+GND                          : M1        : gnd    :                   :         :           :                
+GND                          : M2        : gnd    :                   :         :           :                
+DNU                          : M3        :        :                   :         :           :                
+DNU                          : M4        :        :                   :         :           :                
+GND                          : M5        : gnd    :                   :         :           :                
+VCC                          : M6        : power  :                   : 1.1V    :           :                
+GND                          : M7        : gnd    :                   :         :           :                
+GND                          : M8        : gnd    :                   :         :           :                
+VCC                          : M9        : power  :                   : 1.1V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+VCC                          : M11       : power  :                   : 1.1V    :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+VCC                          : M13       : power  :                   : 1.1V    :           :                
+GND                          : M14       : gnd    :                   :         :           :                
+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
+GND                          : M16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
+GND                          : M18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
+GND                          : M20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
+GND                          : M29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
+GND                          : N1        : gnd    :                   :         :           :                
+GND                          : N2        : gnd    :                   :         :           :                
+GND                          : N3        : gnd    :                   :         :           :                
+GND                          : N4        : gnd    :                   :         :           :                
+VCC                          : N5        : power  :                   : 1.1V    :           :                
+GND                          : N6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
+GND                          : N8        : gnd    :                   :         :           :                
+GND                          : N9        : gnd    :                   :         :           :                
+VCC                          : N10       : power  :                   : 1.1V    :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+VCC                          : N12       : power  :                   : 1.1V    :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCC                          : N14       : power  :                   : 1.1V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
+GND                          : N17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
+GND                          : N19       : gnd    :                   :         :           :                
+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
+GND                          : N26       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
+GND                          : P1        : gnd    :                   :         :           :                
+GND                          : P2        : gnd    :                   :         :           :                
+DNU                          : P3        :        :                   :         :           :                
+DNU                          : P4        :        :                   :         :           :                
+GND                          : P5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
+GND                          : P7        : gnd    :                   :         :           :                
+GND                          : P8        : gnd    :                   :         :           :                
+GND                          : P9        : gnd    :                   :         :           :                
+GND                          : P10       : gnd    :                   :         :           :                
+VCC                          : P11       : power  :                   : 1.1V    :           :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCC                          : P13       : power  :                   : 1.1V    :           :                
+GND                          : P14       : gnd    :                   :         :           :                
+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
+GND                          : P16       : gnd    :                   :         :           :                
+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
+GND                          : P18       : gnd    :                   :         :           :                
+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
+GND                          : P20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
+GND                          : R1        : gnd    :                   :         :           :                
+GND                          : R2        : gnd    :                   :         :           :                
+GND                          : R3        : gnd    :                   :         :           :                
+GND                          : R4        : gnd    :                   :         :           :                
+VCC                          : R5        : power  :                   : 1.1V    :           :                
+GND                          : R6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
+GND                          : R8        : gnd    :                   :         :           :                
+GND                          : R9        : gnd    :                   :         :           :                
+VCC                          : R10       : power  :                   : 1.1V    :           :                
+GND                          : R11       : gnd    :                   :         :           :                
+VCC                          : R12       : power  :                   : 1.1V    :           :                
+GND                          : R13       : gnd    :                   :         :           :                
+VCC                          : R14       : power  :                   : 1.1V    :           :                
+GND                          : R15       : gnd    :                   :         :           :                
+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
+GND                          : R17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
+GND                          : R30       : gnd    :                   :         :           :                
+GND                          : T1        : gnd    :                   :         :           :                
+GND                          : T2        : gnd    :                   :         :           :                
+DNU                          : T3        :        :                   :         :           :                
+DNU                          : T4        :        :                   :         :           :                
+GND                          : T5        : gnd    :                   :         :           :                
+VCC                          : T6        : power  :                   : 1.1V    :           :                
+GND                          : T7        : gnd    :                   :         :           :                
+GND                          : T8        : gnd    :                   :         :           :                
+GND                          : T9        : gnd    :                   :         :           :                
+GND                          : T10       : gnd    :                   :         :           :                
+VCC                          : T11       : power  :                   : 1.1V    :           :                
+GND                          : T12       : gnd    :                   :         :           :                
+VCC                          : T13       : power  :                   : 1.1V    :           :                
+GND                          : T14       : gnd    :                   :         :           :                
+GND                          : T15       : gnd    :                   :         :           :                
+GND                          : T16       : gnd    :                   :         :           :                
+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
+GND                          : T18       : gnd    :                   :         :           :                
+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
+GND                          : T20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
+GND                          : T27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
+GND                          : U1        : gnd    :                   :         :           :                
+GND                          : U2        : gnd    :                   :         :           :                
+GND                          : U3        : gnd    :                   :         :           :                
+GND                          : U4        : gnd    :                   :         :           :                
+VCC                          : U5        : power  :                   : 1.1V    :           :                
+GND                          : U6        : gnd    :                   :         :           :                
+DCLK                         : U7        :        :                   :         : 3A        :                
+TDI                          : U8        : input  :                   :         : 3A        :                
+GND                          : U9        : gnd    :                   :         :           :                
+VCC                          : U10       : power  :                   : 1.1V    :           :                
+GND                          : U11       : gnd    :                   :         :           :                
+VCC                          : U12       : power  :                   : 1.1V    :           :                
+GND                          : U13       : gnd    :                   :         :           :                
+VCC                          : U14       : power  :                   : 1.1V    :           :                
+GND                          : U15       : gnd    :                   :         :           :                
+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
+GND                          : U17       : gnd    :                   :         :           :                
+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
+VCC                          : U21       : power  :                   : 1.1V    :           :                
+GND                          : U22       : gnd    :                   :         :           :                
+VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                
+GND                          : U24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
+GND                          : U29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
+GND                          : V1        : gnd    :                   :         :           :                
+GND                          : V2        : gnd    :                   :         :           :                
+DNU                          : V3        :        :                   :         :           :                
+DNU                          : V4        :        :                   :         :           :                
+GND                          : V5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
+GND                          : V7        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
+TMS                          : V9        : input  :                   :         : 3A        :                
+GND                          : V10       : gnd    :                   :         :           :                
+VCC                          : V11       : power  :                   : 1.1V    :           :                
+GND                          : V12       : gnd    :                   :         :           :                
+VCC                          : V13       : power  :                   : 1.1V    :           :                
+GND                          : V14       : gnd    :                   :         :           :                
+VCC                          : V15       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                
+GND                          : V19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
+GND                          : V21       : gnd    :                   :         :           :                
+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V23       :        :                   :         : 5A        :                
+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
+GND                          : W1        : gnd    :                   :         :           :                
+GND                          : W2        : gnd    :                   :         :           :                
+GND                          : W3        : gnd    :                   :         :           :                
+GND                          : W4        : gnd    :                   :         :           :                
+VCC                          : W5        : power  :                   : 1.1V    :           :                
+GND                          : W6        : gnd    :                   :         :           :                
+GND                          : W7        : gnd    :                   :         :           :                
+GND                          : W8        : gnd    :                   :         :           :                
+GND                          : W9        : gnd    :                   :         :           :                
+VCC                          : W10       : power  :                   : 1.1V    :           :                
+GND                          : W11       : gnd    :                   :         :           :                
+VCC                          : W12       : power  :                   : 1.1V    :           :                
+GND                          : W13       : gnd    :                   :         :           :                
+VCC                          : W14       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4A        :                
+GND                          : W18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5A        :                
+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W24       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W25       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
+GND                          : W28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
+GND                          : Y1        : gnd    :                   :         :           :                
+GND                          : Y2        : gnd    :                   :         :           :                
+DNU                          : Y3        :        :                   :         :           :                
+DNU                          : Y4        :        :                   :         :           :                
+GND                          : Y5        : gnd    :                   :         :           :                
+VCC                          : Y6        : power  :                   : 1.1V    :           :                
+GND                          : Y7        : gnd    :                   :         :           :                
+GND                          : Y8        : gnd    :                   :         :           :                
+VCC                          : Y9        : power  :                   : 1.1V    :           :                
+GND                          : Y10       : gnd    :                   :         :           :                
+VCC                          : Y11       : power  :                   : 1.1V    :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+VCC                          : Y13       : power  :                   : 1.1V    :           :                
+GND                          : Y14       : gnd    :                   :         :           :                
+GND                          : Y15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                
+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24       :        :                   :         : 5A        :                
+GND                          : Y25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
+GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/part_3/ex12/output_files/ex12.sld b/part_3/ex12/output_files/ex12.sld
new file mode 100755
index 0000000..41a6030
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.sld
@@ -0,0 +1 @@
+<sld_project_info/>
diff --git a/part_3/ex12/output_files/ex12.sof b/part_3/ex12/output_files/ex12.sof
new file mode 100755
index 0000000..9a50a26
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.sof
diff --git a/part_3/ex12/output_files/ex12.sta.rpt b/part_3/ex12/output_files/ex12.sta.rpt
new file mode 100755
index 0000000..16a7a19
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+TimeQuest Timing Analyzer report for ex12
+Tue Nov 29 11:37:18 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1100mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1100mV 85C Model Setup Summary
+  8. Slow 1100mV 85C Model Hold Summary
+  9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Setup Transfers
+ 40. Hold Transfers
+ 41. Report TCCS
+ 42. Report RSKM
+ 43. Unconstrained Paths Summary
+ 44. Clock Status Summary
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. Unconstrained Input Ports
+ 48. Unconstrained Output Ports
+ 49. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                               ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer       ; TimeQuest                                               ;
+; Revision Name         ; ex12                                                    ;
+; Device Family         ; Cyclone V                                               ;
+; Device Name           ; 5CSEMA5F31C6                                            ;
+; Timing Models         ; Final                                                   ;
+; Delay Model           ; Combined                                                ;
+; Rise/Fall Delays      ; Enabled                                                 ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.05        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   1.7%      ;
+;     Processor 3            ;   1.7%      ;
+;     Processor 4            ;   1.7%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                               ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets      ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+; CLOCK_50   ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 } ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Slow 1100mV 85C Model Fmax Summary                                                         ;
++------------+-----------------+------------+------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note                                           ;
++------------+-----------------+------------+------------------------------------------------+
+; 475.06 MHz ; 315.06 MHz      ; CLOCK_50   ; limit due to minimum period restriction (tmin) ;
++------------+-----------------+------------+------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++-------------------------------------+
+; Slow 1100mV 85C Model Setup Summary ;
++----------+--------+-----------------+
+; Clock    ; Slack  ; End Point TNS   ;
++----------+--------+-----------------+
+; CLOCK_50 ; -1.105 ; -11.022         ;
++----------+--------+-----------------+
+
+
++------------------------------------+
+; Slow 1100mV 85C Model Hold Summary ;
++----------+-------+-----------------+
+; Clock    ; Slack ; End Point TNS   ;
++----------+-------+-----------------+
+; CLOCK_50 ; 0.721 ; 0.000           ;
++----------+-------+-----------------+
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
++----------+--------+-------------------------------+
+; Clock    ; Slack  ; End Point TNS                 ;
++----------+--------+-------------------------------+
+; CLOCK_50 ; -2.174 ; -68.175                       ;
++----------+--------+-------------------------------+
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary                                                          ;
++------------+-----------------+------------+------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note                                           ;
++------------+-----------------+------------+------------------------------------------------+
+; 467.95 MHz ; 315.06 MHz      ; CLOCK_50   ; limit due to minimum period restriction (tmin) ;
++------------+-----------------+------------+------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------+
+; Slow 1100mV 0C Model Setup Summary ;
++----------+--------+----------------+
+; Clock    ; Slack  ; End Point TNS  ;
++----------+--------+----------------+
+; CLOCK_50 ; -1.137 ; -11.339        ;
++----------+--------+----------------+
+
+
++-----------------------------------+
+; Slow 1100mV 0C Model Hold Summary ;
++----------+-------+----------------+
+; Clock    ; Slack ; End Point TNS  ;
++----------+-------+----------------+
+; CLOCK_50 ; 0.752 ; 0.000          ;
++----------+-------+----------------+
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
++----------+--------+------------------------------+
+; Clock    ; Slack  ; End Point TNS                ;
++----------+--------+------------------------------+
+; CLOCK_50 ; -2.174 ; -67.971                      ;
++----------+--------+------------------------------+
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------+
+; Fast 1100mV 85C Model Setup Summary ;
++----------+--------+-----------------+
+; Clock    ; Slack  ; End Point TNS   ;
++----------+--------+-----------------+
+; CLOCK_50 ; -0.257 ; -2.544          ;
++----------+--------+-----------------+
+
+
++------------------------------------+
+; Fast 1100mV 85C Model Hold Summary ;
++----------+-------+-----------------+
+; Clock    ; Slack ; End Point TNS   ;
++----------+-------+-----------------+
+; CLOCK_50 ; 0.431 ; 0.000           ;
++----------+-------+-----------------+
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
++----------+--------+-------------------------------+
+; Clock    ; Slack  ; End Point TNS                 ;
++----------+--------+-------------------------------+
+; CLOCK_50 ; -2.174 ; -69.669                       ;
++----------+--------+-------------------------------+
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------+
+; Fast 1100mV 0C Model Setup Summary ;
++----------+--------+----------------+
+; Clock    ; Slack  ; End Point TNS  ;
++----------+--------+----------------+
+; CLOCK_50 ; -0.238 ; -2.357         ;
++----------+--------+----------------+
+
+
++-----------------------------------+
+; Fast 1100mV 0C Model Hold Summary ;
++----------+-------+----------------+
+; Clock    ; Slack ; End Point TNS  ;
++----------+-------+----------------+
+; CLOCK_50 ; 0.425 ; 0.000          ;
++----------+-------+----------------+
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
++----------+--------+------------------------------+
+; Clock    ; Slack  ; End Point TNS                ;
++----------+--------+------------------------------+
+; CLOCK_50 ; -2.174 ; -70.932                      ;
++----------+--------+------------------------------+
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                           ;
++------------------+---------+-------+----------+---------+---------------------+
+; Clock            ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+---------+-------+----------+---------+---------------------+
+; Worst-case Slack ; -1.137  ; 0.425 ; N/A      ; N/A     ; -2.174              ;
+;  CLOCK_50        ; -1.137  ; 0.425 ; N/A      ; N/A     ; -2.174              ;
+; Design-wide TNS  ; -11.339 ; 0.0   ; 0.0      ; 0.0     ; -70.932             ;
+;  CLOCK_50        ; -11.339 ; 0.000 ; N/A      ; N/A     ; -70.932             ;
++------------------+---------+-------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------+
+; Input Transition Times                                      ;
++----------+--------------+-----------------+-----------------+
+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------+--------------+-----------------+-----------------+
+; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[0]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++----------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers                                                   ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50 ; 10       ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers                                                    ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50 ; 10       ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 10    ; 10   ;
+; Unconstrained Input Port Paths  ; 10    ; 10   ;
+; Unconstrained Output Ports      ; 20    ; 20   ;
+; Unconstrained Output Port Paths ; 66    ; 66   ;
++---------------------------------+-------+------+
+
+
++------------------------------------------+
+; Clock Status Summary                     ;
++----------+----------+------+-------------+
+; Target   ; Clock    ; Type ; Status      ;
++----------+----------+------+-------------+
+; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ;
++----------+----------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[8]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[9]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[8]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[9]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Tue Nov 29 11:37:13 2016
+Info: Command: quartus_sta ex12 -c ex12
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex12.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.105
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.105             -11.022 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.721
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.721               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174             -68.175 CLOCK_50 
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.137
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.137             -11.339 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.752
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.752               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174             -67.971 CLOCK_50 
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.257
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.257              -2.544 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.431
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.431               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174             -69.669 CLOCK_50 
+Info: Analyzing Fast 1100mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.238
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.238              -2.357 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.425
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.425               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174             -70.932 CLOCK_50 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 1205 megabytes
+    Info: Processing ended: Tue Nov 29 11:37:18 2016
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:05
+
+
diff --git a/part_3/ex12/output_files/ex12.sta.summary b/part_3/ex12/output_files/ex12.sta.summary
new file mode 100755
index 0000000..1fc806b
--- /dev/null
+++ b/part_3/ex12/output_files/ex12.sta.summary
@@ -0,0 +1,53 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -1.105
+TNS   : -11.022
+
+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.721
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -68.175
+
+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -1.137
+TNS   : -11.339
+
+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.752
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -67.971
+
+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -0.257
+TNS   : -2.544
+
+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.431
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -69.669
+
+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -0.238
+TNS   : -2.357
+
+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.425
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -70.932
+
+------------------------------------------------------------
diff --git a/part_3/ex12/rom_data/rom_data.mif b/part_3/ex12/rom_data/rom_data.mif
new file mode 100755
index 0000000..a688b6f
--- /dev/null
+++ b/part_3/ex12/rom_data/rom_data.mif
@@ -0,0 +1,1032 @@
+-- ROM Initialization file
+WIDTH = 10;
+DEPTH = 1024;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+   0 :  200;
+   1 :  203;
+   2 :  206;
+   3 :  209;
+   4 :  20C;
+   5 :  20F;
+   6 :  212;
+   7 :  215;
+   8 :  219;
+   9 :  21C;
+   A :  21F;
+   B :  222;
+   C :  225;
+   D :  228;
+   E :  22B;
+   F :  22F;
+  10 :  232;
+  11 :  235;
+  12 :  238;
+  13 :  23B;
+  14 :  23E;
+  15 :  241;
+  16 :  244;
+  17 :  247;
+  18 :  24B;
+  19 :  24E;
+  1A :  251;
+  1B :  254;
+  1C :  257;
+  1D :  25A;
+  1E :  25D;
+  1F :  260;
+  20 :  263;
+  21 :  266;
+  22 :  269;
+  23 :  26D;
+  24 :  270;
+  25 :  273;
+  26 :  276;
+  27 :  279;
+  28 :  27C;
+  29 :  27F;
+  2A :  282;
+  2B :  285;
+  2C :  288;
+  2D :  28B;
+  2E :  28E;
+  2F :  291;
+  30 :  294;
+  31 :  297;
+  32 :  29A;
+  33 :  29D;
+  34 :  2A0;
+  35 :  2A3;
+  36 :  2A6;
+  37 :  2A9;
+  38 :  2AC;
+  39 :  2AF;
+  3A :  2B2;
+  3B :  2B5;
+  3C :  2B8;
+  3D :  2BB;
+  3E :  2BD;
+  3F :  2C0;
+  40 :  2C3;
+  41 :  2C6;
+  42 :  2C9;
+  43 :  2CC;
+  44 :  2CF;
+  45 :  2D2;
+  46 :  2D5;
+  47 :  2D7;
+  48 :  2DA;
+  49 :  2DD;
+  4A :  2E0;
+  4B :  2E3;
+  4C :  2E5;
+  4D :  2E8;
+  4E :  2EB;
+  4F :  2EE;
+  50 :  2F1;
+  51 :  2F3;
+  52 :  2F6;
+  53 :  2F9;
+  54 :  2FC;
+  55 :  2FE;
+  56 :  301;
+  57 :  304;
+  58 :  306;
+  59 :  309;
+  5A :  30C;
+  5B :  30E;
+  5C :  311;
+  5D :  314;
+  5E :  316;
+  5F :  319;
+  60 :  31C;
+  61 :  31E;
+  62 :  321;
+  63 :  323;
+  64 :  326;
+  65 :  329;
+  66 :  32B;
+  67 :  32E;
+  68 :  330;
+  69 :  333;
+  6A :  335;
+  6B :  338;
+  6C :  33A;
+  6D :  33D;
+  6E :  33F;
+  6F :  342;
+  70 :  344;
+  71 :  346;
+  72 :  349;
+  73 :  34B;
+  74 :  34E;
+  75 :  350;
+  76 :  352;
+  77 :  355;
+  78 :  357;
+  79 :  359;
+  7A :  35C;
+  7B :  35E;
+  7C :  360;
+  7D :  362;
+  7E :  365;
+  7F :  367;
+  80 :  369;
+  81 :  36B;
+  82 :  36E;
+  83 :  370;
+  84 :  372;
+  85 :  374;
+  86 :  376;
+  87 :  378;
+  88 :  37A;
+  89 :  37D;
+  8A :  37F;
+  8B :  381;
+  8C :  383;
+  8D :  385;
+  8E :  387;
+  8F :  389;
+  90 :  38B;
+  91 :  38D;
+  92 :  38F;
+  93 :  391;
+  94 :  393;
+  95 :  395;
+  96 :  397;
+  97 :  398;
+  98 :  39A;
+  99 :  39C;
+  9A :  39E;
+  9B :  3A0;
+  9C :  3A2;
+  9D :  3A3;
+  9E :  3A5;
+  9F :  3A7;
+  A0 :  3A9;
+  A1 :  3AB;
+  A2 :  3AC;
+  A3 :  3AE;
+  A4 :  3B0;
+  A5 :  3B1;
+  A6 :  3B3;
+  A7 :  3B5;
+  A8 :  3B6;
+  A9 :  3B8;
+  AA :  3B9;
+  AB :  3BB;
+  AC :  3BD;
+  AD :  3BE;
+  AE :  3C0;
+  AF :  3C1;
+  B0 :  3C3;
+  B1 :  3C4;
+  B2 :  3C6;
+  B3 :  3C7;
+  B4 :  3C8;
+  B5 :  3CA;
+  B6 :  3CB;
+  B7 :  3CD;
+  B8 :  3CE;
+  B9 :  3CF;
+  BA :  3D1;
+  BB :  3D2;
+  BC :  3D3;
+  BD :  3D4;
+  BE :  3D6;
+  BF :  3D7;
+  C0 :  3D8;
+  C1 :  3D9;
+  C2 :  3DA;
+  C3 :  3DC;
+  C4 :  3DD;
+  C5 :  3DE;
+  C6 :  3DF;
+  C7 :  3E0;
+  C8 :  3E1;
+  C9 :  3E2;
+  CA :  3E3;
+  CB :  3E4;
+  CC :  3E5;
+  CD :  3E6;
+  CE :  3E7;
+  CF :  3E8;
+  D0 :  3E9;
+  D1 :  3EA;
+  D2 :  3EB;
+  D3 :  3EC;
+  D4 :  3EC;
+  D5 :  3ED;
+  D6 :  3EE;
+  D7 :  3EF;
+  D8 :  3F0;
+  D9 :  3F0;
+  DA :  3F1;
+  DB :  3F2;
+  DC :  3F3;
+  DD :  3F3;
+  DE :  3F4;
+  DF :  3F5;
+  E0 :  3F5;
+  E1 :  3F6;
+  E2 :  3F6;
+  E3 :  3F7;
+  E4 :  3F7;
+  E5 :  3F8;
+  E6 :  3F9;
+  E7 :  3F9;
+  E8 :  3F9;
+  E9 :  3FA;
+  EA :  3FA;
+  EB :  3FB;
+  EC :  3FB;
+  ED :  3FC;
+  EE :  3FC;
+  EF :  3FC;
+  F0 :  3FD;
+  F1 :  3FD;
+  F2 :  3FD;
+  F3 :  3FD;
+  F4 :  3FE;
+  F5 :  3FE;
+  F6 :  3FE;
+  F7 :  3FE;
+  F8 :  3FE;
+  F9 :  3FF;
+  FA :  3FF;
+  FB :  3FF;
+  FC :  3FF;
+  FD :  3FF;
+  FE :  3FF;
+  FF :  3FF;
+ 100 :  3FF;
+ 101 :  3FF;
+ 102 :  3FF;
+ 103 :  3FF;
+ 104 :  3FF;
+ 105 :  3FF;
+ 106 :  3FF;
+ 107 :  3FF;
+ 108 :  3FE;
+ 109 :  3FE;
+ 10A :  3FE;
+ 10B :  3FE;
+ 10C :  3FE;
+ 10D :  3FD;
+ 10E :  3FD;
+ 10F :  3FD;
+ 110 :  3FD;
+ 111 :  3FC;
+ 112 :  3FC;
+ 113 :  3FC;
+ 114 :  3FB;
+ 115 :  3FB;
+ 116 :  3FA;
+ 117 :  3FA;
+ 118 :  3F9;
+ 119 :  3F9;
+ 11A :  3F9;
+ 11B :  3F8;
+ 11C :  3F7;
+ 11D :  3F7;
+ 11E :  3F6;
+ 11F :  3F6;
+ 120 :  3F5;
+ 121 :  3F5;
+ 122 :  3F4;
+ 123 :  3F3;
+ 124 :  3F3;
+ 125 :  3F2;
+ 126 :  3F1;
+ 127 :  3F0;
+ 128 :  3F0;
+ 129 :  3EF;
+ 12A :  3EE;
+ 12B :  3ED;
+ 12C :  3EC;
+ 12D :  3EC;
+ 12E :  3EB;
+ 12F :  3EA;
+ 130 :  3E9;
+ 131 :  3E8;
+ 132 :  3E7;
+ 133 :  3E6;
+ 134 :  3E5;
+ 135 :  3E4;
+ 136 :  3E3;
+ 137 :  3E2;
+ 138 :  3E1;
+ 139 :  3E0;
+ 13A :  3DF;
+ 13B :  3DE;
+ 13C :  3DD;
+ 13D :  3DC;
+ 13E :  3DA;
+ 13F :  3D9;
+ 140 :  3D8;
+ 141 :  3D7;
+ 142 :  3D6;
+ 143 :  3D4;
+ 144 :  3D3;
+ 145 :  3D2;
+ 146 :  3D1;
+ 147 :  3CF;
+ 148 :  3CE;
+ 149 :  3CD;
+ 14A :  3CB;
+ 14B :  3CA;
+ 14C :  3C8;
+ 14D :  3C7;
+ 14E :  3C6;
+ 14F :  3C4;
+ 150 :  3C3;
+ 151 :  3C1;
+ 152 :  3C0;
+ 153 :  3BE;
+ 154 :  3BD;
+ 155 :  3BB;
+ 156 :  3B9;
+ 157 :  3B8;
+ 158 :  3B6;
+ 159 :  3B5;
+ 15A :  3B3;
+ 15B :  3B1;
+ 15C :  3B0;
+ 15D :  3AE;
+ 15E :  3AC;
+ 15F :  3AB;
+ 160 :  3A9;
+ 161 :  3A7;
+ 162 :  3A5;
+ 163 :  3A3;
+ 164 :  3A2;
+ 165 :  3A0;
+ 166 :  39E;
+ 167 :  39C;
+ 168 :  39A;
+ 169 :  398;
+ 16A :  397;
+ 16B :  395;
+ 16C :  393;
+ 16D :  391;
+ 16E :  38F;
+ 16F :  38D;
+ 170 :  38B;
+ 171 :  389;
+ 172 :  387;
+ 173 :  385;
+ 174 :  383;
+ 175 :  381;
+ 176 :  37F;
+ 177 :  37D;
+ 178 :  37A;
+ 179 :  378;
+ 17A :  376;
+ 17B :  374;
+ 17C :  372;
+ 17D :  370;
+ 17E :  36E;
+ 17F :  36B;
+ 180 :  369;
+ 181 :  367;
+ 182 :  365;
+ 183 :  362;
+ 184 :  360;
+ 185 :  35E;
+ 186 :  35C;
+ 187 :  359;
+ 188 :  357;
+ 189 :  355;
+ 18A :  352;
+ 18B :  350;
+ 18C :  34E;
+ 18D :  34B;
+ 18E :  349;
+ 18F :  346;
+ 190 :  344;
+ 191 :  342;
+ 192 :  33F;
+ 193 :  33D;
+ 194 :  33A;
+ 195 :  338;
+ 196 :  335;
+ 197 :  333;
+ 198 :  330;
+ 199 :  32E;
+ 19A :  32B;
+ 19B :  329;
+ 19C :  326;
+ 19D :  323;
+ 19E :  321;
+ 19F :  31E;
+ 1A0 :  31C;
+ 1A1 :  319;
+ 1A2 :  316;
+ 1A3 :  314;
+ 1A4 :  311;
+ 1A5 :  30E;
+ 1A6 :  30C;
+ 1A7 :  309;
+ 1A8 :  306;
+ 1A9 :  304;
+ 1AA :  301;
+ 1AB :  2FE;
+ 1AC :  2FC;
+ 1AD :  2F9;
+ 1AE :  2F6;
+ 1AF :  2F3;
+ 1B0 :  2F1;
+ 1B1 :  2EE;
+ 1B2 :  2EB;
+ 1B3 :  2E8;
+ 1B4 :  2E5;
+ 1B5 :  2E3;
+ 1B6 :  2E0;
+ 1B7 :  2DD;
+ 1B8 :  2DA;
+ 1B9 :  2D7;
+ 1BA :  2D5;
+ 1BB :  2D2;
+ 1BC :  2CF;
+ 1BD :  2CC;
+ 1BE :  2C9;
+ 1BF :  2C6;
+ 1C0 :  2C3;
+ 1C1 :  2C0;
+ 1C2 :  2BD;
+ 1C3 :  2BB;
+ 1C4 :  2B8;
+ 1C5 :  2B5;
+ 1C6 :  2B2;
+ 1C7 :  2AF;
+ 1C8 :  2AC;
+ 1C9 :  2A9;
+ 1CA :  2A6;
+ 1CB :  2A3;
+ 1CC :  2A0;
+ 1CD :  29D;
+ 1CE :  29A;
+ 1CF :  297;
+ 1D0 :  294;
+ 1D1 :  291;
+ 1D2 :  28E;
+ 1D3 :  28B;
+ 1D4 :  288;
+ 1D5 :  285;
+ 1D6 :  282;
+ 1D7 :  27F;
+ 1D8 :  27C;
+ 1D9 :  279;
+ 1DA :  276;
+ 1DB :  273;
+ 1DC :  270;
+ 1DD :  26D;
+ 1DE :  269;
+ 1DF :  266;
+ 1E0 :  263;
+ 1E1 :  260;
+ 1E2 :  25D;
+ 1E3 :  25A;
+ 1E4 :  257;
+ 1E5 :  254;
+ 1E6 :  251;
+ 1E7 :  24E;
+ 1E8 :  24B;
+ 1E9 :  247;
+ 1EA :  244;
+ 1EB :  241;
+ 1EC :  23E;
+ 1ED :  23B;
+ 1EE :  238;
+ 1EF :  235;
+ 1F0 :  232;
+ 1F1 :  22F;
+ 1F2 :  22B;
+ 1F3 :  228;
+ 1F4 :  225;
+ 1F5 :  222;
+ 1F6 :  21F;
+ 1F7 :  21C;
+ 1F8 :  219;
+ 1F9 :  215;
+ 1FA :  212;
+ 1FB :  20F;
+ 1FC :  20C;
+ 1FD :  209;
+ 1FE :  206;
+ 1FF :  203;
+ 200 :  200;
+ 201 :  1FC;
+ 202 :  1F9;
+ 203 :  1F6;
+ 204 :  1F3;
+ 205 :  1F0;
+ 206 :  1ED;
+ 207 :  1EA;
+ 208 :  1E6;
+ 209 :  1E3;
+ 20A :  1E0;
+ 20B :  1DD;
+ 20C :  1DA;
+ 20D :  1D7;
+ 20E :  1D4;
+ 20F :  1D0;
+ 210 :  1CD;
+ 211 :  1CA;
+ 212 :  1C7;
+ 213 :  1C4;
+ 214 :  1C1;
+ 215 :  1BE;
+ 216 :  1BB;
+ 217 :  1B8;
+ 218 :  1B4;
+ 219 :  1B1;
+ 21A :  1AE;
+ 21B :  1AB;
+ 21C :  1A8;
+ 21D :  1A5;
+ 21E :  1A2;
+ 21F :  19F;
+ 220 :  19C;
+ 221 :  199;
+ 222 :  196;
+ 223 :  192;
+ 224 :  18F;
+ 225 :  18C;
+ 226 :  189;
+ 227 :  186;
+ 228 :  183;
+ 229 :  180;
+ 22A :  17D;
+ 22B :  17A;
+ 22C :  177;
+ 22D :  174;
+ 22E :  171;
+ 22F :  16E;
+ 230 :  16B;
+ 231 :  168;
+ 232 :  165;
+ 233 :  162;
+ 234 :  15F;
+ 235 :  15C;
+ 236 :  159;
+ 237 :  156;
+ 238 :  153;
+ 239 :  150;
+ 23A :  14D;
+ 23B :  14A;
+ 23C :  147;
+ 23D :  144;
+ 23E :  142;
+ 23F :  13F;
+ 240 :  13C;
+ 241 :  139;
+ 242 :  136;
+ 243 :  133;
+ 244 :  130;
+ 245 :  12D;
+ 246 :  12A;
+ 247 :  128;
+ 248 :  125;
+ 249 :  122;
+ 24A :  11F;
+ 24B :  11C;
+ 24C :  11A;
+ 24D :  117;
+ 24E :  114;
+ 24F :  111;
+ 250 :  10E;
+ 251 :  10C;
+ 252 :  109;
+ 253 :  106;
+ 254 :  103;
+ 255 :  101;
+ 256 :   FE;
+ 257 :   FB;
+ 258 :   F9;
+ 259 :   F6;
+ 25A :   F3;
+ 25B :   F1;
+ 25C :   EE;
+ 25D :   EB;
+ 25E :   E9;
+ 25F :   E6;
+ 260 :   E3;
+ 261 :   E1;
+ 262 :   DE;
+ 263 :   DC;
+ 264 :   D9;
+ 265 :   D6;
+ 266 :   D4;
+ 267 :   D1;
+ 268 :   CF;
+ 269 :   CC;
+ 26A :   CA;
+ 26B :   C7;
+ 26C :   C5;
+ 26D :   C2;
+ 26E :   C0;
+ 26F :   BD;
+ 270 :   BB;
+ 271 :   B9;
+ 272 :   B6;
+ 273 :   B4;
+ 274 :   B1;
+ 275 :   AF;
+ 276 :   AD;
+ 277 :   AA;
+ 278 :   A8;
+ 279 :   A6;
+ 27A :   A3;
+ 27B :   A1;
+ 27C :   9F;
+ 27D :   9D;
+ 27E :   9A;
+ 27F :   98;
+ 280 :   96;
+ 281 :   94;
+ 282 :   91;
+ 283 :   8F;
+ 284 :   8D;
+ 285 :   8B;
+ 286 :   89;
+ 287 :   87;
+ 288 :   85;
+ 289 :   82;
+ 28A :   80;
+ 28B :   7E;
+ 28C :   7C;
+ 28D :   7A;
+ 28E :   78;
+ 28F :   76;
+ 290 :   74;
+ 291 :   72;
+ 292 :   70;
+ 293 :   6E;
+ 294 :   6C;
+ 295 :   6A;
+ 296 :   68;
+ 297 :   67;
+ 298 :   65;
+ 299 :   63;
+ 29A :   61;
+ 29B :   5F;
+ 29C :   5D;
+ 29D :   5C;
+ 29E :   5A;
+ 29F :   58;
+ 2A0 :   56;
+ 2A1 :   54;
+ 2A2 :   53;
+ 2A3 :   51;
+ 2A4 :   4F;
+ 2A5 :   4E;
+ 2A6 :   4C;
+ 2A7 :   4A;
+ 2A8 :   49;
+ 2A9 :   47;
+ 2AA :   46;
+ 2AB :   44;
+ 2AC :   42;
+ 2AD :   41;
+ 2AE :   3F;
+ 2AF :   3E;
+ 2B0 :   3C;
+ 2B1 :   3B;
+ 2B2 :   39;
+ 2B3 :   38;
+ 2B4 :   37;
+ 2B5 :   35;
+ 2B6 :   34;
+ 2B7 :   32;
+ 2B8 :   31;
+ 2B9 :   30;
+ 2BA :   2E;
+ 2BB :   2D;
+ 2BC :   2C;
+ 2BD :   2B;
+ 2BE :   29;
+ 2BF :   28;
+ 2C0 :   27;
+ 2C1 :   26;
+ 2C2 :   25;
+ 2C3 :   23;
+ 2C4 :   22;
+ 2C5 :   21;
+ 2C6 :   20;
+ 2C7 :   1F;
+ 2C8 :   1E;
+ 2C9 :   1D;
+ 2CA :   1C;
+ 2CB :   1B;
+ 2CC :   1A;
+ 2CD :   19;
+ 2CE :   18;
+ 2CF :   17;
+ 2D0 :   16;
+ 2D1 :   15;
+ 2D2 :   14;
+ 2D3 :   13;
+ 2D4 :   13;
+ 2D5 :   12;
+ 2D6 :   11;
+ 2D7 :   10;
+ 2D8 :    F;
+ 2D9 :    F;
+ 2DA :    E;
+ 2DB :    D;
+ 2DC :    C;
+ 2DD :    C;
+ 2DE :    B;
+ 2DF :    A;
+ 2E0 :    A;
+ 2E1 :    9;
+ 2E2 :    9;
+ 2E3 :    8;
+ 2E4 :    8;
+ 2E5 :    7;
+ 2E6 :    6;
+ 2E7 :    6;
+ 2E8 :    6;
+ 2E9 :    5;
+ 2EA :    5;
+ 2EB :    4;
+ 2EC :    4;
+ 2ED :    3;
+ 2EE :    3;
+ 2EF :    3;
+ 2F0 :    2;
+ 2F1 :    2;
+ 2F2 :    2;
+ 2F3 :    2;
+ 2F4 :    1;
+ 2F5 :    1;
+ 2F6 :    1;
+ 2F7 :    1;
+ 2F8 :    1;
+ 2F9 :    0;
+ 2FA :    0;
+ 2FB :    0;
+ 2FC :    0;
+ 2FD :    0;
+ 2FE :    0;
+ 2FF :    0;
+ 300 :    0;
+ 301 :    0;
+ 302 :    0;
+ 303 :    0;
+ 304 :    0;
+ 305 :    0;
+ 306 :    0;
+ 307 :    0;
+ 308 :    1;
+ 309 :    1;
+ 30A :    1;
+ 30B :    1;
+ 30C :    1;
+ 30D :    2;
+ 30E :    2;
+ 30F :    2;
+ 310 :    2;
+ 311 :    3;
+ 312 :    3;
+ 313 :    3;
+ 314 :    4;
+ 315 :    4;
+ 316 :    5;
+ 317 :    5;
+ 318 :    6;
+ 319 :    6;
+ 31A :    6;
+ 31B :    7;
+ 31C :    8;
+ 31D :    8;
+ 31E :    9;
+ 31F :    9;
+ 320 :    A;
+ 321 :    A;
+ 322 :    B;
+ 323 :    C;
+ 324 :    C;
+ 325 :    D;
+ 326 :    E;
+ 327 :    F;
+ 328 :    F;
+ 329 :   10;
+ 32A :   11;
+ 32B :   12;
+ 32C :   13;
+ 32D :   13;
+ 32E :   14;
+ 32F :   15;
+ 330 :   16;
+ 331 :   17;
+ 332 :   18;
+ 333 :   19;
+ 334 :   1A;
+ 335 :   1B;
+ 336 :   1C;
+ 337 :   1D;
+ 338 :   1E;
+ 339 :   1F;
+ 33A :   20;
+ 33B :   21;
+ 33C :   22;
+ 33D :   23;
+ 33E :   25;
+ 33F :   26;
+ 340 :   27;
+ 341 :   28;
+ 342 :   29;
+ 343 :   2B;
+ 344 :   2C;
+ 345 :   2D;
+ 346 :   2E;
+ 347 :   30;
+ 348 :   31;
+ 349 :   32;
+ 34A :   34;
+ 34B :   35;
+ 34C :   37;
+ 34D :   38;
+ 34E :   39;
+ 34F :   3B;
+ 350 :   3C;
+ 351 :   3E;
+ 352 :   3F;
+ 353 :   41;
+ 354 :   42;
+ 355 :   44;
+ 356 :   46;
+ 357 :   47;
+ 358 :   49;
+ 359 :   4A;
+ 35A :   4C;
+ 35B :   4E;
+ 35C :   4F;
+ 35D :   51;
+ 35E :   53;
+ 35F :   54;
+ 360 :   56;
+ 361 :   58;
+ 362 :   5A;
+ 363 :   5C;
+ 364 :   5D;
+ 365 :   5F;
+ 366 :   61;
+ 367 :   63;
+ 368 :   65;
+ 369 :   67;
+ 36A :   68;
+ 36B :   6A;
+ 36C :   6C;
+ 36D :   6E;
+ 36E :   70;
+ 36F :   72;
+ 370 :   74;
+ 371 :   76;
+ 372 :   78;
+ 373 :   7A;
+ 374 :   7C;
+ 375 :   7E;
+ 376 :   80;
+ 377 :   82;
+ 378 :   85;
+ 379 :   87;
+ 37A :   89;
+ 37B :   8B;
+ 37C :   8D;
+ 37D :   8F;
+ 37E :   91;
+ 37F :   94;
+ 380 :   96;
+ 381 :   98;
+ 382 :   9A;
+ 383 :   9D;
+ 384 :   9F;
+ 385 :   A1;
+ 386 :   A3;
+ 387 :   A6;
+ 388 :   A8;
+ 389 :   AA;
+ 38A :   AD;
+ 38B :   AF;
+ 38C :   B1;
+ 38D :   B4;
+ 38E :   B6;
+ 38F :   B9;
+ 390 :   BB;
+ 391 :   BD;
+ 392 :   C0;
+ 393 :   C2;
+ 394 :   C5;
+ 395 :   C7;
+ 396 :   CA;
+ 397 :   CC;
+ 398 :   CF;
+ 399 :   D1;
+ 39A :   D4;
+ 39B :   D6;
+ 39C :   D9;
+ 39D :   DC;
+ 39E :   DE;
+ 39F :   E1;
+ 3A0 :   E3;
+ 3A1 :   E6;
+ 3A2 :   E9;
+ 3A3 :   EB;
+ 3A4 :   EE;
+ 3A5 :   F1;
+ 3A6 :   F3;
+ 3A7 :   F6;
+ 3A8 :   F9;
+ 3A9 :   FB;
+ 3AA :   FE;
+ 3AB :  101;
+ 3AC :  103;
+ 3AD :  106;
+ 3AE :  109;
+ 3AF :  10C;
+ 3B0 :  10E;
+ 3B1 :  111;
+ 3B2 :  114;
+ 3B3 :  117;
+ 3B4 :  11A;
+ 3B5 :  11C;
+ 3B6 :  11F;
+ 3B7 :  122;
+ 3B8 :  125;
+ 3B9 :  128;
+ 3BA :  12A;
+ 3BB :  12D;
+ 3BC :  130;
+ 3BD :  133;
+ 3BE :  136;
+ 3BF :  139;
+ 3C0 :  13C;
+ 3C1 :  13F;
+ 3C2 :  142;
+ 3C3 :  144;
+ 3C4 :  147;
+ 3C5 :  14A;
+ 3C6 :  14D;
+ 3C7 :  150;
+ 3C8 :  153;
+ 3C9 :  156;
+ 3CA :  159;
+ 3CB :  15C;
+ 3CC :  15F;
+ 3CD :  162;
+ 3CE :  165;
+ 3CF :  168;
+ 3D0 :  16B;
+ 3D1 :  16E;
+ 3D2 :  171;
+ 3D3 :  174;
+ 3D4 :  177;
+ 3D5 :  17A;
+ 3D6 :  17D;
+ 3D7 :  180;
+ 3D8 :  183;
+ 3D9 :  186;
+ 3DA :  189;
+ 3DB :  18C;
+ 3DC :  18F;
+ 3DD :  192;
+ 3DE :  196;
+ 3DF :  199;
+ 3E0 :  19C;
+ 3E1 :  19F;
+ 3E2 :  1A2;
+ 3E3 :  1A5;
+ 3E4 :  1A8;
+ 3E5 :  1AB;
+ 3E6 :  1AE;
+ 3E7 :  1B1;
+ 3E8 :  1B4;
+ 3E9 :  1B8;
+ 3EA :  1BB;
+ 3EB :  1BE;
+ 3EC :  1C1;
+ 3ED :  1C4;
+ 3EE :  1C7;
+ 3EF :  1CA;
+ 3F0 :  1CD;
+ 3F1 :  1D0;
+ 3F2 :  1D4;
+ 3F3 :  1D7;
+ 3F4 :  1DA;
+ 3F5 :  1DD;
+ 3F6 :  1E0;
+ 3F7 :  1E3;
+ 3F8 :  1E6;
+ 3F9 :  1EA;
+ 3FA :  1ED;
+ 3FB :  1F0;
+ 3FC :  1F3;
+ 3FD :  1F6;
+ 3FE :  1F9;
+ 3FF :  1FC;
+END
diff --git a/part_3/ex12/sin_gen_scripts/rom_data.mif b/part_3/ex12/sin_gen_scripts/rom_data.mif
new file mode 100755
index 0000000..a688b6f
--- /dev/null
+++ b/part_3/ex12/sin_gen_scripts/rom_data.mif
@@ -0,0 +1,1032 @@
+-- ROM Initialization file
+WIDTH = 10;
+DEPTH = 1024;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+   0 :  200;
+   1 :  203;
+   2 :  206;
+   3 :  209;
+   4 :  20C;
+   5 :  20F;
+   6 :  212;
+   7 :  215;
+   8 :  219;
+   9 :  21C;
+   A :  21F;
+   B :  222;
+   C :  225;
+   D :  228;
+   E :  22B;
+   F :  22F;
+  10 :  232;
+  11 :  235;
+  12 :  238;
+  13 :  23B;
+  14 :  23E;
+  15 :  241;
+  16 :  244;
+  17 :  247;
+  18 :  24B;
+  19 :  24E;
+  1A :  251;
+  1B :  254;
+  1C :  257;
+  1D :  25A;
+  1E :  25D;
+  1F :  260;
+  20 :  263;
+  21 :  266;
+  22 :  269;
+  23 :  26D;
+  24 :  270;
+  25 :  273;
+  26 :  276;
+  27 :  279;
+  28 :  27C;
+  29 :  27F;
+  2A :  282;
+  2B :  285;
+  2C :  288;
+  2D :  28B;
+  2E :  28E;
+  2F :  291;
+  30 :  294;
+  31 :  297;
+  32 :  29A;
+  33 :  29D;
+  34 :  2A0;
+  35 :  2A3;
+  36 :  2A6;
+  37 :  2A9;
+  38 :  2AC;
+  39 :  2AF;
+  3A :  2B2;
+  3B :  2B5;
+  3C :  2B8;
+  3D :  2BB;
+  3E :  2BD;
+  3F :  2C0;
+  40 :  2C3;
+  41 :  2C6;
+  42 :  2C9;
+  43 :  2CC;
+  44 :  2CF;
+  45 :  2D2;
+  46 :  2D5;
+  47 :  2D7;
+  48 :  2DA;
+  49 :  2DD;
+  4A :  2E0;
+  4B :  2E3;
+  4C :  2E5;
+  4D :  2E8;
+  4E :  2EB;
+  4F :  2EE;
+  50 :  2F1;
+  51 :  2F3;
+  52 :  2F6;
+  53 :  2F9;
+  54 :  2FC;
+  55 :  2FE;
+  56 :  301;
+  57 :  304;
+  58 :  306;
+  59 :  309;
+  5A :  30C;
+  5B :  30E;
+  5C :  311;
+  5D :  314;
+  5E :  316;
+  5F :  319;
+  60 :  31C;
+  61 :  31E;
+  62 :  321;
+  63 :  323;
+  64 :  326;
+  65 :  329;
+  66 :  32B;
+  67 :  32E;
+  68 :  330;
+  69 :  333;
+  6A :  335;
+  6B :  338;
+  6C :  33A;
+  6D :  33D;
+  6E :  33F;
+  6F :  342;
+  70 :  344;
+  71 :  346;
+  72 :  349;
+  73 :  34B;
+  74 :  34E;
+  75 :  350;
+  76 :  352;
+  77 :  355;
+  78 :  357;
+  79 :  359;
+  7A :  35C;
+  7B :  35E;
+  7C :  360;
+  7D :  362;
+  7E :  365;
+  7F :  367;
+  80 :  369;
+  81 :  36B;
+  82 :  36E;
+  83 :  370;
+  84 :  372;
+  85 :  374;
+  86 :  376;
+  87 :  378;
+  88 :  37A;
+  89 :  37D;
+  8A :  37F;
+  8B :  381;
+  8C :  383;
+  8D :  385;
+  8E :  387;
+  8F :  389;
+  90 :  38B;
+  91 :  38D;
+  92 :  38F;
+  93 :  391;
+  94 :  393;
+  95 :  395;
+  96 :  397;
+  97 :  398;
+  98 :  39A;
+  99 :  39C;
+  9A :  39E;
+  9B :  3A0;
+  9C :  3A2;
+  9D :  3A3;
+  9E :  3A5;
+  9F :  3A7;
+  A0 :  3A9;
+  A1 :  3AB;
+  A2 :  3AC;
+  A3 :  3AE;
+  A4 :  3B0;
+  A5 :  3B1;
+  A6 :  3B3;
+  A7 :  3B5;
+  A8 :  3B6;
+  A9 :  3B8;
+  AA :  3B9;
+  AB :  3BB;
+  AC :  3BD;
+  AD :  3BE;
+  AE :  3C0;
+  AF :  3C1;
+  B0 :  3C3;
+  B1 :  3C4;
+  B2 :  3C6;
+  B3 :  3C7;
+  B4 :  3C8;
+  B5 :  3CA;
+  B6 :  3CB;
+  B7 :  3CD;
+  B8 :  3CE;
+  B9 :  3CF;
+  BA :  3D1;
+  BB :  3D2;
+  BC :  3D3;
+  BD :  3D4;
+  BE :  3D6;
+  BF :  3D7;
+  C0 :  3D8;
+  C1 :  3D9;
+  C2 :  3DA;
+  C3 :  3DC;
+  C4 :  3DD;
+  C5 :  3DE;
+  C6 :  3DF;
+  C7 :  3E0;
+  C8 :  3E1;
+  C9 :  3E2;
+  CA :  3E3;
+  CB :  3E4;
+  CC :  3E5;
+  CD :  3E6;
+  CE :  3E7;
+  CF :  3E8;
+  D0 :  3E9;
+  D1 :  3EA;
+  D2 :  3EB;
+  D3 :  3EC;
+  D4 :  3EC;
+  D5 :  3ED;
+  D6 :  3EE;
+  D7 :  3EF;
+  D8 :  3F0;
+  D9 :  3F0;
+  DA :  3F1;
+  DB :  3F2;
+  DC :  3F3;
+  DD :  3F3;
+  DE :  3F4;
+  DF :  3F5;
+  E0 :  3F5;
+  E1 :  3F6;
+  E2 :  3F6;
+  E3 :  3F7;
+  E4 :  3F7;
+  E5 :  3F8;
+  E6 :  3F9;
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+ 3FB :  1F0;
+ 3FC :  1F3;
+ 3FD :  1F6;
+ 3FE :  1F9;
+ 3FF :  1FC;
+END
diff --git a/part_3/ex12/sin_gen_scripts/sinegen.m b/part_3/ex12/sin_gen_scripts/sinegen.m
new file mode 100755
index 0000000..1c0f400
--- /dev/null
+++ b/part_3/ex12/sin_gen_scripts/sinegen.m
@@ -0,0 +1,43 @@
+% Purpose:  MATLAB script to produce contents of a ROM that stores
+%           one cycle of sinewave
+% Inputs:   None
+% Outputs:  rom_data.mif file
+% Author:   Peter Cheung
+% Version: 	1.0
+% Date:			20 Nov 2011
+	
+DEPTH = 1024;		% Size of ROM
+WIDTH = 10;			% Size of data in bits
+OUTMAX = 2^WIDTH - 1;	% Amplitude of sinewave
+
+filename = 'rom_data.mif';
+fid = fopen(filename,'w');
+
+fprintf(fid,'-- ROM Initialization file\n');
+fprintf(fid,'WIDTH = %d;\n',WIDTH);
+fprintf(fid,'DEPTH = %d;\n',DEPTH);
+fprintf(fid,'ADDRESS_RADIX = HEX;\n');
+fprintf(fid,'DATA_RADIX = HEX;\n');
+fprintf(fid,'CONTENT\nBEGIN\n');
+
+for address = 0:1023
+	angle = (address*2*pi)/DEPTH;
+	sine_value = sin(angle);
+	data = (sine_value*0.5*OUTMAX) + OUTMAX*0.5;
+	
+	fprintf(fid,'%4X : %4X;\n',address,int16(data));
+end
+
+fprintf(fid,'END\n');
+fclose(fid);
+disp('Finished');
+
+
+
+
+
+
+
+
+
+
diff --git a/part_3/ex12/sin_gen_scripts/sinegen.py b/part_3/ex12/sin_gen_scripts/sinegen.py
new file mode 100755
index 0000000..9dba855
--- /dev/null
+++ b/part_3/ex12/sin_gen_scripts/sinegen.py
@@ -0,0 +1,33 @@
+# sinegen.py - Generate sinewave table
+#  ... for use with Altera ROMs
+# 
+from math import sin, cos, radians
+
+DEPTH = 1024  # Size of ROM
+WIDTH = 10   # Size of data in bits
+OUTMAX = 2**WIDTH - 1   # Amplitude of sinewave
+
+filename = "rom_data.mif"
+f = open(filename,'w')
+
+#  Header for the .mif file
+print >> f, "-- ROM Initialization file\n"
+print >> f, "DEPTH = %d;" % DEPTH
+print >> f, "WIDTH = %d;" % WIDTH
+print >> f, "ADDRESS_RADIX = HEX;"
+print >> f, "DATA_RADIX = HEX;\n"
+print >> f, "CONTENT\nBEGIN\n"
+
+for address in range(DEPTH):
+	angle = (address*2*pi)/DEPTH
+	sine_value = sin(angle)
+	data = int((sine_value)*0.5*OUTMAX)+OUTMAX/2
+	
+	print "%4x : %4x;" % (address, data)
+	print >> f, "%4x : %4x;" % (address, data)
+
+print >> f, "END;\n"
+
+f.close()
+
+
diff --git a/part_3/ex12/verilog_files/hex_to_7seg.v b/part_3/ex12/verilog_files/hex_to_7seg.v
new file mode 100755
index 0000000..82aa9a5
--- /dev/null
+++ b/part_3/ex12/verilog_files/hex_to_7seg.v
@@ -0,0 +1,27 @@
+module hex_to_7seg (out, in);
+
+	output [6:0] out;
+	input [3:0] in;
+	
+	reg [6:0] out;
+	
+	always @ (*)
+		case(in)
+			4'h0: out = 7'b1000000;
+			4'h1: out = 7'b1111001;
+			4'h2: out = 7'b0100100;
+			4'h3: out = 7'b0110000;
+			4'h4: out = 7'b0011001;
+			4'h5: out = 7'b0010010;
+			4'h6: out = 7'b0000010;
+			4'h7: out = 7'b1111000;
+			4'h8: out = 7'b0000000;
+			4'h9: out = 7'b0011000;
+			4'ha: out = 7'b0001000;
+			4'hb: out = 7'b0000011;
+			4'hc: out = 7'b1000110;
+			4'hd: out = 7'b0100001;
+			4'he: out = 7'b0000110;
+			4'hf: out = 7'b0001110;
+		endcase
+endmodule
author	zedarider <ymherklotz@gmail.com>	2016-12-01 23:57:19 +0000
committer	zedarider <ymherklotz@gmail.com>	2016-12-01 23:57:19 +0000
commit	81337eb41dca51fcdba7572b0449927732f4f3b5 (patch)
tree	e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex12
parent	6b492b7687c87f80bd530dda5a769c635b855ea4 (diff)
download	VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip