adding part 2 and 3

author: zedarider <ymherklotz@gmail.com> 2016-12-01 23:57:19 +0000
committer: zedarider <ymherklotz@gmail.com> 2016-12-01 23:57:19 +0000
commit: 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch)
tree: e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex13/db
parent: 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff)
download: VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz
VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip
74 files changed, 986 insertions, 0 deletions
diff --git a/part_3/ex13/db/.cmp.kpt b/part_3/ex13/db/.cmp.kpt
new file mode 100755
index 0000000..957fbc6
--- /dev/null
+++ b/part_3/ex13/db/.cmp.kpt
diff --git a/part_3/ex13/db/altsyncram_6ng1.tdf b/part_3/ex13/db/altsyncram_6ng1.tdf
new file mode 100755
index 0000000..e896d11
--- /dev/null
+++ b/part_3/ex13/db/altsyncram_6ng1.tdf
@@ -0,0 +1,264 @@
+--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./rom_data/rom_data.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=10 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 16.0 cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
+RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M10K 1 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_6ng1
+( 
+	address_a[9..0]	:	input;
+	clock0	:	input;
+	q_a[9..0]	:	output;
+) 
+VARIABLE 
+	ram_block1a0 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a8 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a9 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[9..0]	: WIRE;
+
+BEGIN 
+	ram_block1a[9..0].clk0 = clock0;
+	ram_block1a[9..0].portaaddr[] = ( address_a_wire[9..0]);
+	ram_block1a[9..0].portare = B"1111111111";
+	address_a_wire[] = address_a[];
+	q_a[] = ( ram_block1a[9..0].portadataout[0..0]);
+END;
+--VALID FILE
diff --git a/part_3/ex13/db/ex10.(0).cnf.cdb b/part_3/ex13/db/ex10.(0).cnf.cdb
new file mode 100755
index 0000000..f92a3e3
--- /dev/null
+++ b/part_3/ex13/db/ex10.(0).cnf.cdb
diff --git a/part_3/ex13/db/ex10.(0).cnf.hdb b/part_3/ex13/db/ex10.(0).cnf.hdb
new file mode 100755
index 0000000..202a1e2
--- /dev/null
+++ b/part_3/ex13/db/ex10.(0).cnf.hdb
diff --git a/part_3/ex13/db/ex10.(1).cnf.cdb b/part_3/ex13/db/ex10.(1).cnf.cdb
new file mode 100755
index 0000000..2d16e9a
--- /dev/null
+++ b/part_3/ex13/db/ex10.(1).cnf.cdb
diff --git a/part_3/ex13/db/ex10.(1).cnf.hdb b/part_3/ex13/db/ex10.(1).cnf.hdb
new file mode 100755
index 0000000..8e48fa4
--- /dev/null
+++ b/part_3/ex13/db/ex10.(1).cnf.hdb
diff --git a/part_3/ex13/db/ex10.(2).cnf.cdb b/part_3/ex13/db/ex10.(2).cnf.cdb
new file mode 100755
index 0000000..42be68b
--- /dev/null
+++ b/part_3/ex13/db/ex10.(2).cnf.cdb
diff --git a/part_3/ex13/db/ex10.(2).cnf.hdb b/part_3/ex13/db/ex10.(2).cnf.hdb
new file mode 100755
index 0000000..485cbbc
--- /dev/null
+++ b/part_3/ex13/db/ex10.(2).cnf.hdb
diff --git a/part_3/ex13/db/ex10.(3).cnf.cdb b/part_3/ex13/db/ex10.(3).cnf.cdb
new file mode 100755
index 0000000..cb20763
--- /dev/null
+++ b/part_3/ex13/db/ex10.(3).cnf.cdb
diff --git a/part_3/ex13/db/ex10.(3).cnf.hdb b/part_3/ex13/db/ex10.(3).cnf.hdb
new file mode 100755
index 0000000..6eeb420
--- /dev/null
+++ b/part_3/ex13/db/ex10.(3).cnf.hdb
diff --git a/part_3/ex13/db/ex10.(4).cnf.cdb b/part_3/ex13/db/ex10.(4).cnf.cdb
new file mode 100755
index 0000000..1cd5ccf
--- /dev/null
+++ b/part_3/ex13/db/ex10.(4).cnf.cdb
diff --git a/part_3/ex13/db/ex10.(4).cnf.hdb b/part_3/ex13/db/ex10.(4).cnf.hdb
new file mode 100755
index 0000000..756157f
--- /dev/null
+++ b/part_3/ex13/db/ex10.(4).cnf.hdb
diff --git a/part_3/ex13/db/ex10.(5).cnf.cdb b/part_3/ex13/db/ex10.(5).cnf.cdb
new file mode 100755
index 0000000..229cabc
--- /dev/null
+++ b/part_3/ex13/db/ex10.(5).cnf.cdb
diff --git a/part_3/ex13/db/ex10.(5).cnf.hdb b/part_3/ex13/db/ex10.(5).cnf.hdb
new file mode 100755
index 0000000..921436a
--- /dev/null
+++ b/part_3/ex13/db/ex10.(5).cnf.hdb
diff --git a/part_3/ex13/db/ex10.(6).cnf.cdb b/part_3/ex13/db/ex10.(6).cnf.cdb
new file mode 100755
index 0000000..3d68a80
--- /dev/null
+++ b/part_3/ex13/db/ex10.(6).cnf.cdb
diff --git a/part_3/ex13/db/ex10.(6).cnf.hdb b/part_3/ex13/db/ex10.(6).cnf.hdb
new file mode 100755
index 0000000..2976597
--- /dev/null
+++ b/part_3/ex13/db/ex10.(6).cnf.hdb
diff --git a/part_3/ex13/db/ex10.(7).cnf.cdb b/part_3/ex13/db/ex10.(7).cnf.cdb
new file mode 100755
index 0000000..bfe231a
--- /dev/null
+++ b/part_3/ex13/db/ex10.(7).cnf.cdb
diff --git a/part_3/ex13/db/ex10.(7).cnf.hdb b/part_3/ex13/db/ex10.(7).cnf.hdb
new file mode 100755
index 0000000..d5b25f9
--- /dev/null
+++ b/part_3/ex13/db/ex10.(7).cnf.hdb
diff --git a/part_3/ex13/db/ex10.asm.qmsg b/part_3/ex13/db/ex10.asm.qmsg
new file mode 100755
index 0000000..35b7d69
--- /dev/null
+++ b/part_3/ex13/db/ex10.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480420509453 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480420509455 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:55:09 2016 " "Processing started: Tue Nov 29 11:55:09 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480420509455 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480420509455 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex10 -c ex10 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480420509455 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480420510202 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480420514682 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "889 " "Peak virtual memory: 889 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480420515021 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:55:15 2016 " "Processing ended: Tue Nov 29 11:55:15 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480420515021 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480420515021 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480420515021 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480420515021 ""}
diff --git a/part_3/ex13/db/ex10.asm.rdb b/part_3/ex13/db/ex10.asm.rdb
new file mode 100755
index 0000000..84d5534
--- /dev/null
+++ b/part_3/ex13/db/ex10.asm.rdb
diff --git a/part_3/ex13/db/ex10.cbx.xml b/part_3/ex13/db/ex10.cbx.xml
new file mode 100755
index 0000000..6012e60
--- /dev/null
+++ b/part_3/ex13/db/ex10.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ex10">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/part_3/ex13/db/ex10.cmp.ammdb b/part_3/ex13/db/ex10.cmp.ammdb
new file mode 100755
index 0000000..4d8ce41
--- /dev/null
+++ b/part_3/ex13/db/ex10.cmp.ammdb
diff --git a/part_3/ex13/db/ex10.cmp.bpm b/part_3/ex13/db/ex10.cmp.bpm
new file mode 100755
index 0000000..5726c8e
--- /dev/null
+++ b/part_3/ex13/db/ex10.cmp.bpm
diff --git a/part_3/ex13/db/ex10.cmp.cdb b/part_3/ex13/db/ex10.cmp.cdb
new file mode 100755
index 0000000..8432cc2
--- /dev/null
+++ b/part_3/ex13/db/ex10.cmp.cdb
diff --git a/part_3/ex13/db/ex10.cmp.hdb b/part_3/ex13/db/ex10.cmp.hdb
new file mode 100755
index 0000000..a1d26b8
--- /dev/null
+++ b/part_3/ex13/db/ex10.cmp.hdb
diff --git a/part_3/ex13/db/ex10.cmp.idb b/part_3/ex13/db/ex10.cmp.idb
new file mode 100755
index 0000000..9d9704a
--- /dev/null
+++ b/part_3/ex13/db/ex10.cmp.idb
diff --git a/part_3/ex13/db/ex10.cmp.logdb b/part_3/ex13/db/ex10.cmp.logdb
new file mode 100755
index 0000000..b33547f
--- /dev/null
+++ b/part_3/ex13/db/ex10.cmp.logdb
@@ -0,0 +1,45 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,6;0;6;0;0;6;6;0;6;6;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;6;0;6;6;0;0;6;0;0;6;6;6;6;6;6;6;6;6;6;6;6;6;6;6;6;6;6,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,DAC_CS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SDI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_LD,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PWM_OUT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_3/ex13/db/ex10.cmp.rdb b/part_3/ex13/db/ex10.cmp.rdb
new file mode 100755
index 0000000..069f9b4
--- /dev/null
+++ b/part_3/ex13/db/ex10.cmp.rdb
diff --git a/part_3/ex13/db/ex10.cmp_merge.kpt b/part_3/ex13/db/ex10.cmp_merge.kpt
new file mode 100755
index 0000000..f13b219
--- /dev/null
+++ b/part_3/ex13/db/ex10.cmp_merge.kpt
diff --git a/part_3/ex13/db/ex10.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_3/ex13/db/ex10.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..5b115d6
--- /dev/null
+++ b/part_3/ex13/db/ex10.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_3/ex13/db/ex10.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_3/ex13/db/ex10.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..3a7a497
--- /dev/null
+++ b/part_3/ex13/db/ex10.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_3/ex13/db/ex10.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_3/ex13/db/ex10.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100755
index 0000000..aa473fa
--- /dev/null
+++ b/part_3/ex13/db/ex10.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_3/ex13/db/ex10.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_3/ex13/db/ex10.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100755
index 0000000..dce4f6b
--- /dev/null
+++ b/part_3/ex13/db/ex10.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_3/ex13/db/ex10.db_info b/part_3/ex13/db/ex10.db_info
new file mode 100755
index 0000000..542ea43
--- /dev/null
+++ b/part_3/ex13/db/ex10.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 29 11:43:32 2016
diff --git a/part_3/ex13/db/ex10.eda.qmsg b/part_3/ex13/db/ex10.eda.qmsg
new file mode 100755
index 0000000..53c1569
--- /dev/null
+++ b/part_3/ex13/db/ex10.eda.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480420522473 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480420522475 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:55:22 2016 " "Processing started: Tue Nov 29 11:55:22 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480420522475 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1480420522475 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ex10 -c ex10 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1480420522475 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1480420523378 ""}
+{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." {  } {  } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1480420523410 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ex10.vo C:/New folder/ex13/simulation/modelsim/ simulation " "Generated file ex10.vo in folder \"C:/New folder/ex13/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1480420523550 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "806 " "Peak virtual memory: 806 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480420523608 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:55:23 2016 " "Processing ended: Tue Nov 29 11:55:23 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480420523608 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480420523608 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480420523608 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1480420523608 ""}
diff --git a/part_3/ex13/db/ex10.fit.qmsg b/part_3/ex13/db/ex10.fit.qmsg
new file mode 100755
index 0000000..2e5ed28
--- /dev/null
+++ b/part_3/ex13/db/ex10.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480420475022 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480420475022 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex10 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex10\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480420475281 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480420475342 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480420475342 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480420475723 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480420475857 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1480420475860 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480420485819 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 66 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 66 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480420485862 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480420485862 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480420485863 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480420485866 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480420485866 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480420485867 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480420485867 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480420485867 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480420485868 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex10.sdc " "Synopsys Design Constraints File file not found: 'ex10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480420486615 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480420486616 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480420486618 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480420486619 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480420486619 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480420486630 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480420486630 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480420486630 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480420486648 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480420486648 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480420486650 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480420491463 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480420491576 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480420492538 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480420493573 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480420494457 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480420494457 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480420495592 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X67_Y0 X77_Y10 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex13/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10"} { { 12 { 0 ""} 67 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480420500182 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480420500182 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480420503701 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480420503701 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480420503704 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.35 " "Total time spent on timing analysis during the Fitter is 0.35 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480420504656 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480420504693 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480420504978 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480420504978 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480420505260 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480420507394 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480420507648 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex13/output_files/ex10.fit.smsg " "Generated suppressed messages file C:/New folder/ex13/output_files/ex10.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480420507703 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 80 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 80 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2630 " "Peak virtual memory: 2630 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480420508113 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:55:08 2016 " "Processing ended: Tue Nov 29 11:55:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480420508113 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480420508113 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:02 " "Total CPU time (on all processors): 00:01:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480420508113 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480420508113 ""}
diff --git a/part_3/ex13/db/ex10.hier_info b/part_3/ex13/db/ex10.hier_info
new file mode 100755
index 0000000..7d5e4fe
--- /dev/null
+++ b/part_3/ex13/db/ex10.hier_info
@@ -0,0 +1,337 @@
+|ex13
+CLOCK_50 => CLOCK_50.IN5
+DAC_CS <= spi2dac:s.port4
+DAC_SDI <= spi2dac:s.port3
+DAC_LD <= spi2dac:s.port6
+DAC_SCK <= spi2dac:s.port5
+PWM_OUT <= pwm:p.port3
+
+
+|ex13|tick_5000:t
+CLOCK_IN => count[0].CLK
+CLOCK_IN => count[1].CLK
+CLOCK_IN => count[2].CLK
+CLOCK_IN => count[3].CLK
+CLOCK_IN => count[4].CLK
+CLOCK_IN => count[5].CLK
+CLOCK_IN => count[6].CLK
+CLOCK_IN => count[7].CLK
+CLOCK_IN => count[8].CLK
+CLOCK_IN => count[9].CLK
+CLOCK_IN => count[10].CLK
+CLOCK_IN => count[11].CLK
+CLOCK_IN => count[12].CLK
+CLOCK_IN => count[13].CLK
+CLOCK_IN => count[14].CLK
+CLOCK_IN => count[15].CLK
+CLOCK_IN => CLK_OUT~reg0.CLK
+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex13|counter_10:c
+clock => count[0]~reg0.CLK
+clock => count[1]~reg0.CLK
+clock => count[2]~reg0.CLK
+clock => count[3]~reg0.CLK
+clock => count[4]~reg0.CLK
+clock => count[5]~reg0.CLK
+clock => count[6]~reg0.CLK
+clock => count[7]~reg0.CLK
+clock => count[8]~reg0.CLK
+clock => count[9]~reg0.CLK
+enable => count[0]~reg0.ENA
+enable => count[1]~reg0.ENA
+enable => count[2]~reg0.ENA
+enable => count[3]~reg0.ENA
+enable => count[4]~reg0.ENA
+enable => count[5]~reg0.ENA
+enable => count[6]~reg0.ENA
+enable => count[7]~reg0.ENA
+enable => count[8]~reg0.ENA
+enable => count[9]~reg0.ENA
+count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex13|ROM:r
+address[0] => address[0].IN1
+address[1] => address[1].IN1
+address[2] => address[2].IN1
+address[3] => address[3].IN1
+address[4] => address[4].IN1
+address[5] => address[5].IN1
+address[6] => address[6].IN1
+address[7] => address[7].IN1
+address[8] => address[8].IN1
+address[9] => address[9].IN1
+clock => clock.IN1
+q[0] <= altsyncram:altsyncram_component.q_a
+q[1] <= altsyncram:altsyncram_component.q_a
+q[2] <= altsyncram:altsyncram_component.q_a
+q[3] <= altsyncram:altsyncram_component.q_a
+q[4] <= altsyncram:altsyncram_component.q_a
+q[5] <= altsyncram:altsyncram_component.q_a
+q[6] <= altsyncram:altsyncram_component.q_a
+q[7] <= altsyncram:altsyncram_component.q_a
+q[8] <= altsyncram:altsyncram_component.q_a
+q[9] <= altsyncram:altsyncram_component.q_a
+
+
+|ex13|ROM:r|altsyncram:altsyncram_component
+wren_a => ~NO_FANOUT~
+rden_a => ~NO_FANOUT~
+wren_b => ~NO_FANOUT~
+rden_b => ~NO_FANOUT~
+data_a[0] => ~NO_FANOUT~
+data_a[1] => ~NO_FANOUT~
+data_a[2] => ~NO_FANOUT~
+data_a[3] => ~NO_FANOUT~
+data_a[4] => ~NO_FANOUT~
+data_a[5] => ~NO_FANOUT~
+data_a[6] => ~NO_FANOUT~
+data_a[7] => ~NO_FANOUT~
+data_a[8] => ~NO_FANOUT~
+data_a[9] => ~NO_FANOUT~
+data_b[0] => ~NO_FANOUT~
+address_a[0] => altsyncram_6ng1:auto_generated.address_a[0]
+address_a[1] => altsyncram_6ng1:auto_generated.address_a[1]
+address_a[2] => altsyncram_6ng1:auto_generated.address_a[2]
+address_a[3] => altsyncram_6ng1:auto_generated.address_a[3]
+address_a[4] => altsyncram_6ng1:auto_generated.address_a[4]
+address_a[5] => altsyncram_6ng1:auto_generated.address_a[5]
+address_a[6] => altsyncram_6ng1:auto_generated.address_a[6]
+address_a[7] => altsyncram_6ng1:auto_generated.address_a[7]
+address_a[8] => altsyncram_6ng1:auto_generated.address_a[8]
+address_a[9] => altsyncram_6ng1:auto_generated.address_a[9]
+address_b[0] => ~NO_FANOUT~
+addressstall_a => ~NO_FANOUT~
+addressstall_b => ~NO_FANOUT~
+clock0 => altsyncram_6ng1:auto_generated.clock0
+clock1 => ~NO_FANOUT~
+clocken0 => ~NO_FANOUT~
+clocken1 => ~NO_FANOUT~
+clocken2 => ~NO_FANOUT~
+clocken3 => ~NO_FANOUT~
+aclr0 => ~NO_FANOUT~
+aclr1 => ~NO_FANOUT~
+byteena_a[0] => ~NO_FANOUT~
+byteena_b[0] => ~NO_FANOUT~
+q_a[0] <= altsyncram_6ng1:auto_generated.q_a[0]
+q_a[1] <= altsyncram_6ng1:auto_generated.q_a[1]
+q_a[2] <= altsyncram_6ng1:auto_generated.q_a[2]
+q_a[3] <= altsyncram_6ng1:auto_generated.q_a[3]
+q_a[4] <= altsyncram_6ng1:auto_generated.q_a[4]
+q_a[5] <= altsyncram_6ng1:auto_generated.q_a[5]
+q_a[6] <= altsyncram_6ng1:auto_generated.q_a[6]
+q_a[7] <= altsyncram_6ng1:auto_generated.q_a[7]
+q_a[8] <= altsyncram_6ng1:auto_generated.q_a[8]
+q_a[9] <= altsyncram_6ng1:auto_generated.q_a[9]
+q_b[0] <= <GND>
+eccstatus[0] <= <GND>
+eccstatus[1] <= <GND>
+eccstatus[2] <= <GND>
+
+
+|ex13|ROM:r|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated
+address_a[0] => ram_block1a0.PORTAADDR
+address_a[0] => ram_block1a1.PORTAADDR
+address_a[0] => ram_block1a2.PORTAADDR
+address_a[0] => ram_block1a3.PORTAADDR
+address_a[0] => ram_block1a4.PORTAADDR
+address_a[0] => ram_block1a5.PORTAADDR
+address_a[0] => ram_block1a6.PORTAADDR
+address_a[0] => ram_block1a7.PORTAADDR
+address_a[0] => ram_block1a8.PORTAADDR
+address_a[0] => ram_block1a9.PORTAADDR
+address_a[1] => ram_block1a0.PORTAADDR1
+address_a[1] => ram_block1a1.PORTAADDR1
+address_a[1] => ram_block1a2.PORTAADDR1
+address_a[1] => ram_block1a3.PORTAADDR1
+address_a[1] => ram_block1a4.PORTAADDR1
+address_a[1] => ram_block1a5.PORTAADDR1
+address_a[1] => ram_block1a6.PORTAADDR1
+address_a[1] => ram_block1a7.PORTAADDR1
+address_a[1] => ram_block1a8.PORTAADDR1
+address_a[1] => ram_block1a9.PORTAADDR1
+address_a[2] => ram_block1a0.PORTAADDR2
+address_a[2] => ram_block1a1.PORTAADDR2
+address_a[2] => ram_block1a2.PORTAADDR2
+address_a[2] => ram_block1a3.PORTAADDR2
+address_a[2] => ram_block1a4.PORTAADDR2
+address_a[2] => ram_block1a5.PORTAADDR2
+address_a[2] => ram_block1a6.PORTAADDR2
+address_a[2] => ram_block1a7.PORTAADDR2
+address_a[2] => ram_block1a8.PORTAADDR2
+address_a[2] => ram_block1a9.PORTAADDR2
+address_a[3] => ram_block1a0.PORTAADDR3
+address_a[3] => ram_block1a1.PORTAADDR3
+address_a[3] => ram_block1a2.PORTAADDR3
+address_a[3] => ram_block1a3.PORTAADDR3
+address_a[3] => ram_block1a4.PORTAADDR3
+address_a[3] => ram_block1a5.PORTAADDR3
+address_a[3] => ram_block1a6.PORTAADDR3
+address_a[3] => ram_block1a7.PORTAADDR3
+address_a[3] => ram_block1a8.PORTAADDR3
+address_a[3] => ram_block1a9.PORTAADDR3
+address_a[4] => ram_block1a0.PORTAADDR4
+address_a[4] => ram_block1a1.PORTAADDR4
+address_a[4] => ram_block1a2.PORTAADDR4
+address_a[4] => ram_block1a3.PORTAADDR4
+address_a[4] => ram_block1a4.PORTAADDR4
+address_a[4] => ram_block1a5.PORTAADDR4
+address_a[4] => ram_block1a6.PORTAADDR4
+address_a[4] => ram_block1a7.PORTAADDR4
+address_a[4] => ram_block1a8.PORTAADDR4
+address_a[4] => ram_block1a9.PORTAADDR4
+address_a[5] => ram_block1a0.PORTAADDR5
+address_a[5] => ram_block1a1.PORTAADDR5
+address_a[5] => ram_block1a2.PORTAADDR5
+address_a[5] => ram_block1a3.PORTAADDR5
+address_a[5] => ram_block1a4.PORTAADDR5
+address_a[5] => ram_block1a5.PORTAADDR5
+address_a[5] => ram_block1a6.PORTAADDR5
+address_a[5] => ram_block1a7.PORTAADDR5
+address_a[5] => ram_block1a8.PORTAADDR5
+address_a[5] => ram_block1a9.PORTAADDR5
+address_a[6] => ram_block1a0.PORTAADDR6
+address_a[6] => ram_block1a1.PORTAADDR6
+address_a[6] => ram_block1a2.PORTAADDR6
+address_a[6] => ram_block1a3.PORTAADDR6
+address_a[6] => ram_block1a4.PORTAADDR6
+address_a[6] => ram_block1a5.PORTAADDR6
+address_a[6] => ram_block1a6.PORTAADDR6
+address_a[6] => ram_block1a7.PORTAADDR6
+address_a[6] => ram_block1a8.PORTAADDR6
+address_a[6] => ram_block1a9.PORTAADDR6
+address_a[7] => ram_block1a0.PORTAADDR7
+address_a[7] => ram_block1a1.PORTAADDR7
+address_a[7] => ram_block1a2.PORTAADDR7
+address_a[7] => ram_block1a3.PORTAADDR7
+address_a[7] => ram_block1a4.PORTAADDR7
+address_a[7] => ram_block1a5.PORTAADDR7
+address_a[7] => ram_block1a6.PORTAADDR7
+address_a[7] => ram_block1a7.PORTAADDR7
+address_a[7] => ram_block1a8.PORTAADDR7
+address_a[7] => ram_block1a9.PORTAADDR7
+address_a[8] => ram_block1a0.PORTAADDR8
+address_a[8] => ram_block1a1.PORTAADDR8
+address_a[8] => ram_block1a2.PORTAADDR8
+address_a[8] => ram_block1a3.PORTAADDR8
+address_a[8] => ram_block1a4.PORTAADDR8
+address_a[8] => ram_block1a5.PORTAADDR8
+address_a[8] => ram_block1a6.PORTAADDR8
+address_a[8] => ram_block1a7.PORTAADDR8
+address_a[8] => ram_block1a8.PORTAADDR8
+address_a[8] => ram_block1a9.PORTAADDR8
+address_a[9] => ram_block1a0.PORTAADDR9
+address_a[9] => ram_block1a1.PORTAADDR9
+address_a[9] => ram_block1a2.PORTAADDR9
+address_a[9] => ram_block1a3.PORTAADDR9
+address_a[9] => ram_block1a4.PORTAADDR9
+address_a[9] => ram_block1a5.PORTAADDR9
+address_a[9] => ram_block1a6.PORTAADDR9
+address_a[9] => ram_block1a7.PORTAADDR9
+address_a[9] => ram_block1a8.PORTAADDR9
+address_a[9] => ram_block1a9.PORTAADDR9
+clock0 => ram_block1a0.CLK0
+clock0 => ram_block1a1.CLK0
+clock0 => ram_block1a2.CLK0
+clock0 => ram_block1a3.CLK0
+clock0 => ram_block1a4.CLK0
+clock0 => ram_block1a5.CLK0
+clock0 => ram_block1a6.CLK0
+clock0 => ram_block1a7.CLK0
+clock0 => ram_block1a8.CLK0
+clock0 => ram_block1a9.CLK0
+q_a[0] <= ram_block1a0.PORTADATAOUT
+q_a[1] <= ram_block1a1.PORTADATAOUT
+q_a[2] <= ram_block1a2.PORTADATAOUT
+q_a[3] <= ram_block1a3.PORTADATAOUT
+q_a[4] <= ram_block1a4.PORTADATAOUT
+q_a[5] <= ram_block1a5.PORTADATAOUT
+q_a[6] <= ram_block1a6.PORTADATAOUT
+q_a[7] <= ram_block1a7.PORTADATAOUT
+q_a[8] <= ram_block1a8.PORTADATAOUT
+q_a[9] <= ram_block1a9.PORTADATAOUT
+
+
+|ex13|spi2dac:s
+sysclk => clk_1MHz.CLK
+sysclk => ctr[0].CLK
+sysclk => ctr[1].CLK
+sysclk => ctr[2].CLK
+sysclk => ctr[3].CLK
+sysclk => ctr[4].CLK
+sysclk => sr_state~4.DATAIN
+data_in[0] => shift_reg.DATAB
+data_in[1] => shift_reg.DATAB
+data_in[2] => shift_reg.DATAB
+data_in[3] => shift_reg.DATAB
+data_in[4] => shift_reg.DATAB
+data_in[5] => shift_reg.DATAB
+data_in[6] => shift_reg.DATAB
+data_in[7] => shift_reg.DATAB
+data_in[8] => shift_reg.DATAB
+data_in[9] => shift_reg.DATAB
+load => sr_state.OUTPUTSELECT
+load => sr_state.OUTPUTSELECT
+load => sr_state.OUTPUTSELECT
+dac_sdi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE
+dac_cs <= WideNor0.DB_MAX_OUTPUT_PORT_TYPE
+dac_sck <= dac_sck.DB_MAX_OUTPUT_PORT_TYPE
+dac_ld <= Equal2.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex13|pwm:p
+clk => pwm_out~reg0.CLK
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => d[0].CLK
+clk => d[1].CLK
+clk => d[2].CLK
+clk => d[3].CLK
+clk => d[4].CLK
+clk => d[5].CLK
+clk => d[6].CLK
+clk => d[7].CLK
+clk => d[8].CLK
+clk => d[9].CLK
+data_in[0] => d[0].DATAIN
+data_in[1] => d[1].DATAIN
+data_in[2] => d[2].DATAIN
+data_in[3] => d[3].DATAIN
+data_in[4] => d[4].DATAIN
+data_in[5] => d[5].DATAIN
+data_in[6] => d[6].DATAIN
+data_in[7] => d[7].DATAIN
+data_in[8] => d[8].DATAIN
+data_in[9] => d[9].DATAIN
+load => d[0].ENA
+load => d[1].ENA
+load => d[2].ENA
+load => d[3].ENA
+load => d[4].ENA
+load => d[5].ENA
+load => d[6].ENA
+load => d[7].ENA
+load => d[8].ENA
+load => d[9].ENA
+pwm_out <= pwm_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/part_3/ex13/db/ex10.hif b/part_3/ex13/db/ex10.hif
new file mode 100755
index 0000000..426648d
--- /dev/null
+++ b/part_3/ex13/db/ex10.hif
diff --git a/part_3/ex13/db/ex10.lpc.html b/part_3/ex13/db/ex10.lpc.html
new file mode 100755
index 0000000..c558b63
--- /dev/null
+++ b/part_3/ex13/db/ex10.lpc.html
@@ -0,0 +1,114 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >p</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >s</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >r|altsyncram_component|auto_generated</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >r</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >c</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >t</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_3/ex13/db/ex10.lpc.rdb b/part_3/ex13/db/ex10.lpc.rdb
new file mode 100755
index 0000000..2f75d29
--- /dev/null
+++ b/part_3/ex13/db/ex10.lpc.rdb
diff --git a/part_3/ex13/db/ex10.lpc.txt b/part_3/ex13/db/ex10.lpc.txt
new file mode 100755
index 0000000..a7dec14
--- /dev/null
+++ b/part_3/ex13/db/ex10.lpc.txt
@@ -0,0 +1,12 @@
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                 ;
++---------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                             ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++---------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; p                                     ; 12    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; s                                     ; 12    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; r|altsyncram_component|auto_generated ; 11    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; r                                     ; 11    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; c                                     ; 2     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; t                                     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++---------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_3/ex13/db/ex10.map.ammdb b/part_3/ex13/db/ex10.map.ammdb
new file mode 100755
index 0000000..174eb00
--- /dev/null
+++ b/part_3/ex13/db/ex10.map.ammdb
diff --git a/part_3/ex13/db/ex10.map.bpm b/part_3/ex13/db/ex10.map.bpm
new file mode 100755
index 0000000..2488815
--- /dev/null
+++ b/part_3/ex13/db/ex10.map.bpm
diff --git a/part_3/ex13/db/ex10.map.cdb b/part_3/ex13/db/ex10.map.cdb
new file mode 100755
index 0000000..3686d32
--- /dev/null
+++ b/part_3/ex13/db/ex10.map.cdb
diff --git a/part_3/ex13/db/ex10.map.hdb b/part_3/ex13/db/ex10.map.hdb
new file mode 100755
index 0000000..fd7d235
--- /dev/null
+++ b/part_3/ex13/db/ex10.map.hdb
diff --git a/part_3/ex13/db/ex10.map.kpt b/part_3/ex13/db/ex10.map.kpt
new file mode 100755
index 0000000..5214b99
--- /dev/null
+++ b/part_3/ex13/db/ex10.map.kpt
diff --git a/part_3/ex13/db/ex10.map.logdb b/part_3/ex13/db/ex10.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_3/ex13/db/ex10.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_3/ex13/db/ex10.map.qmsg b/part_3/ex13/db/ex10.map.qmsg
new file mode 100755
index 0000000..4005865
--- /dev/null
+++ b/part_3/ex13/db/ex10.map.qmsg
@@ -0,0 +1,28 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480420463362 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480420463364 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:54:23 2016 " "Processing started: Tue Nov 29 11:54:23 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480420463364 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420463364 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420463365 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420463646 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420463659 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480420463871 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480420463871 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/rom.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/rom.v" { { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" {  } { { "verilog_files/ROM.v" "" { Text "C:/New folder/ex13/verilog_files/ROM.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472180 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472180 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_10.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_10.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_10 " "Found entity 1: counter_10" {  } { { "verilog_files/counter_10.v" "" { Text "C:/New folder/ex13/verilog_files/counter_10.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472181 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472181 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex13.v 1 1 " "Found 1 design units, including 1 entities, in source file ex13.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex13 " "Found entity 1: ex13" {  } { { "ex13.v" "" { Text "C:/New folder/ex13/ex13.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472183 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472183 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_5000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_5000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_5000 " "Found entity 1: tick_5000" {  } { { "verilog_files/tick_5000.v" "" { Text "C:/New folder/ex13/verilog_files/tick_5000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472184 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472184 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "C:/New folder/ex13/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472186 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472186 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "C:/New folder/ex13/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472188 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472188 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex13 " "Elaborating entity \"ex13\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480420472214 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_5000 tick_5000:t " "Elaborating entity \"tick_5000\" for hierarchy \"tick_5000:t\"" {  } { { "ex13.v" "t" { Text "C:/New folder/ex13/ex13.v" 9 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472220 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_10 counter_10:c " "Elaborating entity \"counter_10\" for hierarchy \"counter_10:c\"" {  } { { "ex13.v" "c" { Text "C:/New folder/ex13/ex13.v" 11 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472221 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:r " "Elaborating entity \"ROM\" for hierarchy \"ROM:r\"" {  } { { "ex13.v" "r" { Text "C:/New folder/ex13/ex13.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472222 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ROM:r\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ROM:r\|altsyncram:altsyncram_component\"" {  } { { "verilog_files/ROM.v" "altsyncram_component" { Text "C:/New folder/ex13/verilog_files/ROM.v" 82 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472278 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "ROM:r\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ROM:r\|altsyncram:altsyncram_component\"" {  } { { "verilog_files/ROM.v" "" { Text "C:/New folder/ex13/verilog_files/ROM.v" 82 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472289 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ROM:r\|altsyncram:altsyncram_component " "Instantiated megafunction \"ROM:r\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom_data/rom_data.mif " "Parameter \"init_file\" = \"./rom_data/rom_data.mif\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 10 " "Parameter \"width_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480420472290 ""}  } { { "verilog_files/ROM.v" "" { Text "C:/New folder/ex13/verilog_files/ROM.v" 82 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1480420472290 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6ng1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_6ng1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6ng1 " "Found entity 1: altsyncram_6ng1" {  } { { "db/altsyncram_6ng1.tdf" "" { Text "C:/New folder/ex13/db/altsyncram_6ng1.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420472331 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420472331 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_6ng1 ROM:r\|altsyncram:altsyncram_component\|altsyncram_6ng1:auto_generated " "Elaborating entity \"altsyncram_6ng1\" for hierarchy \"ROM:r\|altsyncram:altsyncram_component\|altsyncram_6ng1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472332 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:s " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:s\"" {  } { { "ex13.v" "s" { Text "C:/New folder/ex13/ex13.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472354 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:p " "Elaborating entity \"pwm\" for hierarchy \"pwm:p\"" {  } { { "ex13.v" "p" { Text "C:/New folder/ex13/ex13.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420472355 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480420472975 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480420473259 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420473259 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "115 " "Implemented 115 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480420473301 ""} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Implemented 5 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480420473301 ""} { "Info" "ICUT_CUT_TM_LCELLS" "99 " "Implemented 99 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480420473301 ""} { "Info" "ICUT_CUT_TM_RAMS" "10 " "Implemented 10 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1480420473301 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480420473301 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "902 " "Peak virtual memory: 902 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480420473313 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:54:33 2016 " "Processing ended: Tue Nov 29 11:54:33 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480420473313 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480420473313 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480420473313 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420473313 ""}
diff --git a/part_3/ex13/db/ex10.map.rdb b/part_3/ex13/db/ex10.map.rdb
new file mode 100755
index 0000000..179b6cc
--- /dev/null
+++ b/part_3/ex13/db/ex10.map.rdb
diff --git a/part_3/ex13/db/ex10.map_bb.cdb b/part_3/ex13/db/ex10.map_bb.cdb
new file mode 100755
index 0000000..72717b6
--- /dev/null
+++ b/part_3/ex13/db/ex10.map_bb.cdb
diff --git a/part_3/ex13/db/ex10.map_bb.hdb b/part_3/ex13/db/ex10.map_bb.hdb
new file mode 100755
index 0000000..c45c974
--- /dev/null
+++ b/part_3/ex13/db/ex10.map_bb.hdb
diff --git a/part_3/ex13/db/ex10.map_bb.logdb b/part_3/ex13/db/ex10.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_3/ex13/db/ex10.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_3/ex13/db/ex10.pre_map.hdb b/part_3/ex13/db/ex10.pre_map.hdb
new file mode 100755
index 0000000..06e0af3
--- /dev/null
+++ b/part_3/ex13/db/ex10.pre_map.hdb
diff --git a/part_3/ex13/db/ex10.root_partition.map.reg_db.cdb b/part_3/ex13/db/ex10.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..f90c550
--- /dev/null
+++ b/part_3/ex13/db/ex10.root_partition.map.reg_db.cdb
diff --git a/part_3/ex13/db/ex10.routing.rdb b/part_3/ex13/db/ex10.routing.rdb
new file mode 100755
index 0000000..df53e14
--- /dev/null
+++ b/part_3/ex13/db/ex10.routing.rdb
diff --git a/part_3/ex13/db/ex10.rtlv.hdb b/part_3/ex13/db/ex10.rtlv.hdb
new file mode 100755
index 0000000..5bc8c25
--- /dev/null
+++ b/part_3/ex13/db/ex10.rtlv.hdb
diff --git a/part_3/ex13/db/ex10.rtlv_sg.cdb b/part_3/ex13/db/ex10.rtlv_sg.cdb
new file mode 100755
index 0000000..5761b78
--- /dev/null
+++ b/part_3/ex13/db/ex10.rtlv_sg.cdb
diff --git a/part_3/ex13/db/ex10.rtlv_sg_swap.cdb b/part_3/ex13/db/ex10.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..15a47be
--- /dev/null
+++ b/part_3/ex13/db/ex10.rtlv_sg_swap.cdb
diff --git a/part_3/ex13/db/ex10.sld_design_entry.sci b/part_3/ex13/db/ex10.sld_design_entry.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_3/ex13/db/ex10.sld_design_entry.sci
diff --git a/part_3/ex13/db/ex10.sld_design_entry_dsc.sci b/part_3/ex13/db/ex10.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_3/ex13/db/ex10.sld_design_entry_dsc.sci
diff --git a/part_3/ex13/db/ex10.smart_action.txt b/part_3/ex13/db/ex10.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_3/ex13/db/ex10.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/part_3/ex13/db/ex10.smp_dump.txt b/part_3/ex13/db/ex10.smp_dump.txt
new file mode 100755
index 0000000..ac35ca9
--- /dev/null
+++ b/part_3/ex13/db/ex10.smp_dump.txt
@@ -0,0 +1,6 @@
+
+State Machine - |ex13|spi2dac:s|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
diff --git a/part_3/ex13/db/ex10.sta.qmsg b/part_3/ex13/db/ex10.sta.qmsg
new file mode 100755
index 0000000..24e4b2e
--- /dev/null
+++ b/part_3/ex13/db/ex10.sta.qmsg
@@ -0,0 +1,53 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480420516503 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480420516504 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:55:15 2016 " "Processing started: Tue Nov 29 11:55:15 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480420516504 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420516504 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex10 -c ex10 " "Command: quartus_sta ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420516504 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480420516627 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517014 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517173 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517173 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517220 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517220 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex10.sdc " "Synopsys Design Constraints File file not found: 'ex10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517727 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517728 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480420517728 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2dac:s\|clk_1MHz spi2dac:s\|clk_1MHz " "create_clock -period 1.000 -name spi2dac:s\|clk_1MHz spi2dac:s\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480420517728 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517728 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517730 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517731 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480420517732 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480420517739 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480420517752 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517752 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.083 " "Worst-case setup slack is -4.083" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420517753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420517753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.083            -115.939 CLOCK_50  " "   -4.083            -115.939 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420517753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.628             -60.393 spi2dac:s\|clk_1MHz  " "   -3.628             -60.393 spi2dac:s\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420517753 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517753 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.375 " "Worst-case hold slack is 0.375" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420517756 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420517756 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.375               0.000 CLOCK_50  " "    0.375               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420517756 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.682               0.000 spi2dac:s\|clk_1MHz  " "    0.682               0.000 spi2dac:s\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420517756 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517756 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517758 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517759 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420517761 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420517761 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174            -112.809 CLOCK_50  " "   -2.174            -112.809 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420517761 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -11.033 spi2dac:s\|clk_1MHz  " "   -0.394             -11.033 spi2dac:s\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420517761 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517761 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480420517771 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420517805 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420518762 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420518805 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480420518809 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420518809 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.969 " "Worst-case setup slack is -3.969" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420518810 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420518810 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.969            -113.185 CLOCK_50  " "   -3.969            -113.185 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420518810 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.808             -61.946 spi2dac:s\|clk_1MHz  " "   -3.808             -61.946 spi2dac:s\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420518810 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420518810 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.255 " "Worst-case hold slack is 0.255" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420518813 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420518813 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.255               0.000 CLOCK_50  " "    0.255               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420518813 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.675               0.000 spi2dac:s\|clk_1MHz  " "    0.675               0.000 spi2dac:s\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420518813 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420518813 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420518814 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420518816 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420518817 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420518817 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174            -108.874 CLOCK_50  " "   -2.174            -108.874 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420518817 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -10.846 spi2dac:s\|clk_1MHz  " "   -0.394             -10.846 spi2dac:s\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420518817 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420518817 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480420518828 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420518979 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420519802 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420519846 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480420519847 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420519847 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.335 " "Worst-case setup slack is -3.335" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420519849 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420519849 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.335             -41.574 CLOCK_50  " "   -3.335             -41.574 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420519849 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.741             -27.896 spi2dac:s\|clk_1MHz  " "   -1.741             -27.896 spi2dac:s\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420519849 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420519849 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.183 " "Worst-case hold slack is 0.183" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420519851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420519851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.183               0.000 CLOCK_50  " "    0.183               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420519851 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.336               0.000 spi2dac:s\|clk_1MHz  " "    0.336               0.000 spi2dac:s\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420519851 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420519851 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420519853 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420519854 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420519856 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420519856 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174             -99.704 CLOCK_50  " "   -2.174             -99.704 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420519856 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.135               0.000 spi2dac:s\|clk_1MHz  " "    0.135               0.000 spi2dac:s\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420519856 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420519856 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480420519865 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420520017 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480420520018 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420520018 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.835 " "Worst-case setup slack is -2.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420520020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420520020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.835             -32.972 CLOCK_50  " "   -2.835             -32.972 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420520020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.725             -26.254 spi2dac:s\|clk_1MHz  " "   -1.725             -26.254 spi2dac:s\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420520020 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420520020 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.172 " "Worst-case hold slack is 0.172" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420520022 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420520022 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.172               0.000 CLOCK_50  " "    0.172               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420520022 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.306               0.000 spi2dac:s\|clk_1MHz  " "    0.306               0.000 spi2dac:s\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420520022 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420520022 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420520024 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420520026 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420520027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420520027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174            -106.501 CLOCK_50  " "   -2.174            -106.501 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420520027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.147               0.000 spi2dac:s\|clk_1MHz  " "    0.147               0.000 spi2dac:s\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480420520027 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420520027 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420521129 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420521129 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1228 " "Peak virtual memory: 1228 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480420521165 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 29 11:55:21 2016 " "Processing ended: Tue Nov 29 11:55:21 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480420521165 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480420521165 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480420521165 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480420521165 ""}
diff --git a/part_3/ex13/db/ex10.sta.rdb b/part_3/ex13/db/ex10.sta.rdb
new file mode 100755
index 0000000..a8109ea
--- /dev/null
+++ b/part_3/ex13/db/ex10.sta.rdb
diff --git a/part_3/ex13/db/ex10.sta_cmp.6_slow_1100mv_85c.tdb b/part_3/ex13/db/ex10.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..6ddfb92
--- /dev/null
+++ b/part_3/ex13/db/ex10.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_3/ex13/db/ex10.tis_db_list.ddb b/part_3/ex13/db/ex10.tis_db_list.ddb
new file mode 100755
index 0000000..88225e8
--- /dev/null
+++ b/part_3/ex13/db/ex10.tis_db_list.ddb
diff --git a/part_3/ex13/db/ex10.tiscmp.fast_1100mv_0c.ddb b/part_3/ex13/db/ex10.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..eaaa215
--- /dev/null
+++ b/part_3/ex13/db/ex10.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_3/ex13/db/ex10.tiscmp.fast_1100mv_85c.ddb b/part_3/ex13/db/ex10.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..b204f74
--- /dev/null
+++ b/part_3/ex13/db/ex10.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_3/ex13/db/ex10.tiscmp.slow_1100mv_0c.ddb b/part_3/ex13/db/ex10.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..4cd76ba
--- /dev/null
+++ b/part_3/ex13/db/ex10.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_3/ex13/db/ex10.tiscmp.slow_1100mv_85c.ddb b/part_3/ex13/db/ex10.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..65c36aa
--- /dev/null
+++ b/part_3/ex13/db/ex10.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_3/ex13/db/ex10.tmw_info b/part_3/ex13/db/ex10.tmw_info
new file mode 100755
index 0000000..bc79130
--- /dev/null
+++ b/part_3/ex13/db/ex10.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:01:02
+start_analysis_synthesis:s:00:00:11-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:35-start_full_compilation
+start_assembler:s:00:00:07-start_full_compilation
+start_timing_analyzer:s:00:00:06-start_full_compilation
+start_eda_netlist_writer:s:00:00:03-start_full_compilation
diff --git a/part_3/ex13/db/ex10.vpr.ammdb b/part_3/ex13/db/ex10.vpr.ammdb
new file mode 100755
index 0000000..3683a5d
--- /dev/null
+++ b/part_3/ex13/db/ex10.vpr.ammdb
diff --git a/part_3/ex13/db/ex10_partition_pins.json b/part_3/ex13/db/ex10_partition_pins.json
new file mode 100755
index 0000000..c4da352
--- /dev/null
+++ b/part_3/ex13/db/ex10_partition_pins.json
@@ -0,0 +1,33 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "DAC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_LD",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "PWM_OUT",
+					"strict" : false
+				},
+				{
+					"name" : "CLOCK_50",
+					"strict" : false
+				}
+			]
+		}
+	]
+}
+\ No newline at end of file
diff --git a/part_3/ex13/db/prev_cmp_ex10.qmsg b/part_3/ex13/db/prev_cmp_ex10.qmsg
new file mode 100755
index 0000000..a2cf464
--- /dev/null
+++ b/part_3/ex13/db/prev_cmp_ex10.qmsg
@@ -0,0 +1,18 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480420424225 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480420424226 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 29 11:53:43 2016 " "Processing started: Tue Nov 29 11:53:43 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480420424226 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420424226 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420424227 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420424449 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420424462 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480420424690 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480420424690 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/rom_bb.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/rom_bb.v" { { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" {  } { { "verilog_files/ROM_bb.v" "" { Text "C:/New folder/ex13/verilog_files/ROM_bb.v" 35 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420433150 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420433150 ""}
+{ "Error" "EVRFX_VERI_FOUND_DUPLICATE_MODULE_DEFINITION" "ROM ROM.v(40) " "Verilog HDL error at ROM.v(40): module \"ROM\" cannot be declared more than once" {  } { { "verilog_files/ROM.v" "" { Text "C:/New folder/ex13/verilog_files/ROM.v" 40 0 0 } }  } 0 10228 "Verilog HDL error at %2!s!: module \"%1!s!\" cannot be declared more than once" 0 0 "Analysis & Synthesis" 0 -1 1480420433152 ""}
+{ "Info" "IVRFX_HDL_SEE_DECLARATION" "ROM ROM_bb.v(35) " "HDL info at ROM_bb.v(35): see declaration for object \"ROM\"" {  } { { "verilog_files/ROM_bb.v" "" { Text "C:/New folder/ex13/verilog_files/ROM_bb.v" 35 0 0 } }  } 0 10499 "HDL info at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480420433152 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/rom.v 0 0 " "Found 0 design units, including 0 entities, in source file verilog_files/rom.v" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420433153 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_10.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_10.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_10 " "Found entity 1: counter_10" {  } { { "verilog_files/counter_10.v" "" { Text "C:/New folder/ex13/verilog_files/counter_10.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420433154 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420433154 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex13.v 1 1 " "Found 1 design units, including 1 entities, in source file ex13.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex13 " "Found entity 1: ex13" {  } { { "ex13.v" "" { Text "C:/New folder/ex13/ex13.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420433157 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420433157 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_5000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_5000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_5000 " "Found entity 1: tick_5000" {  } { { "verilog_files/tick_5000.v" "" { Text "C:/New folder/ex13/verilog_files/tick_5000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420433158 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420433158 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "C:/New folder/ex13/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420433160 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420433160 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "C:/New folder/ex13/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480420433161 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420433161 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 3 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "830 " "Peak virtual memory: 830 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480420433209 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Nov 29 11:53:53 2016 " "Processing ended: Tue Nov 29 11:53:53 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480420433209 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480420433209 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480420433209 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420433209 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 3 s " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 3 warnings" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480420433803 ""}
author	zedarider <ymherklotz@gmail.com>	2016-12-01 23:57:19 +0000
committer	zedarider <ymherklotz@gmail.com>	2016-12-01 23:57:19 +0000
commit	81337eb41dca51fcdba7572b0449927732f4f3b5 (patch)
tree	e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex13/db
parent	6b492b7687c87f80bd530dda5a769c635b855ea4 (diff)
download	VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip