diff options
| author | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-12-01 23:57:19 +0000 |
| commit | 81337eb41dca51fcdba7572b0449927732f4f3b5 (patch) | |
| tree | e7b0af7afa897e754a423b44b0fcd3849afc367b /part_3/ex13/output_files/ex10.sta.summary | |
| parent | 6b492b7687c87f80bd530dda5a769c635b855ea4 (diff) | |
| download | VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.tar.gz VerilogCoursework-81337eb41dca51fcdba7572b0449927732f4f3b5.zip | |
adding part 2 and 3
Diffstat (limited to 'part_3/ex13/output_files/ex10.sta.summary')
| -rwxr-xr-x | part_3/ex13/output_files/ex10.sta.summary | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/part_3/ex13/output_files/ex10.sta.summary b/part_3/ex13/output_files/ex10.sta.summary new file mode 100755 index 0000000..314ef9e --- /dev/null +++ b/part_3/ex13/output_files/ex10.sta.summary @@ -0,0 +1,101 @@ +------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -4.083
+TNS : -115.939
+
+Type : Slow 1100mV 85C Model Setup 'spi2dac:s|clk_1MHz'
+Slack : -3.628
+TNS : -60.393
+
+Type : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.375
+TNS : 0.000
+
+Type : Slow 1100mV 85C Model Hold 'spi2dac:s|clk_1MHz'
+Slack : 0.682
+TNS : 0.000
+
+Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS : -112.809
+
+Type : Slow 1100mV 85C Model Minimum Pulse Width 'spi2dac:s|clk_1MHz'
+Slack : -0.394
+TNS : -11.033
+
+Type : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -3.969
+TNS : -113.185
+
+Type : Slow 1100mV 0C Model Setup 'spi2dac:s|clk_1MHz'
+Slack : -3.808
+TNS : -61.946
+
+Type : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.255
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Hold 'spi2dac:s|clk_1MHz'
+Slack : 0.675
+TNS : 0.000
+
+Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS : -108.874
+
+Type : Slow 1100mV 0C Model Minimum Pulse Width 'spi2dac:s|clk_1MHz'
+Slack : -0.394
+TNS : -10.846
+
+Type : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -3.335
+TNS : -41.574
+
+Type : Fast 1100mV 85C Model Setup 'spi2dac:s|clk_1MHz'
+Slack : -1.741
+TNS : -27.896
+
+Type : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.183
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Hold 'spi2dac:s|clk_1MHz'
+Slack : 0.336
+TNS : 0.000
+
+Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS : -99.704
+
+Type : Fast 1100mV 85C Model Minimum Pulse Width 'spi2dac:s|clk_1MHz'
+Slack : 0.135
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -2.835
+TNS : -32.972
+
+Type : Fast 1100mV 0C Model Setup 'spi2dac:s|clk_1MHz'
+Slack : -1.725
+TNS : -26.254
+
+Type : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.172
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Hold 'spi2dac:s|clk_1MHz'
+Slack : 0.306
+TNS : 0.000
+
+Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS : -106.501
+
+Type : Fast 1100mV 0C Model Minimum Pulse Width 'spi2dac:s|clk_1MHz'
+Slack : 0.147
+TNS : 0.000
+
+------------------------------------------------------------
|