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diff --git a/part_1/README.md b/part_1/README.md new file mode 100644 index 0000000..c787a1b --- /dev/null +++ b/part_1/README.md @@ -0,0 +1,3 @@ +# Experiment VERI: FPGA Design with Verilog (Part 1) +In this experiment we will be programming a Cyclone V FPGA from Altera on a DE1-SoC Board that was made by Terasicas +We will minsdawdaw |