5 files changed, 14 insertions, 0 deletions
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dat b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dat
new file mode 100755
index 0000000..ea67fd1
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dat
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dbs b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dbs
new file mode 100755
index 0000000..8019c2d
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.dbs
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
new file mode 100755
index 0000000..0dd84bc
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
@@ -0,0 +1,14 @@
+library verilog;
+use verilog.vl_types.all;
+entity counter_8 is
+    generic(
+        BIT_SZ          : integer := 8
+    );
+    port(
+        clock           : in     vl_logic;
+        enable          : in     vl_logic;
+        count           : out    vl_logic_vector
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BIT_SZ : constant is 1;
+end counter_8;
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.prw b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.prw
new file mode 100755
index 0000000..a7325bf
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.prw
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.psm b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.psm
new file mode 100755
index 0000000..3efd040
--- /dev/null
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/verilog.psm