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-rwxr-xr-xpart_2/ex8/output_files/ex8.map.rpt1145
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diff --git a/part_2/ex8/output_files/ex8.map.rpt b/part_2/ex8/output_files/ex8.map.rpt
index cf3e200..ace9229 100755
--- a/part_2/ex8/output_files/ex8.map.rpt
+++ b/part_2/ex8/output_files/ex8.map.rpt
@@ -1,573 +1,572 @@
-Analysis & Synthesis report for ex8
-Sun Dec 11 20:25:03 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. State Machine - |ex8|delay:DEL0|state
- 9. State Machine - |ex8|formula_fsm:FSM|state
- 10. User-Specified and Inferred Latches
- 11. Registers Removed During Synthesis
- 12. General Register Statistics
- 13. Inverted Register Statistics
- 14. Multiplexer Restructuring Statistics (Restructuring Performed)
- 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
- 16. Parameter Settings for User Entity Instance: tick_2500:TICK1
- 17. Parameter Settings for User Entity Instance: formula_fsm:FSM
- 18. Parameter Settings for User Entity Instance: delay:DEL0
- 19. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
- 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
- 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
- 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
- 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
- 24. Port Connectivity Checks: "bin2bcd_16:BCD"
- 25. Port Connectivity Checks: "delay:DEL0"
- 26. Post-Synthesis Netlist Statistics for Top Partition
- 27. Elapsed Time Per Partition
- 28. Analysis & Synthesis Messages
- 29. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+---------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Sun Dec 11 20:25:03 2016 ;
-; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Revision Name ; ex8 ;
-; Top-level Entity Name ; ex8 ;
-; Family ; Cyclone V ;
-; Logic utilization (in ALMs) ; N/A ;
-; Total registers ; 64 ;
-; Total pins ; 36 ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 0 ;
-; Total DSP Blocks ; 0 ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 ;
-; Total DLLs ; 0 ;
-+---------------------------------+---------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Device ; 5CSEMA5F31C6 ; ;
-; Top-level entity name ; ex8 ; ex8 ;
-; Family name ; Cyclone V ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; OpenCore Plus hardware evaluation ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 3 ; 3 ;
-; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-; Automatic Parallel Synthesis ; On ; On ;
-; Partial Reconfiguration Bitstream ID ; Off ; Off ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 8 ;
-; Maximum allowed ; 4 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 4 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processors 2-4 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
-; verilog_files/tick_50000.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v ; ;
-; verilog_files/LFSR.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v ; ;
-; verilog_files/hex_to_7seg.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v ; ;
-; verilog_files/bin2bcd_16.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v ; ;
-; verilog_files/add3_ge5.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v ; ;
-; verilog_files/formula_fsm.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v ; ;
-; verilog_files/delay.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v ; ;
-; verilog_files/tick_2500.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v ; ;
-; verilog_files/ex8.v ; yes ; User Verilog HDL File ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v ; ;
-+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
-
-
-+------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+--------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+--------------------------+
-; Estimate of Logic utilization (ALMs needed) ; 81 ;
-; ; ;
-; Combinational ALUT usage for logic ; 136 ;
-; -- 7 input functions ; 1 ;
-; -- 6 input functions ; 24 ;
-; -- 5 input functions ; 5 ;
-; -- 4 input functions ; 39 ;
-; -- <=3 input functions ; 67 ;
-; ; ;
-; Dedicated logic registers ; 64 ;
-; ; ;
-; I/O pins ; 36 ;
-; ; ;
-; Total DSP Blocks ; 0 ;
-; ; ;
-; Maximum fan-out node ; tick_50000:TICK0|CLK_OUT ;
-; Maximum fan-out ; 47 ;
-; Total fan-out ; 706 ;
-; Average fan-out ; 2.60 ;
-+---------------------------------------------+--------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex8 ; 136 (1) ; 64 (0) ; 0 ; 0 ; 36 ; 0 ; |ex8 ; ex8 ; work ;
-; |LFSR:LFSR0| ; 3 (3) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |ex8|LFSR:LFSR0 ; LFSR ; work ;
-; |bin2bcd_16:BCD| ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD ; bin2bcd_16 ; work ;
-; |add3_ge5:A22| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5 ; work ;
-; |add3_ge5:A26| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5 ; work ;
-; |add3_ge5:A30| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5 ; work ;
-; |add3_ge5:A34| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5 ; work ;
-; |add3_ge5:A35| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5 ; work ;
-; |delay:DEL0| ; 25 (25) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |ex8|delay:DEL0 ; delay ; work ;
-; |formula_fsm:FSM| ; 37 (37) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |ex8|formula_fsm:FSM ; formula_fsm ; work ;
-; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
-; |hex_to_7seg:SEG1| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
-; |tick_50000:TICK0| ; 36 (36) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex8|tick_50000:TICK0 ; tick_50000 ; work ;
-+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-Encoding Type: One-Hot
-+--------------------------------------------------------------------------------+
-; State Machine - |ex8|delay:DEL0|state ;
-+----------------+----------------+----------------+----------------+------------+
-; Name ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
-+----------------+----------------+----------------+----------------+------------+
-; state.IDLE ; 0 ; 0 ; 0 ; 0 ;
-; state.COUNTING ; 0 ; 0 ; 1 ; 1 ;
-; state.TIME_OUT ; 0 ; 1 ; 0 ; 1 ;
-; state.WAIT_LOW ; 1 ; 0 ; 0 ; 1 ;
-+----------------+----------------+----------------+----------------+------------+
-
-
-Encoding Type: One-Hot
-+--------------------------------------------------------------------------------------------+
-; State Machine - |ex8|formula_fsm:FSM|state ;
-+------------------------+--------------------+------------------------+---------------------+
-; Name ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
-+------------------------+--------------------+------------------------+---------------------+
-; state.WAIT_TRIGGER ; 0 ; 0 ; 0 ;
-; state.LIGHT_UP_LEDS ; 1 ; 0 ; 1 ;
-; state.WAIT_FOR_TIMEOUT ; 1 ; 1 ; 0 ;
-+------------------------+--------------------+------------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; User-Specified and Inferred Latches ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; formula_fsm:FSM|start_delay ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes ;
-; Number of user-specified and inferred latches = 1 ; ; ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
-
-
-+------------------------------------------------------------+
-; Registers Removed During Synthesis ;
-+---------------------------------------+--------------------+
-; Register name ; Reason for Removal ;
-+---------------------------------------+--------------------+
-; delay:DEL0|state~5 ; Lost fanout ;
-; delay:DEL0|state~6 ; Lost fanout ;
-; Total Number of Removed Registers = 2 ; ;
-+---------------------------------------+--------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 64 ;
-; Number of registers using Synchronous Clear ; 0 ;
-; Number of registers using Synchronous Load ; 15 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 27 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+---------------------------------------------------+
-; Inverted Register Statistics ;
-+-----------------------------------------+---------+
-; Inverted Register ; Fan out ;
-+-----------------------------------------+---------+
-; LFSR:LFSR0|COUNT[1] ; 10 ;
-; tick_50000:TICK0|count[14] ; 2 ;
-; tick_50000:TICK0|count[15] ; 2 ;
-; tick_50000:TICK0|count[0] ; 2 ;
-; tick_50000:TICK0|count[1] ; 2 ;
-; tick_50000:TICK0|count[2] ; 2 ;
-; tick_50000:TICK0|count[3] ; 2 ;
-; tick_50000:TICK0|count[6] ; 2 ;
-; tick_50000:TICK0|count[8] ; 2 ;
-; tick_50000:TICK0|count[9] ; 2 ;
-; Total number of inverted registers = 10 ; ;
-+-----------------------------------------+---------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
-; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |ex8|formula_fsm:FSM|count[4] ;
-; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |ex8|delay:DEL0|count[6] ;
-; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |ex8|delay:DEL0|count[7] ;
-; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |ex8|formula_fsm:FSM|Selector4 ;
-; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; No ; |ex8|delay:DEL0|Selector16 ;
-; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |ex8|delay:DEL0|Selector17 ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
-
-
-+---------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
-+----------------+-------+--------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+--------------------------------------+
-; NBIT ; 16 ; Signed Integer ;
-+----------------+-------+--------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_2500:TICK1 ;
-+----------------+-------+-------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+-------------------------------------+
-; NBIT ; 12 ; Signed Integer ;
-+----------------+-------+-------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
-+------------------+-------+-----------------------------------+
-; Parameter Name ; Value ; Type ;
-+------------------+-------+-----------------------------------+
-; WAIT_TRIGGER ; 00 ; Unsigned Binary ;
-; LIGHT_UP_LEDS ; 01 ; Unsigned Binary ;
-; WAIT_FOR_TIMEOUT ; 10 ; Unsigned Binary ;
-+------------------+-------+-----------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------+
-; Parameter Settings for User Entity Instance: delay:DEL0 ;
-+----------------+-------+--------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+--------------------------------+
-; BIT_SZ ; 14 ; Signed Integer ;
-; IDLE ; 00 ; Unsigned Binary ;
-; COUNTING ; 01 ; Unsigned Binary ;
-; TIME_OUT ; 10 ; Unsigned Binary ;
-; WAIT_LOW ; 11 ; Unsigned Binary ;
-+----------------+-------+--------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31" ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-; oA[3] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
-+-------+-------+----------+------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-+-------+-------+----------+------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
-+-------+-------+----------+------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-+-------+-------+----------+------------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
-+-------+-------+----------+-----------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-+-------+-------+----------+-----------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
-+-------+-------+----------+-----------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info ; Stuck at GND ;
-+-------+-------+----------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD" ;
-+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; B ; Input ; Warning ; Input port expression (7 bits) is smaller than the input port (16 bits) it drives. Extra input bit(s) "B[15..7]" will be connected to GND. ;
-; BCD_3 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; BCD_4 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "delay:DEL0" ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; N ; Input ; Warning ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives. Extra input bit(s) "N[13..7]" will be connected to GND. ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; arriav_ff ; 64 ;
-; ENA ; 13 ;
-; ENA SLD ; 14 ;
-; SLD ; 1 ;
-; plain ; 36 ;
-; arriav_lcell_comb ; 140 ;
-; arith ; 39 ;
-; 1 data inputs ; 39 ;
-; extend ; 1 ;
-; 7 data inputs ; 1 ;
-; normal ; 100 ;
-; 0 data inputs ; 2 ;
-; 1 data inputs ; 14 ;
-; 2 data inputs ; 9 ;
-; 3 data inputs ; 7 ;
-; 4 data inputs ; 39 ;
-; 5 data inputs ; 5 ;
-; 6 data inputs ; 24 ;
-; boundary_port ; 36 ;
-; ; ;
-; Max LUT depth ; 6.00 ;
-; Average LUT depth ; 2.82 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:00 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
- Info: Processing started: Sun Dec 11 20:24:53 2016
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
- Info (12023): Found entity 1: tick_50000 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/LFSR.v
- Info (12023): Found entity 1: LFSR File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
- Info (12023): Found entity 1: hex_to_7seg File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
- Info (12023): Found entity 1: counter_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v Line: 3
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
- Info (12023): Found entity 1: bin2bcd_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 12
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
- Info (12023): Found entity 1: add3_ge5 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v Line: 9
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
- Info (12023): Found entity 1: formula_fsm File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
- Info (12023): Found entity 1: delay File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v
- Info (12023): Found entity 1: tick_2500 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex8.v
- Info (12023): Found entity 1: ex8 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 1
-Info (12127): Elaborating entity "ex8" for the top level hierarchy
-Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 13
-Info (12128): Elaborating entity "tick_2500" for hierarchy "tick_2500:TICK1" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 14
-Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 15
-Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 39
-Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 58
-Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 58
-Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 16
-Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 17
-Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 24
-Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 18
-Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 26
-Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 19
-Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
-Warning (13024): Output pins are stuck at VCC or GND
- Warning (13410): Pin "HEX2[1]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
- Warning (13410): Pin "HEX2[2]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
- Warning (13410): Pin "HEX2[6]" is stuck at VCC File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
-Info (286030): Timing-Driven Synthesis is running
-Info (17049): 2 registers lost all their fanouts during netlist optimizations.
-Info (144001): Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 3 input pin(s) that do not drive logic
- Warning (15610): No output dependent on input pin "KEY[0]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
- Warning (15610): No output dependent on input pin "KEY[1]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
- Warning (15610): No output dependent on input pin "KEY[2]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
-Info (21057): Implemented 178 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 5 input pins
- Info (21059): Implemented 31 output pins
- Info (21061): Implemented 142 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
- Info: Peak virtual memory: 1054 megabytes
- Info: Processing ended: Sun Dec 11 20:25:03 2016
- Info: Elapsed time: 00:00:10
- Info: Total CPU time (on all processors): 00:00:24
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg.
-
-
+Analysis & Synthesis report for ex8
+Wed Dec 07 12:21:24 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Parallel Compilation
+ 5. Analysis & Synthesis Source Files Read
+ 6. Analysis & Synthesis Resource Usage Summary
+ 7. Analysis & Synthesis Resource Utilization by Entity
+ 8. State Machine - |ex8|delay:DEL0|state
+ 9. State Machine - |ex8|formula_fsm:FSM|state
+ 10. User-Specified and Inferred Latches
+ 11. Registers Removed During Synthesis
+ 12. General Register Statistics
+ 13. Inverted Register Statistics
+ 14. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
+ 16. Parameter Settings for User Entity Instance: tick_2500:TICK1
+ 17. Parameter Settings for User Entity Instance: formula_fsm:FSM
+ 18. Parameter Settings for User Entity Instance: delay:DEL0
+ 19. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
+ 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
+ 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
+ 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
+ 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
+ 24. Port Connectivity Checks: "bin2bcd_16:BCD"
+ 25. Port Connectivity Checks: "delay:DEL0"
+ 26. Post-Synthesis Netlist Statistics for Top Partition
+ 27. Elapsed Time Per Partition
+ 28. Analysis & Synthesis Messages
+ 29. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Wed Dec 07 12:21:23 2016 ;
+; Quartus Prime Version ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name ; ex8 ;
+; Top-level Entity Name ; ex8 ;
+; Family ; Cyclone V ;
+; Logic utilization (in ALMs) ; N/A ;
+; Total registers ; 67 ;
+; Total pins ; 36 ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 0 ;
+; Total DSP Blocks ; 0 ;
+; Total HSSI RX PCSs ; 0 ;
+; Total HSSI PMA RX Deserializers ; 0 ;
+; Total HSSI TX PCSs ; 0 ;
+; Total HSSI PMA TX Serializers ; 0 ;
+; Total PLLs ; 0 ;
+; Total DLLs ; 0 ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device ; 5CSEMA5F31C6 ; ;
+; Top-level entity name ; ex8 ; ex8 ;
+; Family name ; Cyclone V ; Cyclone V ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Infer RAMs from Raw Logic ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; On ; On ;
+; Report Parameter Settings ; On ; On ;
+; Report Source Assignments ; On ; On ;
+; Report Connectivity Checks ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 3 ; 3 ;
+; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
+; Synthesis Seed ; 1 ; 1 ;
+; Automatic Parallel Synthesis ; On ; On ;
+; Partial Reconfiguration Bitstream ID ; Off ; Off ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processors 2-4 ; 0.0% ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------+---------+
+; verilog_files/tick_50000.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v ; ;
+; verilog_files/LFSR.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v ; ;
+; verilog_files/hex_to_7seg.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v ; ;
+; verilog_files/bin2bcd_16.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v ; ;
+; verilog_files/add3_ge5.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v ; ;
+; verilog_files/formula_fsm.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v ; ;
+; verilog_files/delay.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v ; ;
+; verilog_files/tick_2500.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v ; ;
+; verilog_files/ex8.v ; yes ; User Verilog HDL File ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v ; ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------+---------+
+
+
++------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+--------------------------+
+; Resource ; Usage ;
++---------------------------------------------+--------------------------+
+; Estimate of Logic utilization (ALMs needed) ; 86 ;
+; ; ;
+; Combinational ALUT usage for logic ; 142 ;
+; -- 7 input functions ; 0 ;
+; -- 6 input functions ; 29 ;
+; -- 5 input functions ; 5 ;
+; -- 4 input functions ; 40 ;
+; -- <=3 input functions ; 68 ;
+; ; ;
+; Dedicated logic registers ; 67 ;
+; ; ;
+; I/O pins ; 36 ;
+; ; ;
+; Total DSP Blocks ; 0 ;
+; ; ;
+; Maximum fan-out node ; tick_50000:TICK0|CLK_OUT ;
+; Maximum fan-out ; 50 ;
+; Total fan-out ; 739 ;
+; Average fan-out ; 2.63 ;
++---------------------------------------------+--------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+; |ex8 ; 142 (1) ; 67 (0) ; 0 ; 0 ; 36 ; 0 ; |ex8 ; ex8 ; work ;
+; |LFSR:LFSR0| ; 3 (3) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |ex8|LFSR:LFSR0 ; LFSR ; work ;
+; |bin2bcd_16:BCD| ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD ; bin2bcd_16 ; work ;
+; |add3_ge5:A22| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5 ; work ;
+; |add3_ge5:A26| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5 ; work ;
+; |add3_ge5:A30| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5 ; work ;
+; |add3_ge5:A35| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5 ; work ;
+; |delay:DEL0| ; 25 (25) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |ex8|delay:DEL0 ; delay ; work ;
+; |formula_fsm:FSM| ; 43 (43) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; |ex8|formula_fsm:FSM ; formula_fsm ; work ;
+; |hex_to_7seg:SEG0| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG0 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG1| ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG1 ; hex_to_7seg ; work ;
+; |hex_to_7seg:SEG2| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |ex8|hex_to_7seg:SEG2 ; hex_to_7seg ; work ;
+; |tick_50000:TICK0| ; 36 (36) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; |ex8|tick_50000:TICK0 ; tick_50000 ; work ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
+Encoding Type: One-Hot
++--------------------------------------------------------------------------------+
+; State Machine - |ex8|delay:DEL0|state ;
++----------------+----------------+----------------+----------------+------------+
+; Name ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
++----------------+----------------+----------------+----------------+------------+
+; state.IDLE ; 0 ; 0 ; 0 ; 0 ;
+; state.COUNTING ; 0 ; 0 ; 1 ; 1 ;
+; state.TIME_OUT ; 0 ; 1 ; 0 ; 1 ;
+; state.WAIT_LOW ; 1 ; 0 ; 0 ; 1 ;
++----------------+----------------+----------------+----------------+------------+
+
+
+Encoding Type: One-Hot
++--------------------------------------------------------------------------------------------+
+; State Machine - |ex8|formula_fsm:FSM|state ;
++------------------------+--------------------+------------------------+---------------------+
+; Name ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
++------------------------+--------------------+------------------------+---------------------+
+; state.WAIT_TRIGGER ; 0 ; 0 ; 0 ;
+; state.LIGHT_UP_LEDS ; 1 ; 0 ; 1 ;
+; state.WAIT_FOR_TIMEOUT ; 1 ; 1 ; 0 ;
++------------------------+--------------------+------------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; User-Specified and Inferred Latches ;
++----------------------------------------------------+-------------------------------------+------------------------+
+; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
++----------------------------------------------------+-------------------------------------+------------------------+
+; formula_fsm:FSM|start_delay ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes ;
+; Number of user-specified and inferred latches = 1 ; ; ;
++----------------------------------------------------+-------------------------------------+------------------------+
+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+
+
++------------------------------------------------------------+
+; Registers Removed During Synthesis ;
++---------------------------------------+--------------------+
+; Register name ; Reason for Removal ;
++---------------------------------------+--------------------+
+; delay:DEL0|state~5 ; Lost fanout ;
+; delay:DEL0|state~6 ; Lost fanout ;
+; Total Number of Removed Registers = 2 ; ;
++---------------------------------------+--------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 67 ;
+; Number of registers using Synchronous Clear ; 0 ;
+; Number of registers using Synchronous Load ; 15 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 26 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++---------------------------------------------------+
+; Inverted Register Statistics ;
++-----------------------------------------+---------+
+; Inverted Register ; Fan out ;
++-----------------------------------------+---------+
+; LFSR:LFSR0|COUNT[1] ; 10 ;
+; tick_50000:TICK0|count[14] ; 2 ;
+; tick_50000:TICK0|count[15] ; 2 ;
+; tick_50000:TICK0|count[0] ; 2 ;
+; tick_50000:TICK0|count[1] ; 2 ;
+; tick_50000:TICK0|count[2] ; 2 ;
+; tick_50000:TICK0|count[3] ; 2 ;
+; tick_50000:TICK0|count[6] ; 2 ;
+; tick_50000:TICK0|count[8] ; 2 ;
+; tick_50000:TICK0|count[9] ; 2 ;
+; Total number of inverted registers = 10 ; ;
++-----------------------------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed) ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
+; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |ex8|formula_fsm:FSM|count[11] ;
+; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |ex8|delay:DEL0|count[0] ;
+; 5:1 ; 7 bits ; 21 LEs ; 7 LEs ; 14 LEs ; Yes ; |ex8|delay:DEL0|count[9] ;
+; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |ex8|formula_fsm:FSM|Selector3 ;
+; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; No ; |ex8|delay:DEL0|Selector15 ;
+; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |ex8|delay:DEL0|Selector14 ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
+
+
++---------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
++----------------+-------+--------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+--------------------------------------+
+; NBIT ; 16 ; Signed Integer ;
++----------------+-------+--------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_2500:TICK1 ;
++----------------+-------+-------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+-------------------------------------+
+; NBIT ; 12 ; Signed Integer ;
++----------------+-------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
++------------------+-------+-----------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------+-------+-----------------------------------+
+; WAIT_TRIGGER ; 00 ; Unsigned Binary ;
+; LIGHT_UP_LEDS ; 01 ; Unsigned Binary ;
+; WAIT_FOR_TIMEOUT ; 10 ; Unsigned Binary ;
++------------------+-------+-----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------+
+; Parameter Settings for User Entity Instance: delay:DEL0 ;
++----------------+-------+--------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+--------------------------------+
+; BIT_SZ ; 14 ; Signed Integer ;
+; IDLE ; 00 ; Unsigned Binary ;
+; COUNTING ; 01 ; Unsigned Binary ;
+; TIME_OUT ; 10 ; Unsigned Binary ;
+; WAIT_LOW ; 11 ; Unsigned Binary ;
++----------------+-------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31" ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
+; oA[3] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
++-------+-------+----------+------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+------------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
++-------+-------+----------+------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
++-------+-------+----------+------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+------------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
++-------+-------+----------+------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
++-------+-------+----------+-----------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+-----------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
++-------+-------+----------+-----------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
++-------+-------+----------+-----------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+-------+----------+-----------------------------+
+; iW[3] ; Input ; Info ; Stuck at GND ;
++-------+-------+----------+-----------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD" ;
++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; B ; Input ; Warning ; Input port expression (7 bits) is smaller than the input port (16 bits) it drives. Extra input bit(s) "B[15..7]" will be connected to GND. ;
+; BCD_3 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; BCD_4 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "delay:DEL0" ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; N ; Input ; Warning ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives. Extra input bit(s) "N[13..7]" will be connected to GND. ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type ; Count ;
++-----------------------+-----------------------------+
+; arriav_ff ; 67 ;
+; ENA ; 12 ;
+; ENA SLD ; 14 ;
+; SLD ; 1 ;
+; plain ; 40 ;
+; arriav_lcell_comb ; 145 ;
+; arith ; 42 ;
+; 1 data inputs ; 42 ;
+; normal ; 103 ;
+; 0 data inputs ; 2 ;
+; 1 data inputs ; 13 ;
+; 2 data inputs ; 8 ;
+; 3 data inputs ; 6 ;
+; 4 data inputs ; 40 ;
+; 5 data inputs ; 5 ;
+; 6 data inputs ; 29 ;
+; boundary_port ; 36 ;
+; ; ;
+; Max LUT depth ; 6.00 ;
+; Average LUT depth ; 2.87 ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top ; 00:00:00 ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Wed Dec 07 12:21:11 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
+ Info (12023): Found entity 1: tick_50000 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v
+ Info (12023): Found entity 1: LFSR File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+ Info (12023): Found entity 1: hex_to_7seg File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
+ Info (12023): Found entity 1: counter_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v Line: 3
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+ Info (12023): Found entity 1: bin2bcd_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+ Info (12023): Found entity 1: add3_ge5 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
+ Info (12023): Found entity 1: formula_fsm File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
+ Info (12023): Found entity 1: delay File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v
+ Info (12023): Found entity 1: tick_2500 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex8.v
+ Info (12023): Found entity 1: ex8 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 1
+Info (12127): Elaborating entity "ex8" for the top level hierarchy
+Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 13
+Info (12128): Elaborating entity "tick_2500" for hierarchy "tick_2500:TICK1" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 14
+Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 15
+Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 39
+Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 58
+Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 58
+Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 16
+Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 17
+Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 24
+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 18
+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 26
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 19
+Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13024): Output pins are stuck at VCC or GND
+ Warning (13410): Pin "HEX2[1]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
+ Warning (13410): Pin "HEX2[2]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
+ Warning (13410): Pin "HEX2[6]" is stuck at VCC File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 2 registers lost all their fanouts during netlist optimizations.
+Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+ Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 3 input pin(s) that do not drive logic
+ Warning (15610): No output dependent on input pin "KEY[0]" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
+ Warning (15610): No output dependent on input pin "KEY[1]" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
+ Warning (15610): No output dependent on input pin "KEY[2]" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
+Info (21057): Implemented 184 device resources after synthesis - the final resource count might be different
+ Info (21058): Implemented 5 input pins
+ Info (21059): Implemented 31 output pins
+ Info (21061): Implemented 148 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
+ Info: Peak virtual memory: 895 megabytes
+ Info: Processing ended: Wed Dec 07 12:21:24 2016
+ Info: Elapsed time: 00:00:13
+ Info: Total CPU time (on all processors): 00:00:22
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg.
+
+
generated by cgit (git 2.34.1) at 2024-06-09 02:27:16 +0000