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diff --git a/part_2/ex9/output_files/ex9.asm.rpt b/part_2/ex9/output_files/ex9.asm.rpt
index 0da0660..abf1d89 100644
--- a/part_2/ex9/output_files/ex9.asm.rpt
+++ b/part_2/ex9/output_files/ex9.asm.rpt
@@ -1,92 +1,92 @@
-Assembler report for ex9
-Wed Dec 07 12:08:20 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Altera and sold by Altera or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Wed Dec 07 12:08:20 2016 ;
-; Revision Name ; ex9 ;
-; Top-level Entity Name ; ex9 ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+----------------------------------------------------------------------------+
-; Assembler Generated Files ;
-+----------------------------------------------------------------------------+
-; File Name ;
-+----------------------------------------------------------------------------+
-; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof ;
-+----------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------+
-; Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof ;
-+----------------+-------------------------------------------------------------------------------------+
-; Option ; Setting ;
-+----------------+-------------------------------------------------------------------------------------+
-; Device ; 5CSEMA5F31C6 ;
-; JTAG usercode ; 0x00B4D80C ;
-; Checksum ; 0x00B4D80C ;
-+----------------+-------------------------------------------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
- Info: Processing started: Wed Dec 07 12:08:12 2016
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 896 megabytes
- Info: Processing ended: Wed Dec 07 12:08:20 2016
- Info: Elapsed time: 00:00:08
- Info: Total CPU time (on all processors): 00:00:06
-
-
+Assembler report for ex9
+Wed Dec 07 12:08:20 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof
+ 6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Wed Dec 07 12:08:20 2016 ;
+; Revision Name ; ex9 ;
+; Top-level Entity Name ; ex9 ;
+; Family ; Cyclone V ;
+; Device ; 5CSEMA5F31C6 ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++----------------------------------------------------------------------------+
+; Assembler Generated Files ;
++----------------------------------------------------------------------------+
+; File Name ;
++----------------------------------------------------------------------------+
+; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof ;
++----------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof ;
++----------------+-------------------------------------------------------------------------------------+
+; Option ; Setting ;
++----------------+-------------------------------------------------------------------------------------+
+; Device ; 5CSEMA5F31C6 ;
+; JTAG usercode ; 0x00B4D80C ;
+; Checksum ; 0x00B4D80C ;
++----------------+-------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+ Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+ Info: Processing started: Wed Dec 07 12:08:12 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 896 megabytes
+ Info: Processing ended: Wed Dec 07 12:08:20 2016
+ Info: Elapsed time: 00:00:08
+ Info: Total CPU time (on all processors): 00:00:06
+
+
generated by cgit (git 2.34.1) at 2024-05-28 19:35:37 +0000