diff options
Diffstat (limited to 'part_2/ex9/verilog_files/delay.v')
-rw-r--r-- | part_2/ex9/verilog_files/delay.v | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/part_2/ex9/verilog_files/delay.v b/part_2/ex9/verilog_files/delay.v new file mode 100644 index 0000000..b94c715 --- /dev/null +++ b/part_2/ex9/verilog_files/delay.v @@ -0,0 +1,58 @@ +module delay(clk, N, trigger, time_out); + + parameter BIT_SZ = 14; + + input clk, trigger; + input [BIT_SZ-1:0] N; + output time_out; + + reg[BIT_SZ-1:0] count; + reg time_out; + + reg [1:0] state; + + parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11; + + initial begin + state = IDLE; + end + + always @ (posedge clk) + case(state) + IDLE: if(trigger == 1'b1) + begin + count <= N*128; + state <= COUNTING; + end + COUNTING: + begin + if(count == 1'b0) + begin + state <= TIME_OUT; + end + else + count <= count - 1'b1; + end + TIME_OUT: + begin + if(trigger == 1'b0) + state <= IDLE; + else + state <= WAIT_LOW; + end + WAIT_LOW: + if(trigger == 1'b0) + state <= IDLE; + default: ; + endcase + + always @ (*) + case(state) + IDLE: time_out = 1'b0; + COUNTING: time_out = 1'b0; + TIME_OUT: time_out = 1'b1; + WAIT_LOW: time_out = 1'b0; + default: ; + endcase + +endmodule
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