diff options
Diffstat (limited to 'part_2/ex9_final/verilog_files/counter_16.v')
| -rwxr-xr-x | part_2/ex9_final/verilog_files/counter_16.v | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/part_2/ex9_final/verilog_files/counter_16.v b/part_2/ex9_final/verilog_files/counter_16.v new file mode 100755 index 0000000..79c144c --- /dev/null +++ b/part_2/ex9_final/verilog_files/counter_16.v @@ -0,0 +1,31 @@ +module counter_16(clock, start, stop, count);
+
+ parameter BIT_SZ = 16;
+ input clock, start, stop;
+ output [BIT_SZ-1:0] count;
+
+ reg [BIT_SZ-1:0] count;
+
+ reg state;
+
+ parameter COUNTING = 1'b1, IDLE = 1'b0;
+
+ initial count = 0;
+ initial state = IDLE;
+
+ always @ (posedge clock)
+ case(state)
+ IDLE:
+ if(start == 1'b1)
+ begin
+ count = 0;
+ state = COUNTING;
+ end
+ COUNTING:
+ if(stop == 1'b1)
+ state <= IDLE;
+ else
+ count <= count + 1'b1;
+ endcase
+
+endmodule
\ No newline at end of file |