1 files changed, 0 insertions, 21 deletions
diff --git a/part_2/ex9_partially_working/verilog_files/counter_16.v.bak b/part_2/ex9_partially_working/verilog_files/counter_16.v.bak
deleted file mode 100755
index c0ec549..0000000
--- a/part_2/ex9_partially_working/verilog_files/counter_16.v.bak
+++ /dev/null
@@ -1,21 +0,0 @@
-`timescale 1ns / 100ps
-
-module counter_16(clock,enable,reset,count);
-
-	parameter BIT_SZ = 16;
-	input clock, enable, reset;
-	output [BIT_SZ-1:0] count;
-	
-	reg [BIT_SZ-1:0] count;
-	
-	initial count = 0;
-	
-	always @ (posedge clock)
-		begin
-			if(enable == 1'b1)
-				count <= count + 1'b1;
-			if(reset == 1'b1)
-				count <= 16'b0;
-		end
-			
-endmodule
-\ No newline at end of file